Lines Matching +full:line +full:- +full:ranges
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
26 i-cache-line-size = <32>;
27 d-cache-line-size = <32>;
28 cpu0_intc: interrupt-controller {
29 compatible = "riscv,cpu-intc";
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
36 compatible = "andestech,andescore-v5", "riscv";
41 mmu-type = "riscv,sv32";
42 clock-frequency = <60000000>;
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 cpu1_intc: interrupt-controller {
46 compatible = "riscv,cpu-intc";
47 #address-cells = <0>;
48 #interrupt-cells = <1>;
49 interrupt-controller;
53 compatible = "andestech,andescore-v5", "riscv";
58 mmu-type = "riscv,sv32";
59 clock-frequency = <60000000>;
60 i-cache-line-size = <32>;
61 d-cache-line-size = <32>;
62 cpu2_intc: interrupt-controller {
63 compatible = "riscv,cpu-intc";
64 #address-cells = <0>;
65 #interrupt-cells = <1>;
66 interrupt-controller;
70 compatible = "andestech,andescore-v5", "riscv";
75 mmu-type = "riscv,sv32";
76 clock-frequency = <60000000>;
77 i-cache-line-size = <32>;
78 d-cache-line-size = <32>;
79 cpu3_intc: interrupt-controller {
80 compatible = "riscv,cpu-intc";
81 #address-cells = <0>;
82 #interrupt-cells = <1>;
83 interrupt-controller;
87 compatible = "andestech,andescore-v5", "riscv";
92 mmu-type = "riscv,sv32";
93 clock-frequency = <60000000>;
94 i-cache-line-size = <32>;
95 d-cache-line-size = <32>;
96 cpu4_intc: interrupt-controller {
97 compatible = "riscv,cpu-intc";
98 #address-cells = <0>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
104 compatible = "andestech,andescore-v5", "riscv";
109 mmu-type = "riscv,sv32";
110 clock-frequency = <60000000>;
111 i-cache-line-size = <32>;
112 d-cache-line-size = <32>;
113 cpu5_intc: interrupt-controller {
114 compatible = "riscv,cpu-intc";
115 #address-cells = <0>;
116 #interrupt-cells = <1>;
117 interrupt-controller;
121 compatible = "andestech,andescore-v5", "riscv";
126 mmu-type = "riscv,sv32";
127 clock-frequency = <60000000>;
128 i-cache-line-size = <32>;
129 d-cache-line-size = <32>;
130 cpu6_intc: interrupt-controller {
131 compatible = "riscv,cpu-intc";
132 #address-cells = <0>;
133 #interrupt-cells = <1>;
134 interrupt-controller;
138 compatible = "andestech,andescore-v5", "riscv";
143 mmu-type = "riscv,sv32";
144 clock-frequency = <60000000>;
145 i-cache-line-size = <32>;
146 d-cache-line-size = <32>;
147 cpu7_intc: interrupt-controller {
148 compatible = "riscv,cpu-intc";
149 #address-cells = <0>;
150 #interrupt-cells = <1>;
151 interrupt-controller;
158 compatible = "mmio-sram";
163 #address-cells = <1>;
164 #size-cells = <1>;
166 ranges;
168 plic0: interrupt-controller@e4000000 {
169 compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
170 #address-cells = <1>;
171 #interrupt-cells = <2>;
172 interrupt-controller;
174 riscv,max-priority = <255>;
176 interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11
182 plic_sw: interrupt-controller@e6400000 {
183 compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
184 #address-cells = <1>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
188 riscv,max-priority = <255>;
190 interrupts-extended = <&cpu0_intc 3 &cpu1_intc 3
195 #size-cells = <0>;
196 mbox: mbox-controller@0 {
197 compatible = "andestech,mbox-plic-sw";
198 #mbox-cells = <1>;
206 interrupt-names = "mbox_9", "mbox_10", "mbox_11", "mbox_12",
212 interrupt-parent = <&plic_sw>;
218 compatible = "andestech,machine-timer";
220 interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
232 l2_cache: cache-controller@e0500000 {
241 reg-shift = <2>;
243 interrupt-parent = <&plic0>;
250 reg-shift = <2>;
252 interrupt-parent = <&plic0>;
260 interrupt-parent = <&plic0>;
261 clock-frequency = <60000000>;
270 interrupt-parent = <&plic0>;
271 wakeup-source;
279 interrupt-parent = <&plic0>;
280 gpio-controller;
282 #gpio-cells = <2>;
290 interrupt-parent = <&plic0>;
291 #address-cells = <1>;
292 #size-cells = <0>;
300 reg-names = "control", "mem";
302 interrupt-parent = <&plic0>;
305 dma-names = "tx", "rx";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 clock-frequency = <66000000>;
315 reg-names = "control";
317 interrupt-parent = <&plic0>;
320 dma-names = "tx", "rx";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 clock-frequency = <66000000>;
331 interrupt-parent = <&plic0>;
332 dma-channels = <8>;
333 dma-requests = <16>;
334 chain-transfer = <1>;
335 #dma-cells = <3>;
343 interrupt-parent = <&plic0>;
344 local-mac-address = [FC 8C EB 9B A6 51];
352 interrupt-parent = <&plic0>;
353 clock-frequency = <30000000>;
361 interrupt-parent = <&plic0>;
375 interrupt-parent = <&plic0>;
383 interrupt-parent = <&plic0>;
384 cap-sd-highspeed;
385 max-frequency = <100000000>;
386 clock-freq-min-max = <400000 100000000>;
387 fifo-depth = <0x10>;