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/Zephyr-latest/dts/arm64/nxp/
Dnxp_mimx95_a55.dtsi2 * Copyright 2024-2025 NXP
4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/imx95_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&gic>;
20 #address-cells = <1>;
[all …]
Dnxp_mimx93_a55.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu540.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 tlclk: tl-clk {
[all …]
Driscv32-fe310.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
[all …]
Driscv64-fu740.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
[all …]
/Zephyr-latest/dts/bindings/base/
Dbase.yaml12 - "okay" means the resource is operational and, for example,
14 - "disabled" means the resource is not operational and the system
19 - "ok" # Deprecated form
20 - "okay"
21 - "disabled"
22 - "reserved"
23 - "fail"
24 - "fail-sss"
27 type: string-array
41 most- to least-specific. Having additional values is useful when the
[all …]
/Zephyr-latest/dts/arm/silabs/xg29/
Dxg29.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg29-clock.h>
12 #include <dt-bindings/dma/silabs/xg29-dma.h>
17 zephyr,flash-controller = &msc;
23 #clock-cells = <0>;
24 compatible = "fixed-factor-clock";
[all …]
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e507xe.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-timer";
16 interrupt-names = "brk", "up", "trgcom", "cc";
19 is-advanced;
24 compatible = "gd,gd32-pwm";
26 #pwm-cells = <3>;
31 compatible = "gd,gd32-timer";
34 interrupt-names = "global";
41 compatible = "gd,gd32-pwm";
43 #pwm-cells = <3>;
[all …]
/Zephyr-latest/dts/arm/renesas/rz/rzg/
Dr9a08g045.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-m33";
26 clock-frequency = <250000000>;
[all …]
/Zephyr-latest/dts/arm64/fvp/
Dfvp-aemv8r.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm64/armv8-r.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-r82";
23 compatible = "arm,cortex-r82";
29 compatible = "arm,cortex-r82";
35 compatible = "arm,cortex-r82";
41 compatible = "arm,armv8-timer";
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsamc21.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 adc-1 = &adc1;
14 sercom-4 = &sercom4;
15 sercom-5 = &sercom5;
20 compatible = "atmel,sam0-adc";
23 interrupt-names = "resrdy";
25 clock-names = "GCLK", "MCLK";
26 atmel,assigned-clocks = <&gclk 0>;
27 atmel,assigned-clock-names = "GCLK";
30 #io-channel-cells = <1>;
[all …]
Dsame5x.dtsi6 * SPDX-License-Identifier: Apache-2.0
14 compatible = "atmel,sam0-gmac";
17 interrupt-names = "gmac";
20 num-queues = <1>;
21 local-mac-address = [00 00 00 00 00 00];
25 compatible = "atmel,sam-mdio";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "atmel,sam0-can";
37 interrupt-names = "int0", "int1";
[all …]
/Zephyr-latest/dts/bindings/mbox/
Dnordic,nrf-bellboard-rx.yaml2 # SPDX-License-Identifier: Apache-2.0
7 BELLBOARD provides support for inter-domain software signaling. It implements
15 compatible = "nordic,nrf-bellboard-rx";
19 interrupt-names = "irq2", "irq3";
20 nordic,interrupt-mapping = <0x0000000f 2>, <0x000000f0 3>;
21 #mbox-cells = <1>;
24 compatible: "nordic,nrf-bellboard-rx"
26 include: "nordic,nrf-bellboard-common.yaml"
32 interrupt-names:
35 nordic,interrupt-mapping:
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/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "starfive,fu74-g000";
21 clock-frequency = <0>;
[all …]
/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi2 * Copyright (c) 2019-2021 Linaro Limited
3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
8 sysclk: system-clock {
9 compatible = "fixed-clock";
10 clock-frequency = <25000000>;
11 #clock-cells = <0>;
15 compatible = "arm,cmsdk-gpio";
18 gpio-controller;
19 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dra8x1.dtsi2 * Copyright (c) 2024-2025 Renesas Electronics Corporation
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8.1-m.dtsi>
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
11 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m85";
23 #address-cells = <1>;
[all …]
/Zephyr-latest/tests/kernel/interrupt/
Dmultilevel_irq.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = < 0x1 >;
9 #size-cells = < 0x1 >;
11 test_cpu_intc: interrupt-controller {
12 compatible = "vnd,cpu-intc";
13 #address-cells = <0>;
14 #interrupt-cells = < 0x01 >;
15 interrupt-controller;
18 test_l1_irq: interrupt-controller@bbbbcccc {
21 interrupt-controller;
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
[all …]
Drp2350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
12 #include <zephyr/dt-bindings/reset/rp2350_reset.h>
21 die-temp0 = &die_temp;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp_rpu.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "arm,cortex-r5f";
23 rpu0_ipi: zynqmp-ipi@ff310000 {
25 compatible = "xlnx,zynqmp-ipi-mailbox";
26 #address-cells = <1>;
27 #size-cells = <1>;
30 reg-names = "host_ipi_reg";
33 local-ipi-id = <1>;
[all …]
Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
[all …]
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
[all …]
/Zephyr-latest/dts/arc/synopsys/
Darc_iot.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
24 intc: arcv2-intc {
25 compatible = "snps,arcv2-intc";
26 interrupt-controller;
27 #interrupt-cells = <2>;
31 compatible = "snps,arc-timer";
[all …]
/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
[all …]
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
[all …]

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