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Searched +full:internal +full:- +full:osc +full:- +full:disable (Results 1 – 18 of 18) sorted by relevance

/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
44 /* Enable and start internal 32KHz Silicon Oscillator */
50 /* disable XTAL high startup current */
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
72 /* Disable internal 32K VBAT clock source when VTR is off */
77 * Monotonic Counter least significant word (32-bit), read-only.
82 /* Monotonic Counter most significant word (32-bit). Read-Write */
/Zephyr-latest/samples/drivers/clock_control_xec/boards/
Dmec1501modular_assy6885.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
30 periph-32k-src:
35 xtal-single-ended:
39 clk32kmon-period-min:
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
154 #define XEC_CC_VBATR_CS_SO_EN BIT(0) /* enable and start silicon OSC */
157 #define XEC_CC_VBATR_CS_XTAL_DHC BIT(10) /* disable high XTAL startup current */
166 #define XEC_CC_VBATR_CS_PCS_VTR_VBAT_SO 0u /* VTR & VBAT use silicon OSC */
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/Zephyr-latest/soc/nxp/mcx/mcxw/
Dsoc.c2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
32 * Internal capatitor bank is required in order to use the more stable OSC32K source in clock_init()
36 .enableInternalCapBank = true, /* Internal capacitance bank is enabled */ in clock_init()
42 /* Disable ROSC Monitor, because switching the source would generate an expected error */ in clock_init()
53 /* Re-enable monitor */ in clock_init()
55 /* Disable the FRO32K to save power */ in clock_init()
98 /* OSC-RF / System Oscillator Configuration */ in clock_init()
105 /* Init OSC-RF / SOSC */ in clock_init()
109 /* Slow internal reference clock (SIRC) configuration */ in clock_init()
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/Zephyr-latest/soc/atmel/sam/sam4e/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
5 * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
8 * SPDX-License-Identifier: Apache-2.0
15 * This module provides routines to initialize and support board-level hardware
33 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
39 EFC->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
86 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
/Zephyr-latest/soc/atmel/sam/sam3x/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
5 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
7 * SPDX-License-Identifier: Apache-2.0
14 * This module provides routines to initialize and support board-level hardware
30 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
36 EFC0->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
37 EFC1->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
64 EFC0->EEFC_FMR = EEFC_FMR_FWS(4); in clock_init()
65 EFC1->EEFC_FMR = EEFC_FMR_FWS(4); in clock_init()
94 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
/Zephyr-latest/soc/atmel/sam/sam4s/
Dsoc.c2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
6 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
8 * SPDX-License-Identifier: Apache-2.0
15 * This module provides routines to initialize and support board-level hardware
33 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
39 EFC0->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
41 EFC1->EEFC_FMR = EEFC_FMR_FWS(0); in clock_init()
71 EFC0->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
73 EFC1->EEFC_FMR = EEFC_FMR_FWS(5); in clock_init()
92 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc.c3 * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
36 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
42 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
70 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
102 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
120 * DTCM is enabled by default at reset, therefore we have to disable in soc_reset_hook()
122 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
147 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
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/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc.c3 * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
34 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
40 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; in clock_init()
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; in clock_init()
99 /* Disable internal fast RC if we have an external crystal oscillator */ in clock_init()
117 * DTCM is enabled by default at reset, therefore we have to disable in soc_reset_hook()
119 * sys_cache*-functions can enable them, if requested by the in soc_reset_hook()
144 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { in soc_early_init_hook()
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/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpower.c4 * SPDX-License-Identifier: Apache-2.0
29 * If callbacks are present, the low power subsystem will disable
35 __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); in imxrt_clock_pm_callbacks_register()
36 lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; in imxrt_clock_pm_callbacks_register()
37 lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; in imxrt_clock_pm_callbacks_register()
38 if (callbacks->clock_lpm_init) { in imxrt_clock_pm_callbacks_register()
39 lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; in imxrt_clock_pm_callbacks_register()
50 * ERR050143: CCM: When improper low-power sequence is used, in lpm_set_sleep_mode_config()
57 * Low-Power mode. in lpm_set_sleep_mode_config()
58 * 3) Software should mask IRQ #41 right after CCM Low-Power mode in lpm_set_sleep_mode_config()
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Dlpm_rt1064.c4 * SPDX-License-Identifier: Apache-2.0
65 /* Wait until CCM internal handshake finish. */ in clock_set_mux()
66 while ((CCM->CDHIPR & ((1UL << busy_shift))) != 0UL) { in clock_set_mux()
87 /* Wait until CCM internal handshake finish. */ in clock_set_div()
88 while ((CCM->CDHIPR & ((uint32_t)(1UL << busy_shift))) != 0UL) { in clock_set_div()
102 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | in clock_init_usb1_pll()
103 CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); in clock_init_usb1_pll()
105 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | in clock_init_usb1_pll()
108 CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); in clock_init_usb1_pll()
110 while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) { in clock_init_usb1_pll()
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/Zephyr-latest/drivers/serial/
Duart_stellaris.c1 /* stellarisUartDrv.c - Stellaris UART driver */
6 * Copyright (c) 2013-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
15 * an 16550 in functionality, but is not register-compatible.
16 * It is also register-compatible with the UART found on TI CC2650 SoC,
19 * There is only support for poll-mode, so it can only be used with the printk
129 const struct uart_stellaris_config *config = dev->config; in baudrate_set()
132 /* upon reset, the system clock uses the internal OSC @ 12MHz */ in baudrate_set()
147 * those registers are 32-bit, but the reserved bits should be in baudrate_set()
150 config->uart->ibrd = (uint16_t)(brdi & 0xffff); /* 16 bits */ in baudrate_set()
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/Zephyr-latest/drivers/usb/udc/
Dudc_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
39 #define REG_GET_BIT(reg, field) (USB->reg & USB_##reg##_##field##_Msk)
40 #define REG_SET_BIT(reg, field) (USB->reg |= USB_##reg##_##field##_Msk)
41 #define REG_CLR_BIT(reg, field) (USB->reg &= ~USB_##reg##_##field##_Msk)
43 (USB->reg = (USB->reg & ~USB_##reg##_##field##_Msk) | (val << USB_##reg##_##field##_Pos))
123 #define EP0_OUT_STATE(data) (&data->ep_state[0][0])
124 #define EP0_IN_STATE(data) (&data->ep_state[1][0])
128 const struct udc_smartbond_config *config = data->dev->config; in usb_smartbond_dma_config()
129 const struct usb_smartbond_dma_config *dma_cfg = &config->dma_cfg; in usb_smartbond_dma_config()
130 struct dma_config *tx = &data->dma_data.tx_cfg; in usb_smartbond_dma_config()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
125 to disable abbreviations, any future python scripts or python code updates
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