Home
last modified time | relevance | path

Searched +full:divider +full:- +full:int +full:- +full:2 (Results 1 – 25 of 156) sorted by relevance

1234567

/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
26 divider-frac-0:
27 type: int
29 The fractional part of the divider for pwm slice 0.
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
42 int "Freescale K8x bus clock divider"
43 default 2
49 int "Freescale K8x FlexBus clock divider"
50 default 2
56 int "Freescale K8x flash clock divider"
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
31 #define R8A779F0_CLK_SD0H_DIV_SHIFT 2
82 static int r8a779f0_cpg_enable_disable_core(const struct device *dev, in r8a779f0_cpg_enable_disable_core()
85 int ret = 0; in r8a779f0_cpg_enable_disable_core()
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
[all …]
Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
28 #define R8A7795_CLK_SDH_DIV_SHIFT 2
74 static int r8a7795_cpg_enable_disable_core(const struct device *dev, in r8a7795_cpg_enable_disable_core()
77 int ret = 0; in r8a7795_cpg_enable_disable_core()
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
[all …]
Dclock_control_si32_apb.c4 * SPDX-License-Identifier: Apache-2.0
20 uint32_t divider; member
23 static int clock_control_si32_apb_on(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_on()
25 return -ENOTSUP; in clock_control_si32_apb_on()
28 static int clock_control_si32_apb_off(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_off()
31 return -ENOTSUP; in clock_control_si32_apb_off()
34 static int clock_control_si32_apb_get_rate(const struct device *dev, clock_control_subsys_t sys, in clock_control_si32_apb_get_rate()
37 const struct clock_control_si32_apb_config *config = dev->config; in clock_control_si32_apb_get_rate()
38 const int ret = clock_control_get_rate(config->clock_dev, NULL, rate); in clock_control_si32_apb_get_rate()
44 *rate /= config->divider; in clock_control_si32_apb_get_rate()
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
36 {DRP_ADDR_DAT_W, 2},
37 {DRP_ADDR_DAT_R, 2},
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
244 static int litex_clk_wait(uint32_t reg) in litex_clk_wait()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-auxpll.yaml2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
Dnxp,kinetis-mcg.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
22 Division factor is given as 2^fcrdiv.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
[all …]
/Zephyr-latest/dts/bindings/tcpc/
Dst,stm32-ucpd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
23 default: 2
24 type: int
26 - 1
27 - 2
28 - 4
[all …]
/Zephyr-latest/dts/bindings/adc/
Dadi,max32-adc.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
27 type: int
31 vref-mv:
32 type: int
[all …]
Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
18 type: int
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
24 type: int
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
30 "#io-channel-cells":
[all …]
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
18 type: int
19 description: clock divider for the converter
21 clk-source:
22 type: int
25 voltage-ref:
26 type: int
[all …]
/Zephyr-latest/dts/bindings/timer/
Dnuclei,systimer.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
22 type: int
24 clk-divider specifies the division ratio to the CPU frequency that
35 clock-frequency = <108000000>;
37 This property takes exponent of the power of 2.
41 division_ratio = 2^n
44 Setting clk-divider to 2 specifies the system timer uses the clock
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
[all …]
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer()
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
58 int ret = 0; in mdio_xmc4xxx_transfer()
[all …]
Dmdio_nxp_enet_qos.c4 * SPDX-License-Identifier: Apache-2.0
41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy()
47 static int do_transaction(struct mdio_transaction *mdio) in do_transaction()
49 enet_qos_t *base = mdio->base; in do_transaction()
51 int ret; in do_transaction()
53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction()
55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction()
56 base->MAC_MDIO_DATA = in do_transaction()
58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction()
60 } else if (mdio->op == MDIO_OP_C22_READ) { in do_transaction()
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dadi,adltc2990.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: [sensor-device.yaml, i2c-device.yaml]
12 temperature-format:
13 type: int
19 - 0
20 - 1
22 acquistion-format:
23 type: int
29 - 0
30 - 1
[all …]
Dinvensense,mpu9250.yaml2 # SPDX-License-Identifier: Apache-2.0
5 InvenSense MPU-9250 Nine-Axis (Gyro + Accelerometer + Compass). See more
6 info at https://www.invensense.com/products/motion-tracking/9-axis/mpu-9250/
10 include: [sensor-device.yaml, i2c-device.yaml]
13 irq-gpios:
14 type: phandle-array
16 The INT signal default configuration is active-high. The
21 gyro-sr-div:
22 type: int
25 Default gyrscope sample rate divider. This divider is only effective
[all …]
/Zephyr-latest/dts/bindings/can/
Despressif,esp32-twai.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Espressif ESP32 Two-Wire Automotive Interface (TWAI)
6 compatible: "espressif,esp32-twai"
8 include: [can-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 clkout-divider:
27 type: int
29 Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off.
31 Valid values are 1 or any even number from 2 to 14 for ESP32 and 2 to 490 for newer
[all …]
Datmel,sam-can.yaml3 compatible: "atmel,sam-can"
6 - name: bosch,m_can-base.yaml
7 - name: pinctrl-device.yaml
13 2 reg blocks needed; Register block for the MCAN configuration registers;
16 reg-names:
17 type: string-array
25 interrupt-names:
31 divider:
32 type: int
35 - 6
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c4 * SPDX-License-Identifier: Apache-2.0
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
38 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
53 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
54 PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */ in soc_early_init_hook()
[all …]
/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
28 type: int
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
34 type: int
39 child-binding:
40 child-binding:
[all …]
/Zephyr-latest/drivers/sensor/honeywell/hmc5883l/
Dhmc5883l.c4 * SPDX-License-Identifier: Apache-2.0
22 uint16_t divider) in hmc5883l_convert() argument
24 /* val = raw_val / divider */ in hmc5883l_convert()
25 val->val1 = raw_val / divider; in hmc5883l_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in hmc5883l_convert()
29 static int hmc5883l_channel_get(const struct device *dev, in hmc5883l_channel_get()
33 struct hmc5883l_data *drv_data = dev->data; in hmc5883l_channel_get()
36 hmc5883l_convert(val, drv_data->x_sample, in hmc5883l_channel_get()
37 hmc5883l_gain[drv_data->gain_idx]); in hmc5883l_channel_get()
39 hmc5883l_convert(val, drv_data->y_sample, in hmc5883l_channel_get()
[all …]
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.c4 * SPDX-License-Identifier: Apache-2.0
22 uint16_t divider) in lis3mdl_convert() argument
24 /* val = raw_val / divider */ in lis3mdl_convert()
25 val->val1 = raw_val / divider; in lis3mdl_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in lis3mdl_convert()
29 static int lis3mdl_channel_get(const struct device *dev, in lis3mdl_channel_get()
33 struct lis3mdl_data *drv_data = dev->data; in lis3mdl_channel_get()
37 lis3mdl_convert(val, drv_data->x_sample, in lis3mdl_channel_get()
39 lis3mdl_convert(val + 1, drv_data->y_sample, in lis3mdl_channel_get()
41 lis3mdl_convert(val + 2, drv_data->z_sample, in lis3mdl_channel_get()
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_renesas_ra_iic.c4 * SPDX-License-Identifier: Apache-2.0
59 uint32_t divider; member
65 static int i2c_ra_iic_configure(const struct device *dev, uint32_t dev_config) in i2c_ra_iic_configure()
67 struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data; in i2c_ra_iic_configure()
71 return -EIO; in i2c_ra_iic_configure()
76 data->fsp_config.rate = I2C_MASTER_RATE_STANDARD; in i2c_ra_iic_configure()
79 data->fsp_config.rate = I2C_MASTER_RATE_FAST; in i2c_ra_iic_configure()
82 data->fsp_config.rate = I2C_MASTER_RATE_FASTPLUS; in i2c_ra_iic_configure()
86 return -EIO; in i2c_ra_iic_configure()
90 calc_iic_master_clock_setting(dev, data->fsp_config.rate, in i2c_ra_iic_configure()
[all …]

1234567