Lines Matching +full:divider +full:- +full:int +full:- +full:2

1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20   pinctrl-0:
23   pinctrl-names:
26   channel-count:
27     type: int
31   vref-mv:
32     type: int
37     type: int
41   clock-source:
43     type: int
44     enum: [0, 1, 2, 3]
48       - 0: "ADI_MAX32_PRPH_CLK_SRC_PCLK" Peripheral clock
49       - 1: "ADI_MAX32_PRPH_CLK_SRC_EXTCLK" External Clock
50       - 2: "ADI_MAX32_PRPH_CLK_SRC_IBRO" Internal Baud Rate Oscillator
51       - 3: "ADI_MAX32_PRPH_CLK_SRC_ERFO" External Radio Frequency Oscillator
55   clock-divider:
57     type: int
58     enum: [1, 2, 4, 8, 16]
60       The clock divider divides the ADC source clock to set the ADC clock frequency as follows:
61         F_sar_clk = F_clock_source / clock divider
63   track-count:
65     type: int
69   idle-count:
71     type: int
75   "#io-channel-cells":
78 io-channel-cells:
79   - input