Lines Matching +full:divider +full:- +full:int +full:- +full:2
4 * SPDX-License-Identifier: Apache-2.0
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
38 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
53 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
54 PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */ in soc_early_init_hook()
62 /* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */ in soc_early_init_hook()
67 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
68 PLL_F(70) | /* VCO: 2 x (70 + 1) = 154 = 1872MHz */ in soc_early_init_hook()
69 PLL_Q(2) | /* output divider: VCO / 2^2 = 936MHz */ in soc_early_init_hook()
92 for (int i = 0; i < 256; i++) { in soc_early_init_hook()