| /Zephyr-latest/dts/bindings/pwm/ |
| D | raspberrypi,pico-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
23 If the value is set to 0 or this property is not defined when setting
26 divider-frac-0:
27 type: int
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| D | infineon,cat1-pwm.yaml | 4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "infineon,cat1-pwm"
10 include: [pwm-controller.yaml, pinctrl-device.yaml]
21 pinctrl-0:
30 pinctrl-0 = <&p1_1_pwm0_0>;
33 pinctrl-names:
37 type: int
39 divider-type:
40 type: int
42 Specifies which type of divider to use.
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| D | atmel,sam-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-pwm"
9 - name: base.yaml
10 - name: pwm-controller.yaml
11 - name: pinctrl-device.yaml
24 type: int
26 description: Clock prescaler at the input of the PWM (0 to 10)
28 divider:
29 type: int
31 description: Clock divider at the input of the PWM (1 to 255)
[all …]
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| /Zephyr-latest/drivers/mdio/ |
| D | mdio_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer()
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
58 int ret = 0; in mdio_xmc4xxx_transfer()
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| D | mdio_nxp_enet_qos.c | 4 * SPDX-License-Identifier: Apache-2.0
41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy()
47 static int do_transaction(struct mdio_transaction *mdio) in do_transaction()
49 enet_qos_t *base = mdio->base; in do_transaction()
51 int ret; in do_transaction()
53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction()
55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction()
56 base->MAC_MDIO_DATA = in do_transaction()
58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction()
59 goc_1_code = 0b0; in do_transaction()
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_si32_apb.c | 4 * SPDX-License-Identifier: Apache-2.0
20 uint32_t divider; member
23 static int clock_control_si32_apb_on(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_on()
25 return -ENOTSUP; in clock_control_si32_apb_on()
28 static int clock_control_si32_apb_off(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_off()
31 return -ENOTSUP; in clock_control_si32_apb_off()
34 static int clock_control_si32_apb_get_rate(const struct device *dev, clock_control_subsys_t sys, in clock_control_si32_apb_get_rate()
37 const struct clock_control_si32_apb_config *config = dev->config; in clock_control_si32_apb_get_rate()
38 const int ret = clock_control_get_rate(config->clock_dev, NULL, rate); in clock_control_si32_apb_get_rate()
44 *rate /= config->divider; in clock_control_si32_apb_get_rate()
[all …]
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| D | clock_control_r8a779f0_cpg_mssr.c | 7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
26 #define R8A779F0_CLK_SD0_DIV_MASK 0x3
27 #define R8A779F0_CLK_SD0_DIV_SHIFT 0
30 #define R8A779F0_CLK_SD0H_DIV_MASK 0x7
33 #define R8A779F0_CLK_SDSRC_DIV_MASK 0x3
61 RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_SD0H, 0x0870, CLK_SDSRC, RCAR_CPG_NONE),
62 RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_SD0, 0x0870, R8A779F0_CLK_SD0H, RCAR_CPG_NONE),
68 RCAR_CORE_CLK_INFO_ITEM(CLK_SDSRC, 0x08A4, CLK_PLL5, RCAR_CPG_NONE),
[all …]
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| D | clock_control_r8a7795_cpg_mssr.c | 6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
23 #define R8A7795_CLK_SD_DIV_MASK 0x3
24 #define R8A7795_CLK_SD_DIV_SHIFT 0
27 #define R8A7795_CLK_SDH_DIV_MASK 0x7
31 #define R8A7795_CLK_CANFD_DIV_MASK 0x3f
46 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD0H, 0x0074, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
47 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD0, 0x0074, R8A7795_CLK_SD0H, RCAR_CPG_MHZ(800)),
49 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD1H, 0x0078, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
[all …]
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| D | clock_control_renesas_cpg_mssr.c | 2 * Copyright (c) 2020-2022 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
33 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable) in rcar_cpg_mstp_clock_endisable()
55 return 0; in rcar_cpg_mstp_clock_endisable()
58 static int cmp_cpg_clk_info_table_items(const void *key, const void *element) in cmp_cpg_clk_info_table_items()
63 if (e->module == module) { in cmp_cpg_clk_info_table_items()
64 return 0; in cmp_cpg_clk_info_table_items()
65 } else if (e->module < module) { in cmp_cpg_clk_info_table_items()
68 return -1; in cmp_cpg_clk_info_table_items()
[all …]
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| D | clock_control_litex.c | 4 * SPDX-License-Identifier: Apache-2.0
46 for (i = 0; i <= CLKOUT_MAX; i++) { in litex_clk_regs_addr_init()
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
75 0b0001011111,
76 0b0001010111,
77 0b0001111011,
78 0b0001011011,
79 0b0001101011,
80 0b0001110011,
81 0b0001110011,
[all …]
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| D | clock_control_lpc11u6x.h | 4 * SPDX-License-Identifier: Apache-2.0
28 #define LPC11U6X_PDRUNCFG_MASK 0xC800
30 #define LPC11U6X_SYS_PLL_CLK_SEL_IRC 0x0
31 #define LPC11U6X_SYS_PLL_CLK_SEL_SYSOSC 0x1
33 #define LPC11U6X_FLASH_TIMING_REG 0x4003C010
34 #define LPC11U6X_FLASH_TIMING_3CYCLES 0x2
35 #define LPC11U6X_FLASH_TIMING_MASK 0x3
37 #define LPC11U6X_SYS_PLL_CTRL_MSEL_MASK 0x1F
39 #define LPC11U6X_SYS_PLL_CTRL_PSEL_MASK 0x3
41 #define LPC11U6X_MAIN_CLK_SRC_PLLOUT 0x3
[all …]
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam.c | 4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
33 static int sam_pwm_get_cycles_per_sec(const struct device *dev, in sam_pwm_get_cycles_per_sec()
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec()
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
43 return 0; in sam_pwm_get_cycles_per_sec()
46 static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel, in sam_pwm_set_cycles()
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles()
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | litex,clk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
33 litex,lock-timeout:
35 type: int
38 litex,drdy-timeout:
[all …]
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| D | nordic,nrf-auxpll.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
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| D | nxp,kinetis-mcg.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
28 Second Low-frequency Internal Reference Clock Divider.
[all …]
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| /Zephyr-latest/dts/bindings/adc/ |
| D | adi,max32-adc.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
27 type: int
31 vref-mv:
32 type: int
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| D | nxp,vf610-adc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
18 type: int
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
24 type: int
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
30 "#io-channel-cells":
[all …]
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| /Zephyr-latest/soc/nxp/rw/ |
| D | flexspi_clock_setup.c | 2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
18 * the FlexSPI with a new MUX source, only change the divider. This function
22 int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) in flexspi_clock_set_freq()
25 uint32_t divider; in flexspi_clock_set_freq() local
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
33 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
34 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
37 /* Cap divider to max value */ in flexspi_clock_set_freq()
[all …]
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| /Zephyr-latest/drivers/serial/ |
| D | uart_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
31 #define UART_PARITY_NONE ((uint8_t)0u)
36 #define UART_STOP_BIT_1 ((uint8_t)0u)
91 FLD_UART_RX_IRQ_TRIQ_LEV_OFFSET = 0,
97 FLD_UART_RX_BUF_CNT_OFFSET = 0,
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET; in uart_b91_get_tx_bufcnt()
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET; in uart_b91_get_rx_bufcnt()
127 } else if ((n % 2 == 0) || (n % 3 == 0)) { in uart_b91_is_prime()
128 return 0; in uart_b91_is_prime()
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| /Zephyr-latest/dts/bindings/timer/ |
| D | ambiq,stimer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
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| /Zephyr-latest/dts/bindings/tcpc/ |
| D | st,stm32-ucpd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
24 type: int
26 - 1
27 - 2
28 - 4
29 - 8
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_fwdgt_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
17 #define FWDGT_RELOAD_MAX (0xFFFU)
34 #define FWDGT_INITIAL_TIMEOUT DT_INST_PROP(0, initial_timeout_ms)
36 #if (FWDGT_INITIAL_TIMEOUT <= 0)
37 #error Must be initial-timeout > 0
41 #error Must be initial-timeout <= (256 * 4095 * 1000 / GD32_LOW_SPEED_IRC_FREQUENCY)
51 * @return 0 on success, -EINVAL if the timeout is out of range
53 static int gd32_fwdgt_calc_timeout(uint32_t timeout, uint32_t *prescaler, in gd32_fwdgt_calc_timeout()
56 uint16_t divider = 4U; in gd32_fwdgt_calc_timeout() local
57 uint8_t shift = 0U; in gd32_fwdgt_calc_timeout()
[all …]
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| /Zephyr-latest/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
28 type: int
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
34 type: int
37 A mask for channels that have internal counter, lsb is channel 0.
39 child-binding:
[all …]
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| /Zephyr-latest/soc/nxp/kinetis/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
35 Set this option to use the oscillator in low-power mode.
40 Set this option to use the oscillator in high-gain mode.
45 int "External oscillator frequency"
55 hex "PLL external reference divider"
56 range 0 0x18
57 default 0
63 hex "VCO 0 divider"
64 range 0 0x1F
65 default 0
[all …]
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| /Zephyr-latest/drivers/can/ |
| D | can_sam0.c | 7 * SPDX-License-Identifier: Apache-2.0
30 int divider; member
33 static int can_sam0_read_reg(const struct device *dev, uint16_t reg, uint32_t *val) in can_sam0_read_reg()
35 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_reg()
36 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_reg()
38 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam0_read_reg()
41 static int can_sam0_write_reg(const struct device *dev, uint16_t reg, uint32_t val) in can_sam0_write_reg()
43 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_write_reg()
44 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_write_reg()
49 val = 0; in can_sam0_write_reg()
[all …]
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