Lines Matching +full:divider +full:- +full:int +full:- +full:0

2  * Copyright 2022-2023 NXP
3  * SPDX-License-Identifier: Apache-2.0
18  * the FlexSPI with a new MUX source, only change the divider. This function
22 int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)  in flexspi_clock_set_freq()
25 	uint32_t divider;  in flexspi_clock_set_freq()  local
30 	root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) *  in flexspi_clock_set_freq()
33 	/* Select a divider based on root frequency.  in flexspi_clock_set_freq()
34 	 * if we can't get an exact divider, round down  in flexspi_clock_set_freq()
36 	divider = ((root_rate + (rate - 1)) / rate) - 1;  in flexspi_clock_set_freq()
37 	/* Cap divider to max value */  in flexspi_clock_set_freq()
38 	divider = MIN(divider, CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK);  in flexspi_clock_set_freq()
45 	set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL &  in flexspi_clock_set_freq()
46 			CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK), (divider + 1));  in flexspi_clock_set_freq()
53 	return 0;  in flexspi_clock_set_freq()
60 void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)  in set_flexspi_clock()  argument
62 	CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);  in set_flexspi_clock()
63 	CLKCTL0->FLEXSPIFCLKDIV |=  in set_flexspi_clock()
64 		CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */  in set_flexspi_clock()
65 	CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);  in set_flexspi_clock()
66 	while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) {  in set_flexspi_clock()