| /Zephyr-latest/soc/nxp/rw/ |
| D | flexspi_clock_setup.c | 2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
15 * @brief Set flexspi clock to given frequency
18 * the FlexSPI with a new MUX source, only change the divider. This function
19 * is used by the clock control framework to set the clock frequency of
25 uint32_t divider; in flexspi_clock_set_freq() local
29 /* Get the root clock rate: FlexSPI clock * divisor */ in flexspi_clock_set_freq()
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
33 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
34 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
39 from the system clock.
42 int "Freescale K8x bus clock divider"
45 This option specifies the divide value for the K8x bus clock from the
46 system clock.
49 int "Freescale K8x FlexBus clock divider"
52 This option specifies the divide value for the K8x FlexBus clock from the
53 system clock.
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| /Zephyr-latest/dts/bindings/clock/ |
| D | litex,clk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
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| D | raspberrypi,pico-pll.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "raspberrypi,pico-pll"
9 include: [base.yaml, fixed-factor-clock.yaml]
12 fb-div:
16 The feedback divider value.
19 post-div1:
23 The post clock divider.
26 post-div2:
30 The post clock divider.
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| D | nxp,kinetis-sim.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-sim"
14 pllfll-select:
17 description: pll/fll selection for clock system
19 er32k-select:
22 description: er32k selection for clock system
24 clkout-source:
26 description: clkout clock source
28 clkout-divider:
30 description: clkout divider
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| D | nxp,kinetis-mcg.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP Kinetis Multipurpose Clock generator (MCG) IP node
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
21 Internal Reference Clock Divider.
28 Second Low-frequency Internal Reference Clock Divider.
31 clock-cells:
32 - name
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| /Zephyr-latest/dts/bindings/i3c/ |
| D | nxp,mcux-i3c.yaml | 4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
32 description: TC clock divider for I3C
35 clk-divider-slow:
37 description: Slow clock divider for I3C
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| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
21 uint32_t divider; in flexspi_clock_set_freq() local
35 return -ENOTSUP; in flexspi_clock_set_freq()
39 /* Get clock root frequency */ in flexspi_clock_set_freq()
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
46 /* Cap divider to max value */ in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
21 uint32_t divider; in flexspi_clock_set_freq() local
35 return -ENOTSUP; in flexspi_clock_set_freq()
39 /* Get clock root frequency */ in flexspi_clock_set_freq()
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
46 /* Cap divider to max value */ in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm.h>
16 uint8_t divider; in flexspi_clock_set_freq() local
24 /* Get clock root frequency */ in flexspi_clock_set_freq()
33 /* Get clock root frequency */ in flexspi_clock_set_freq()
42 return -ENOTSUP; in flexspi_clock_set_freq()
44 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
45 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
47 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
48 /* Cap divider to max value */ in flexspi_clock_set_freq()
[all …]
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/ |
| D | flash_clock_setup.c | 3 * SPDX-License-Identifier: Apache-2.0
13 /* Enable FLEXSPI clock again */ in flash_deinit()
14 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in flash_deinit()
17 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
20 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && in flash_deinit()
21 (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { in flash_deinit()
24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
33 /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, in flash_init()
36 base->DLLCR[0] = 0x1U; in flash_init()
39 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()
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| D | soc.c | 2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
39 /* Core clock frequency: 198000000Hz */
49 /* OSC clock */
51 /* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 /* Denominator of the SYSPLL0 fractional loop divider is 1 */
59 /* OSC clock */
61 /* Numerator of the Audio PLL fractional loop divider is 0 */
63 /* Denominator of the Audio PLL fractional loop divider is 1 */
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_lpc11u6x.h | 4 * SPDX-License-Identifier: Apache-2.0
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source
77 volatile uint32_t main_clk_sel; /* Main clock select */
78 volatile uint32_t main_clk_uen; /* Main clock update */
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
81 volatile uint32_t sys_ahb_clk_ctrl; /* System clock control */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
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| D | clock_control_renesas_cpg_mssr.c | 2 * Copyright (c) 2020-2022 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
29 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ in rcar_cpg_write()
40 __ASSERT((bit < 32) && reg < ARRAY_SIZE(mstpcr), "Invalid module number for cpg clock: %d", in rcar_cpg_mstp_clock_endisable()
63 if (e->module == module) { in cmp_cpg_clk_info_table_items()
65 } else if (e->module < module) { in cmp_cpg_clk_info_table_items()
68 return -1; in cmp_cpg_clk_info_table_items()
75 struct rcar_cpg_mssr_data *data = dev->data; in rcar_cpg_find_clk_info_by_module_id()
77 struct cpg_clk_info_table *table = data->clk_info_table[domain]; in rcar_cpg_find_clk_info_by_module_id()
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| D | clock_control_r8a779f0_cpg_mssr.c | 5 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
45 /* Core Clock Outputs exported to DT */
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
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| /Zephyr-latest/dts/bindings/timer/ |
| D | ambiq,stimer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
29 6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
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| D | nuclei,systimer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
24 clk-divider specifies the division ratio to the CPU frequency that
25 clock used by the system timer.
27 different clock sources.
30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
32 In this case, the CPU clock frequency is defined in the CPU node
35 clock-frequency = <108000000>;
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam.c | 4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec()
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles()
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles()
56 return -EINVAL; in sam_pwm_set_cycles()
60 return -ENOTSUP; in sam_pwm_set_cycles()
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| /Zephyr-latest/dts/bindings/adc/ |
| D | nxp,vf610-adc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
28 3 clock divided by 8
30 "#io-channel-cells":
33 io-channel-cells:
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| D | adi,max32-adc.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
31 vref-mv:
41 clock-source:
46 Clock source to be used by the ADC peripheral. The following options
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| /Zephyr-latest/samples/sensor/lps22hh_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 7 * cannot tolerate high clock speed. So slow
8 * down the clock.
10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 7 * cannot tolerate high clock speed. So slow
8 * down the clock.
10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-latest/dts/bindings/can/ |
| D | atmel,sam0-can.yaml | 3 compatible: "atmel,sam0-can"
6 - name: bosch,m_can-base.yaml
7 - name: pinctrl-device.yaml
16 interrupt-names:
22 clock-names:
25 divider:
28 description: Clock divider of GLCK7 used by CAN as clock source
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| /Zephyr-latest/drivers/mdio/ |
| D | mdio_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
60 k_mutex_lock(&dev_data->mutex, K_FOREVER); in mdio_xmc4xxx_transfer()
62 if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) { in mdio_xmc4xxx_transfer()
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | soc_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
19 /* Common clock control device node for all NPCX series */
23 * @brief NPCX clock configuration structure
25 * Used to indicate the device's clock bus type and corresponding PWDWN_CTL
26 * register/bit to turn on/off its source clock.
34 /* Clock settings from pcc node */
37 /* Core clock prescaler */
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
39 /* APB1 clock divider */
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
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