4  * SPDX-License-Identifier: Apache-2.0
30 	uint8_t divider;  member
35 	{.divider = 8, .reg_val = 2},  {.divider = 13, .reg_val = 3},
36 	{.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 	{.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
54 	const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config;  in mdio_xmc4xxx_transfer()
55 	ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs;  in mdio_xmc4xxx_transfer()
56 	struct mdio_xmc4xxx_dev_data *const dev_data = dev->data;  in mdio_xmc4xxx_transfer()
60 	k_mutex_lock(&dev_data->mutex, K_FOREVER);  in mdio_xmc4xxx_transfer()
62 	if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) {  in mdio_xmc4xxx_transfer()
63 		ret = -EBUSY;  in mdio_xmc4xxx_transfer()
67 	reg = dev_data->reg_value_gmii_address;  in mdio_xmc4xxx_transfer()
70 		regs->GMII_DATA = data_write;  in mdio_xmc4xxx_transfer()
73 	regs->GMII_ADDRESS = reg | ETH_GMII_ADDRESS_MB_Msk |  in mdio_xmc4xxx_transfer()
77 	if (!WAIT_FOR((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0,  in mdio_xmc4xxx_transfer()
80 		ret = -ETIMEDOUT;  in mdio_xmc4xxx_transfer()
85 		*data_read = regs->GMII_DATA;  in mdio_xmc4xxx_transfer()
89 	k_mutex_unlock(&dev_data->mutex);  in mdio_xmc4xxx_transfer()
109 	/* this will enable the clock for ETH, which generates to MDIO clk  */  in mdio_xmc4xxx_bus_enable()
121 	struct mdio_xmc4xxx_dev_data *dev_data = dev->data;  in mdio_xmc4xxx_set_clock_divider()
125 		uint8_t divider = mdio_clock_divider[i].divider;  in mdio_xmc4xxx_set_clock_divider()  local
127 		uint32_t mdc_clk = eth_mac_clk / divider;  in mdio_xmc4xxx_set_clock_divider()
130 			LOG_DBG("Using MDC clock divider %d", divider);  in mdio_xmc4xxx_set_clock_divider()
131 			LOG_DBG("MDC clock %dHz", mdc_clk);  in mdio_xmc4xxx_set_clock_divider()
132 			dev_data->reg_value_gmii_address =  in mdio_xmc4xxx_set_clock_divider()
138 	return -EINVAL;  in mdio_xmc4xxx_set_clock_divider()
143 	const struct mdio_xmc4xxx_dev_config *dev_cfg = dev->config;  in mdio_xmc4xxx_initialize()
144 	struct mdio_xmc4xxx_dev_data *dev_data = dev->data;  in mdio_xmc4xxx_initialize()
148 	k_mutex_init(&dev_data->mutex);  in mdio_xmc4xxx_initialize()
150 	ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);  in mdio_xmc4xxx_initialize()
157 		LOG_ERR("Error setting MDIO clock divider");  in mdio_xmc4xxx_initialize()
158 		return -EINVAL;  in mdio_xmc4xxx_initialize()
161 	port_ctrl.mdio = dev_cfg->mdi_port_ctrl;  in mdio_xmc4xxx_initialize()
162 	ETH0_CON->CON = port_ctrl.raw;  in mdio_xmc4xxx_initialize()