Lines Matching +full:clock +full:- +full:divider

4  * SPDX-License-Identifier: Apache-2.0
19 /* Common clock control device node for all NPCX series */
23 * @brief NPCX clock configuration structure
25 * Used to indicate the device's clock bus type and corresponding PWDWN_CTL
26 * register/bit to turn on/off its source clock.
34 /* Clock settings from pcc node */
37 /* Core clock prescaler */
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
39 /* APB1 clock divider */
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
41 /* APB2 clock divider */
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
43 /* APB3 clock divider */
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
45 /* APB4 clock divider if supported */
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
50 #error "APB4 clock divider is not supported but defined in pcc node!"
54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
60 * NPCX7 and later series clock tree macros:
67 * - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
68 * - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
69 * - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.
71 /* Core domain clock */
73 /* Low Frequency clock */
76 /* FMUL clock */
78 #define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
80 #define FMCLK OFMCLK /* FMUL clock = OFMCLK */
83 /* APBs source clock */
86 /* AHB6 clock */
93 /* FIU clock divider */
108 /* I3C clock divider */
118 /* Get APB clock freq */
158 /* Clock prescaler configurations in different series */
175 * @brief Function to notify clock driver that backup the counter value of
176 * low-frequency timer before ec entered deep idle state.
181 * @brief Function to notify clock driver that compensate the counter value of
182 * system timer by low-frequency timer after ec left deep idle state.
200 * @param is_instant A boolean indicating 'Instant Wake-up' from deep idle is