Lines Matching +full:clock +full:- +full:divider

4  * SPDX-License-Identifier: Apache-2.0
70 	volatile uint32_t sys_pll_clk_sel;      /* System PLL clock source */
72 	volatile uint32_t usb_pll_clk_sel;      /* USB PLL clock source */
73 	volatile uint32_t usb_pll_clk_uen;      /* USB PLL clock source
77 	volatile uint32_t main_clk_sel;         /* Main clock select */
78 	volatile uint32_t main_clk_uen;         /* Main clock update */
79 	volatile uint32_t sys_ahb_clk_div;      /* System clock divider */
81 	volatile uint32_t sys_ahb_clk_ctrl;     /* System clock control */
83 	volatile uint32_t ssp0_clk_div;         /* SSP0 clock divider */
84 	volatile uint32_t usart0_clk_div;       /* USART0 clock divider */
85 	volatile uint32_t ssp1_clk_div;         /* SSP1 clock divider */
86 	volatile uint32_t frg_clk_div;          /* USART 1-4 fractional baud
87 						 * rate generator clock divider
90 	volatile uint32_t usb_clk_sel;          /* USB clock select */
91 	volatile uint32_t usb_clk_uen;          /* USB clock update */
92 	volatile uint32_t usb_clk_div;          /* USB clock divider */
96 	volatile uint32_t clk_out_div;          /* CLKOUT divider */
98 	volatile uint32_t uart_frg_div;         /* USART1-4 fractional
99 						 * generator divider
101 	volatile uint32_t uart_frg_mult;        /* USART1-4 fractional
110 	volatile uint32_t iocon_clk_div[7];     /* IOCON clock divider */
111 	volatile uint32_t bod_ctrl;             /* Brown-out detect control */
117 	volatile uint32_t usb_clk_ctrl;         /* USB clock control */
118 	volatile const uint32_t usb_clk_stat;   /* USB clock status */
120 	volatile uint32_t starterp0;            /* Start logic 0 int wake-up */
122 	volatile uint32_t starterp1;            /* Start logic 1 int wake-up */
124 	volatile uint32_t pd_sleep_cfg;         /* Deep-sleep power-down
127 	volatile uint32_t pd_awake_cfg;         /* Power-down states for
128 						 * wake-up from deep-sleep