| /Zephyr-latest/dts/bindings/i2c/ |
| D | nxp,lpi2c.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
14 bus-idle-timeout:
16 description: Bus idle timeout in nanoseconds
18 scl-gpios:
19 type: phandle-array
21 GPIO to which the I2C SCL signal is routed. This is only needed for I2C bus recovery
24 sda-gpios:
25 type: phandle-array
27 GPIO to which the I2C SDA signal is routed. This is only needed for I2C bus recovery
|
| /Zephyr-latest/drivers/timer/ |
| D | sam0_rtc_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Atmel SAM0 series RTC-based system timer
14 * In tickless mode, RTC counts continually in 32-bit mode and timeouts are
42 #define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
81 /* Tick value of the next timeout. */
90 * Waits for RTC bus synchronization.
94 /* Wait for bus synchronization... */ in rtc_sync()
96 while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) { in rtc_sync()
99 while (RTC0->SYNCBUSY.reg) { in rtc_sync()
106 * then - when bus synchronization completes - the COUNT register is read and
[all …]
|
| D | stm32_lptim_timer.c | 5 * SPDX-License-Identifier: Apache-2.0
40 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
42 {.bus = STM32_SRC_LSE, .enr = LPTIM1_SEL(3)}
54 * - system clock based on an LPTIM instance, clocked by LSI or LSE
55 * - prescaler is set to a 2^value from 1 (division of the LPTIM source clock by 1)
57 * - using LPTIM AutoReload capability to trig the IRQ (timeout irq)
58 * - when timeout irq occurs the counter is already reset
59 * - the maximum timeout duration is reached with the lptim_time_base value
60 * - with prescaler of 1, the max timeout (LPTIM_TIMEBASE) is 2 seconds:
62 * - with prescaler of 128, the max timeout (LPTIM_TIMEBASE) is 256 seconds:
[all …]
|
| /Zephyr-latest/drivers/eeprom/ |
| D | eeprom_at2x.c | 4 * SPDX-License-Identifier: Apache-2.0
32 #define EEPROM_AT25_STATUS_WIP BIT(0) /* Write-In-Process (RO) */
49 } bus; member
57 uint16_t timeout; member
70 const struct eeprom_at2x_config *config = dev->config; in eeprom_at2x_write_protect()
72 if (!config->wp_gpio.port) { in eeprom_at2x_write_protect()
76 return gpio_pin_set_dt(&config->wp_gpio, 1); in eeprom_at2x_write_protect()
81 const struct eeprom_at2x_config *config = dev->config; in eeprom_at2x_write_enable()
83 if (!config->wp_gpio.port) { in eeprom_at2x_write_enable()
87 return gpio_pin_set_dt(&config->wp_gpio, 0); in eeprom_at2x_write_enable()
[all …]
|
| /Zephyr-latest/drivers/i2c/ |
| D | i2c_npcx_controller.c | 4 * SPDX-License-Identifier: Apache-2.0
15 * support for a two-wire SMBus/I2C synchronous serial interface. The following
21 * +<----------------+<----------------------+
23 * +------+ +------------+ | +------- ----+ | +------- -------+ |
24 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
25 * | +------+ +------------+ +------------+ Yes +---------------+ |
27 * | +-----------+ |
28 * +--------------------------------------------| WAIT_STOP |<------------+
29 * STOP is completed +-----------+ Issue STOP
35 * +<-----------------+<---------------------+
[all …]
|
| D | i2c_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0
29 /* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
33 /* Line High Timeout is 2.5 ms (WAIT_LINE_HIGH_USEC * WAIT_LINE_HIGH_COUNT) */
73 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
74 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
75 * (16MHz/400KHz -2) = 0x0F + 0x17
76 * (16MHz/1MHz -2) = 0x05 + 0x09
105 (const struct i2c_xec_config *const) (dev->config); in i2c_xec_reset_config()
107 (struct i2c_xec_data *const) (dev->data); in i2c_xec_reset_config()
108 uint32_t ba = config->base_addr; in i2c_xec_reset_config()
[all …]
|
| D | i2c_esp32.c | 5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
31 #include "i2c-priv.h"
36 #define I2C_TRANSFER_TIMEOUT_MSEC 500 /* Transfer timeout period */
44 #define I2C_CLOCK_INVALID (-1)
49 I2C_STATUS_IDLE, /* idle status for current master command */
52 I2C_STATUS_TIMEOUT, /* I2C bus status error, and operation timeout */
151 const struct i2c_esp32_config *config = dev->config; in i2c_esp32_config_pin()
154 if (config->index >= SOC_I2C_NUM) { in i2c_esp32_config_pin()
156 return -EINVAL; in i2c_esp32_config_pin()
[all …]
|
| D | i2c_ite_enhance.c | 4 * SPDX-License-Identifier: Apache-2.0
23 #include "i2c-priv.h"
25 /* Start smbus session from idle state */
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
201 /* Bus busy */
231 struct i2c_enhance_data *data = dev->data; in i2c_parsing_return_value()
233 if (!data->err) { in i2c_parsing_return_value()
238 if (data->err == ETIMEDOUT) { in i2c_parsing_return_value()
239 return -ETIMEDOUT; in i2c_parsing_return_value()
243 if (data->err == E_HOSTA_ACK) { in i2c_parsing_return_value()
[all …]
|
| D | i2c_mchp_xec_v2.c | 5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
34 /* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
146 (struct i2c_xec_data *const) (dev->data); in i2c_ctl_wr()
147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_ctl_wr()
[all …]
|
| /Zephyr-latest/drivers/peci/ |
| D | peci_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0
74 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) { in peci_xec_pm_policy_state_lock_get()
82 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) { in peci_xec_pm_policy_state_lock_put()
91 const struct peci_xec_config * const cfg = dev->config; in peci_girq_enable()
93 mchp_xec_ecia_girq_src_en(cfg->girq, cfg->girq_pos); in peci_girq_enable()
98 const struct peci_xec_config * const cfg = dev->config; in peci_girq_status_clear()
100 mchp_soc_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); in peci_girq_status_clear()
105 const struct peci_xec_config * const cfg = dev->config; in peci_clr_slp_en()
107 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); in peci_clr_slp_en()
112 const struct peci_xec_config * const cfg = dev->config; in peci_girq_enable()
[all …]
|
| /Zephyr-latest/doc/services/input/ |
| D | gpio-kbd.rst | 1 .. _gpio-kbd:
6 The :dtcompatible:`gpio-kbd-matrix` driver supports a large variety of keyboard
21 .. figure:: no-diodes.svg
30 .. code-block:: devicetree
32 kbd-matrix {
33 compatible = "gpio-kbd-matrix";
34 row-gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>,
37 col-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>,
42 In this configuration the matrix scanning library enters idle mode once all
49 time can be tweaked by changing the ``settle-time-us`` property.
[all …]
|
| /Zephyr-latest/drivers/input/ |
| D | input_pinnacle.c | 4 * SPDX-License-Identifier: Apache-2.0
27 * Standard registers have 5-bit addresses, BIT[4:0], that range from
122 * timeout.
129 * timeout.
136 #define PINNACLE_SPI_FC 0xFC /* Auto-increment byte */
155 bool (*is_ready)(const struct pinnacle_bus *bus);
156 int (*write)(const struct pinnacle_bus *bus, uint8_t address, uint8_t value);
157 int (*seq_write)(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
159 int (*read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value);
160 int (*seq_read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *data,
[all …]
|
| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_mcr20a.c | 1 /* ieee802154_mcr20a.c - NXP MCR20A driver */
8 * SPDX-License-Identifier: Apache-2.0
113 #define MCR20A_OUTPUT_POWER_MIN (-35)
132 * Fc = 2405 + 5(k - 11) , k = 11,12,...,26
157 const struct mcr20a_config *config = dev->config; in z_mcr20a_read_reg()
178 if (spi_transceive_dt(&config->bus, &tx, &rx) == 0) { in z_mcr20a_read_reg()
179 return cmd_buf[len - 1]; in z_mcr20a_read_reg()
191 const struct mcr20a_config *config = dev->config; in z_mcr20a_write_reg()
207 return (spi_write_dt(&config->bus, &tx) == 0); in z_mcr20a_write_reg()
214 const struct mcr20a_config *config = dev->config; in z_mcr20a_write_burst()
[all …]
|
| D | ieee802154_dw1000.c | 4 * SPDX-License-Identifier: Apache-2.0
79 uint8_t rx_ns_sfd; /* non-standard SFD */
80 uint16_t rx_sfd_to; /* SFD timeout value (in symbols)
81 * (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
93 struct spi_dt_spec bus; member
120 .bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
136 .rx_sfd_to = (129 + 8 - 8),
158 struct dwt_context *ctx = dev->data; in dwt_spi_read()
159 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_spi_read()
187 if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) { in dwt_spi_read()
[all …]
|
| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | controller.rst | 13 Controller Area Network is a two-wire serial bus specified by the
14 Bosch CAN Specification, Bosch CAN with Flexible Data-Rate specification and the
15 ISO 11898-1:2003 standard.
21 CAN controllers can only initialize when the bus is in the idle (recessive)
26 The bit-timing as defined in ISO 11898-1:2003 looks as following:
37 * Prop_Seg: The signal propagation delay of the bus and other delays of the transceiver and node.
41 The bit-rate is calculated from the time of a time quantum and the values
45 The bit-rate is the inverse of the length of a single bit.
57 Phase_Seg1and Phase_Seg2) are initially set from the device-tree and can be
58 changed at run-time from the timing-API.
[all …]
|
| /Zephyr-latest/kernel/ |
| D | Kconfig | 3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
9 module-str = kernel
13 bool "Multi-threading" if ARCH_HAS_SINGLE_THREAD_SUPPORT
35 K_PRIO_COOP(0) to K_PRIO_COOP(CONFIG_NUM_COOP_PRIORITIES - 1)
39 -CONFIG_NUM_COOP_PRIORITIES to -1
48 The extra one is for the idle thread, which must run at the lowest
58 to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1.
66 The extra one is for the idle thread, which must run at the lowest
71 default -2 if !PREEMPT_ENABLED
[all …]
|
| /Zephyr-latest/subsys/sd/ |
| D | sd.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* Idle all cards on bus. Can be used to clear errors on cards */
32 return sdhc_request(card->sdhc, &cmd, NULL); in sd_idle()
38 * - CMD0 (SD reset)
39 * - CMD8 (SD voltage check)
60 ret = sdhc_request(card->sdhc, &cmd, NULL); in sd_send_interface_condition()
66 if (card->host_props.is_spi) { in sd_send_interface_condition()
78 return -ENOTSUP; in sd_send_interface_condition()
81 card->flags |= SD_SDHC_FLAG; in sd_send_interface_condition()
91 __ASSERT_NO_MSG(card->host_props.is_spi); in sd_enable_crc()
[all …]
|
| /Zephyr-latest/drivers/i3c/ |
| D | i3c_mcux.c | 6 * SPDX-License-Identifier: Apache-2.0
98 /** Condvar for waiting for bus to be in IDLE state */
125 * @brief Read a register and test for bit matches with timeout.
129 * @param reg Pointer to 32-bit Register.
132 * @param timeout_us Timeout in microsecond before bailing out.
135 * @retval -ETIMEDOUT Timedout without matching.
143 * quickly (some sub-microseconds) so no extra in reg32_poll_timeout()
147 return -ETIMEDOUT; in reg32_poll_timeout()
155 * @param reg Pointer to 32-bit Register.
173 * @param reg Pointer to 32-bit register.
[all …]
|
| D | i3c_npcx.c | 4 * SPDX-License-Identifier: Apache-2.0
99 #define NPCX_I3C_CHK_TIMEOUT_US 10000 /* Timeout for checking register status */
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
163 uint8_t ppbaud; /* Push-Pull high period */
164 uint8_t pplow; /* Push-Pull low period */
165 uint8_t odhpp; /* Open-Drain high period */
166 uint8_t odbaud; /* Open-Drain low period */
[all …]
|
| /Zephyr-latest/drivers/usb/uhc/ |
| D | uhc_max3421e.c | 4 * SPDX-License-Identifier: Apache-2.0
63 const struct max3421e_config *config = dev->config; in max3421e_read_hirq()
92 ret = spi_transceive_dt(&config->dt_spi, &tx, &rx); in max3421e_read_hirq()
94 priv->hirq = hirq; in max3421e_read_hirq()
113 const struct max3421e_config *config = dev->config; in max3421e_write_byte()
125 return spi_write_dt(&config->dt_spi, &tx); in max3421e_write_byte()
133 const struct max3421e_config *config = dev->config; in max3421e_write()
151 return spi_write_dt(&config->dt_spi, &tx); in max3421e_write()
156 struct uhc_data *data = dev->data; in max3421e_lock()
158 return k_mutex_lock(&data->mutex, K_FOREVER); in max3421e_lock()
[all …]
|
| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32h7x.c | 4 * SPDX-License-Identifier: Apache-2.0
41 #error Flash driver on M4 requires the DT property bank2-flash-size
71 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { in write_optb()
73 return -EIO; in write_optb()
76 if ((regs->OPTCR & mask) == value) { in write_optb()
83 LOG_ERR("Err flash no idle"); in write_optb()
87 regs->OPTCR = (regs->OPTCR & ~mask) | value; in write_optb()
89 regs->OPTCR |= FLASH_OPTCR_PG_OPT; in write_optb()
91 regs->OPTCR |= FLASH_OPTCR_OPTSTART; in write_optb()
98 LOG_ERR("Err flash no idle"); in write_optb()
[all …]
|
| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.5.rst | 38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
|
| D | release-notes-2.3.rst | 17 * The kernel timeout API has been overhauled to be flexible and configurable,
18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
[all …]
|
| /Zephyr-latest/dts/common/nordic/ |
| D | nrf54h20.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
[all …]
|
| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_esp32.c | 4 * SPDX-License-Identifier: Apache-2.0
80 uint8_t bus_width; /* Bus width used by the slot (can change during execution) */
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
106 * maximum bus frequency in high speed (HS) mode is 50 MHz.
107 * Note: for non-UHS-1 cards, HS mode is optional.
140 sdio_hw->ctrl.dma_enable = 1; in sdmmc_host_dma_init()
[all …]
|
