Lines Matching +full:bus +full:- +full:idle +full:- +full:timeout
4 * SPDX-License-Identifier: Apache-2.0
74 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) { in peci_xec_pm_policy_state_lock_get()
82 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) { in peci_xec_pm_policy_state_lock_put()
91 const struct peci_xec_config * const cfg = dev->config; in peci_girq_enable()
93 mchp_xec_ecia_girq_src_en(cfg->girq, cfg->girq_pos); in peci_girq_enable()
98 const struct peci_xec_config * const cfg = dev->config; in peci_girq_status_clear()
100 mchp_soc_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); in peci_girq_status_clear()
105 const struct peci_xec_config * const cfg = dev->config; in peci_clr_slp_en()
107 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); in peci_clr_slp_en()
112 const struct peci_xec_config * const cfg = dev->config; in peci_girq_enable()
114 MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos); in peci_girq_enable()
119 const struct peci_xec_config * const cfg = dev->config; in peci_girq_status_clear()
121 MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos); in peci_girq_status_clear()
136 /* Wait until PECI bus becomes idle. in check_bus_idle()
137 * Note that when IDLE bit in the status register changes, HW do not in check_bus_idle()
140 while (!(regs->STATUS2 & MCHP_PECI_STS2_IDLE)) { in check_bus_idle()
142 delay_cnt--; in check_bus_idle()
145 LOG_WRN("Bus is busy"); in check_bus_idle()
146 return -EBUSY; in check_bus_idle()
154 const struct peci_xec_config * const cfg = dev->config; in peci_xec_configure()
155 struct peci_xec_data * const data = dev->data; in peci_xec_configure()
156 struct peci_regs * const regs = cfg->regs; in peci_xec_configure()
159 data->bitrate = bitrate; in peci_xec_configure()
162 regs->CONTROL = MCHP_PECI_CTRL_PD; in peci_xec_configure()
166 regs->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK; in peci_xec_configure()
167 regs->OPT_BIT_TIME_MSB = ((value >> OPT_BIT_TIME_MSB_OFS) & in peci_xec_configure()
171 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_configure()
178 const struct peci_xec_config * const cfg = dev->config; in peci_xec_disable()
179 struct peci_regs * const regs = cfg->regs; in peci_xec_disable()
190 NVIC_ClearPendingIRQ(cfg->irq_num); in peci_xec_disable()
191 irq_disable(cfg->irq_num); in peci_xec_disable()
193 regs->CONTROL |= MCHP_PECI_CTRL_PD; in peci_xec_disable()
200 const struct peci_xec_config * const cfg = dev->config; in peci_xec_enable()
201 struct peci_regs * const regs = cfg->regs; in peci_xec_enable()
203 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_enable()
208 irq_enable(cfg->irq_num); in peci_xec_enable()
215 const struct peci_xec_config * const cfg = dev->config; in peci_xec_bus_recovery()
216 struct peci_xec_data * const data = dev->data; in peci_xec_bus_recovery()
217 struct peci_regs * const regs = cfg->regs; in peci_xec_bus_recovery()
221 regs->CONTROL = MCHP_PECI_CTRL_PD | MCHP_PECI_CTRL_RST; in peci_xec_bus_recovery()
229 regs->CONTROL &= ~MCHP_PECI_CTRL_RST; in peci_xec_bus_recovery()
231 peci_xec_configure(dev, data->bitrate); in peci_xec_bus_recovery()
234 regs->CONTROL |= MCHP_PECI_CTRL_FRST; in peci_xec_bus_recovery()
240 const struct peci_xec_config * const cfg = dev->config; in peci_xec_write()
241 struct peci_xec_data * const data = dev->data; in peci_xec_write()
242 struct peci_regs * const regs = cfg->regs; in peci_xec_write()
246 struct peci_buf *tx_buf = &msg->tx_buffer; in peci_xec_write()
247 struct peci_buf *rx_buf = &msg->rx_buffer; in peci_xec_write()
250 if (regs->STATUS2 & MCHP_PECI_STS2_WFF) { in peci_xec_write()
252 return -EIO; in peci_xec_write()
255 regs->CONTROL &= ~MCHP_PECI_CTRL_FRST; in peci_xec_write()
258 regs->WR_DATA = msg->addr; in peci_xec_write()
259 regs->WR_DATA = tx_buf->len; in peci_xec_write()
260 regs->WR_DATA = rx_buf->len; in peci_xec_write()
263 if (tx_buf->len) { in peci_xec_write()
264 regs->WR_DATA = msg->cmd_code; in peci_xec_write()
265 for (i = 0; i < tx_buf->len - 1; i++) { in peci_xec_write()
266 if (!(regs->STATUS2 & MCHP_PECI_STS2_WFF)) { in peci_xec_write()
267 regs->WR_DATA = tx_buf->buf[i]; in peci_xec_write()
272 /* Check bus is idle before starting a new transfer */ in peci_xec_write()
278 regs->CONTROL |= MCHP_PECI_CTRL_TXEN; in peci_xec_write()
283 if (k_sem_take(&data->tx_lock, PECI_IO_DELAY * tx_buf->len)) { in peci_xec_write()
284 return -ETIMEDOUT; in peci_xec_write()
287 /* In worst case, overall timeout will be 1msec (100 * 10usec) */ in peci_xec_write()
290 while (!(regs->STATUS1 & MCHP_PECI_STS1_EOF)) { in peci_xec_write()
292 wait_timeout_cnt--; in peci_xec_write()
294 LOG_WRN("Tx timeout"); in peci_xec_write()
295 data->timeout_retries++; in peci_xec_write()
297 if (data->timeout_retries > PECI_TIMEOUT_RETRIES) { in peci_xec_write()
303 return -ETIMEDOUT; in peci_xec_write()
307 data->timeout_retries = 0; in peci_xec_write()
314 const struct peci_xec_config * const cfg = dev->config; in peci_xec_read()
315 struct peci_regs * const regs = cfg->regs; in peci_xec_read()
321 struct peci_buf *rx_buf = &msg->rx_buffer; in peci_xec_read()
325 for (i = 0; i < (rx_buf->len + PECI_FCS_LEN); i++) { in peci_xec_read()
326 /* Worst case timeout will be 1msec (100 * 10usec) */ in peci_xec_read()
329 while (regs->STATUS2 & MCHP_PECI_STS2_RFE) { in peci_xec_read()
331 wait_timeout_cnt--; in peci_xec_read()
334 return -ETIMEDOUT; in peci_xec_read()
340 tx_fcs = regs->RD_DATA; in peci_xec_read()
344 if (msg->cmd_code == PECI_CMD_PING) { in peci_xec_read()
345 rx_buf->buf[0] = tx_fcs; in peci_xec_read()
348 } else if (i == (rx_buf->len + 1)) { in peci_xec_read()
350 rx_buf->buf[i-1] = regs->RD_DATA; in peci_xec_read()
353 rx_buf->buf[i-1] = regs->RD_DATA; in peci_xec_read()
359 if (rx_buf->len != bytes_rcvd) { in peci_xec_read()
360 LOG_INF("Incomplete %x vs %x", bytes_rcvd, rx_buf->len); in peci_xec_read()
363 /* Once write-read transaction is complete, ensure bus is idle in peci_xec_read()
376 const struct peci_xec_config * const cfg = dev->config; in peci_xec_transfer()
377 struct peci_regs * const regs = cfg->regs; in peci_xec_transfer()
381 struct peci_xec_data *data = dev->data; in peci_xec_transfer()
396 if (msg->rx_buffer.len || (msg->cmd_code == PECI_CMD_PING)) { in peci_xec_transfer()
404 if (regs->STATUS1 & MCHP_PECI_STS1_EOF) { in peci_xec_transfer()
405 regs->STATUS1 |= MCHP_PECI_STS1_EOF; in peci_xec_transfer()
408 /* Check for error conditions and perform bus recovery if necessary */ in peci_xec_transfer()
409 err_val = regs->ERROR; in peci_xec_transfer()
420 LOG_ERR("PECI bus error"); in peci_xec_transfer()
424 LOG_DBG("PECI sts1 %x", regs->STATUS1); in peci_xec_transfer()
425 LOG_DBG("PECI sts2 %x", regs->STATUS2); in peci_xec_transfer()
427 /* ERROR is a clear-on-write register, need to clear errors in peci_xec_transfer()
431 regs->ERROR = err_val; in peci_xec_transfer()
433 ret = -EIO; in peci_xec_transfer()
447 const struct peci_xec_config *const devcfg = dev->config; in peci_xec_pm_action()
448 struct peci_regs * const regs = devcfg->regs; in peci_xec_pm_action()
454 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in peci_xec_pm_action()
456 ecs_regs->PECI_DIS = 0x00u; in peci_xec_pm_action()
459 regs->CONTROL &= ~MCHP_PECI_CTRL_PD; in peci_xec_pm_action()
462 regs->CONTROL |= MCHP_PECI_CTRL_PD; in peci_xec_pm_action()
466 ecs_regs->PECI_DIS = 0x01u; in peci_xec_pm_action()
469 * not define pinctrl-1 for this node. in peci_xec_pm_action()
471 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in peci_xec_pm_action()
472 if (ret == -ENOENT) { /* pinctrl-1 does not exist. */ in peci_xec_pm_action()
477 ret = -ENOTSUP; in peci_xec_pm_action()
488 struct peci_xec_config * const cfg = dev->config; in peci_xec_isr()
489 struct peci_xec_data * const data = dev->data; in peci_xec_isr()
490 struct peci_regs * const regs = cfg->regs; in peci_xec_isr()
491 uint8_t peci_error = regs->ERROR; in peci_xec_isr()
492 uint8_t peci_status2 = regs->STATUS2; in peci_xec_isr()
497 regs->ERROR = peci_error; in peci_xec_isr()
502 k_sem_give(&data->tx_lock); in peci_xec_isr()
520 const struct peci_xec_config * const cfg = dev->config; in peci_xec_init()
521 struct peci_regs * const regs = cfg->regs; in peci_xec_init()
524 int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in peci_xec_init()
532 k_sem_init(&data->tx_lock, 0, 1); in peci_xec_init()
537 ecs_regs->PECI_DIS = 0x00u; in peci_xec_init()
540 regs->CONTROL |= MCHP_PECI_CTRL_RST; in peci_xec_init()
542 regs->CONTROL &= ~MCHP_PECI_CTRL_RST; in peci_xec_init()
546 regs->INT_EN1 = (MCHP_PECI_IEN1_EREN | MCHP_PECI_IEN1_EIEN); in peci_xec_init()
549 regs->INT_EN2 |= MCHP_PECI_IEN2_ENWFE; in peci_xec_init()
551 regs->INT_EN2 |= MCHP_PECI_IEN2_ENRFF; in peci_xec_init()
553 regs->CONTROL |= MCHP_PECI_CTRL_MIEN; in peci_xec_init()
556 IRQ_CONNECT(cfg->irq_num, in peci_xec_init()