4  * SPDX-License-Identifier: Apache-2.0
11  * @brief Atmel SAM0 series RTC-based system timer
14  * In tickless mode, RTC counts continually in 32-bit mode and timeouts are
42 #define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
81 /* Tick value of the next timeout. */
90  * Waits for RTC bus synchronization.
94 	/* Wait for bus synchronization... */  in rtc_sync()
96 	while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) {  in rtc_sync()
99 	while (RTC0->SYNCBUSY.reg) {  in rtc_sync()
106  * then - when bus synchronization completes - the COUNT register is read and
112 	RTC0->READREQ.reg = RTC_READREQ_RREQ;  in rtc_count()
115 	return RTC0->COUNT.reg;  in rtc_count()
123 	RTC0->INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;  in rtc_reset()
125 	RTC0->INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;  in rtc_reset()
129 	RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;  in rtc_reset()
131 	RTC0->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;  in rtc_reset()
138 	RTC0->CTRL.bit.SWRST = 1;  in rtc_reset()
139 	while (RTC0->CTRL.bit.SWRST) {  in rtc_reset()
142 	RTC0->CTRLA.bit.SWRST = 1;  in rtc_reset()
143 	while (RTC0->CTRLA.bit.SWRST) {  in rtc_reset()
153 	uint16_t status = RTC0->INTFLAG.reg;  in rtc_isr()
155 	RTC0->INTFLAG.reg = status;  in rtc_isr()
163 		uint32_t ticks = (count - rtc_last) / CYCLES_PER_TICK;  in rtc_isr()
174 			sys_clock_announce(rtc_counter - rtc_last);  in rtc_isr()
185 void sys_clock_set_timeout(int32_t ticks, bool idle)  in sys_clock_set_timeout()  argument
187 	ARG_UNUSED(idle);  in sys_clock_set_timeout()
192 	ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS);  in sys_clock_set_timeout()
194 	/* Compute number of RTC cycles until the next timeout. */  in sys_clock_set_timeout()
196 	uint32_t timeout = ticks * CYCLES_PER_TICK + count % CYCLES_PER_TICK;  in sys_clock_set_timeout()  local
199 	timeout = DIV_ROUND_UP(timeout, CYCLES_PER_TICK) * CYCLES_PER_TICK;  in sys_clock_set_timeout()
201 	if (timeout < TICK_THRESHOLD) {  in sys_clock_set_timeout()
202 		timeout += CYCLES_PER_TICK;  in sys_clock_set_timeout()
206 	RTC0->COMP[0].reg = count + timeout;  in sys_clock_set_timeout()
236 	return (rtc_count() - rtc_last) / CYCLES_PER_TICK;  in sys_clock_elapsed()
238 	return rtc_counter - rtc_last;  in sys_clock_elapsed()
254 	MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;  in sys_clock_driver_init()
255 	OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;  in sys_clock_driver_init()
257 	/* Set up bus clock and GCLK generator. */  in sys_clock_driver_init()
258 	PM->APBAMASK.reg |= PM_APBAMASK_RTC;  in sys_clock_driver_init()
259 	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN  in sys_clock_driver_init()
263 	while (GCLK->STATUS.bit.SYNCBUSY) {  in sys_clock_driver_init()
277 	/* Configure RTC with 32-bit mode, configured prescaler and MATCHCLR. */  in sys_clock_driver_init()
297 	RTC0->CTRL.reg = ctrl;  in sys_clock_driver_init()
299 	RTC0->CTRLA.reg = ctrl;  in sys_clock_driver_init()
304 	RTC0->INTENSET.reg = RTC_MODE0_INTENSET_CMP0;  in sys_clock_driver_init()
306 	/* Non-tickless mode uses comparator together with MATCHCLR. */  in sys_clock_driver_init()
308 	RTC0->COMP[0].reg = CYCLES_PER_TICK;  in sys_clock_driver_init()
309 	RTC0->INTENSET.reg = RTC_MODE0_INTENSET_OVF;  in sys_clock_driver_init()
317 	RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE;  in sys_clock_driver_init()
319 	RTC0->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;  in sys_clock_driver_init()