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/Zephyr-latest/dts/bindings/shi/
Dnuvoton,npcx-shi.yaml4 description: Nuvoton, NPCX Serial Host Interface (SHI) node
6 compatible: "nuvoton,npcx-shi"
8 include: [pinctrl-device.yaml, shi-device.yaml]
21 shi-cs-wui:
28 shi-cs-wui = <&wui_io53>;
Dnuvoton,npcx-shi-enhanced.yaml4 description: Nuvoton, NPCX Serial Host Interface (SHI) node
6 compatible: "nuvoton,npcx-shi-enhanced"
8 include: [pinctrl-device.yaml, shi-device.yaml, "nuvoton,npcx-shi.yaml"]
Dite,it8xxx2-shi.yaml4 description: ITE, IT8XXX2 Serial Host Interface (SHI) node
6 compatible: "ite,it8xxx2-shi"
8 include: [pinctrl-device.yaml, shi-device.yaml]
21 Pin used as chip-select for the SHI interface. Change in level will
/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
DKconfig7 DT_CHOSEN_SHI_BACKEND := zephyr,host-cmd-shi-backend
27 bool "Host commands support using SHI"
50 prompt "SHI driver"
55 bool "SHI by Nuvoton"
60 This option enables the driver for SHI backend in the
64 bool "SHI by ITE"
68 This option enables the driver for SHI backend in the
84 Workaround the issue "CSnFE and CSnRE bits of EVSTATS2 Register (SHI)"
110 prompt "SHI driver"
Dec_host_cmd_backend_shi_npcx.c25 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "Invalid number of NPCX SHI peripherals");
46 * Timeout to wait for SHI request packet
50 * That's as slow as we would practically want to run the SHI interface, since running it slower
88 /* SHI not enabled (initial state, and when chipset is off) */
111 /* Serial Host Interface (SHI) base address */
145 * With the workaround, CS assertion/de-assertion INT and SHI module's INT come from
156 /* SHI device instance */
216 * Valid offset of SHI output buffer to write.
236 * This routine write SHI next half output buffer from msg buffer
258 * This routine read SHI input buffer to msg buffer until
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Dec_host_cmd_backend_shi_ite.c22 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "Invalid number of ITE SHI peripherals");
35 "SHI max request size is too big");
37 "SHI max response size is too big");
56 * Structure shi_it8xxx2_cfg is about the setting of SHI,
60 /* SHI alternate configuration */
86 /* SHI device instance */
434 /* Set the pin to SHI alternate function. */ in shi_ite_init_registers()
437 LOG_ERR("Failed to configure SHI pins"); in shi_ite_init_registers()
463 LOG_ERR("Failed to configure SHI CS pin"); in shi_ite_init()
476 LOG_ERR("Failed to configure SHI CS interrupt"); in shi_ite_init()
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx9m7fb.dtsi45 * Raising the interrupt priority of the MIWU group, which owns SHI CS, to the same as
46 * SHI's priority.
/Zephyr-latest/doc/services/device_mgmt/
Dec_host_cmd.rst32 SHI (Serial Host Interface) is different to this because it is used only for communication with a
33 host. SHI does not have API itself, thus the backend and peripheral driver layers are combined into
43 as it is done for SHI. That means a SPI backend has to be implemented per chip family. However, it
85 * SHI - ITE and NPCX
99 * ``zephyr,host-cmd-shi-backend``
/Zephyr-latest/include/zephyr/mgmt/ec_host_cmd/
Dbackend.h124 * @brief Get the SHI NPCX Host Command backend pointer
126 * @retval the SHI NPCX backend pointer
131 * @brief Get the SHI ITE Host Command backend pointer
133 * @retval the SHI ITE backend pointer
Dec_host_cmd.h270 * When the application configures the zephyr,host-cmd-espi-backend/zephyr,host-cmd-shi-backend/
/Zephyr-latest/dts/bindings/misc/
Dnuvoton,npcx-booter-variant.yaml12 The host interface type (LPC/eSPI/SHI) is configured by booter
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx7.dtsi277 shi0: shi@4000f000 {
278 compatible = "nuvoton,npcx-shi";
285 shi-cs-wui =<&wui_io53>;
Dnpcx9.dtsi317 shi0: shi@4000f000 {
318 compatible = "nuvoton,npcx-shi";
325 shi-cs-wui =<&wui_io53>;
Dnpcx4.dtsi339 shi0: shi@4000f000 {
340 compatible = "nuvoton,npcx-shi-enhanced";
347 shi-cs-wui =<&wui_io53>;
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-pinctrl.dtsi13 /omit-if-no-ref/ vhif_espi_shi_sl: devctl-vhif-1p8v-espi-shi {
331 /* SHI peripheral interfaces */
332 /omit-if-no-ref/ shi_gp46_47_53_55: periph-shi {
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-pinctrl.dtsi14 /omit-if-no-ref/ vhif_espi_shi_sl: devctl-vhif-1p8v-espi-shi {
340 /* SHI peripheral interfaces */
341 /omit-if-no-ref/ shi_gp46_47_53_55: periph-shi {
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-pinctrl.dtsi13 /omit-if-no-ref/ vhif_espi_shi_sl: devctl-vhif-1p8v-espi-shi {
363 /* SHI peripheral interfaces */
364 /omit-if-no-ref/ shi_gp46_47_53_55: periph-shi {
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h1682 /* SHI (Serial Host Interface) registers */
1685 /* 0x001: SHI Configuration 1 */
1687 /* 0x002: SHI Configuration 2 */
1694 /* 0x007: SHI Capabilities */
1703 /* 0x00C: SHI Configuration 3 */
1705 /* 0x00D: SHI Configuration 4 */
1707 /* 0x00E: SHI Configuration 5 */
1713 /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
1724 /* SHI register fields */
/Zephyr-latest/dts/riscv/ite/
Dit8xxx2.dtsi443 shi0: shi@f03a00 {
444 compatible = "ite,it8xxx2-shi";
Dit8xxx2-pinctrl-map.dtsi345 /* SHI alternate function */
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst1312 - :dtcompatible:`ite,it8xxx2-shi`
1351 - :dtcompatible:`nuvoton,npcx-shi`