1/* 2 * Copyright (c) 2022 ITE Corporation. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h> 8 9&pinctrl { 10 /* ADC alternate function */ 11 adc0_ch0_gpi0_default: adc0_ch0_gpi0_default { 12 pinmuxs = <&pinctrli 0 IT8XXX2_ALT_FUNC_1>; 13 }; 14 adc0_ch1_gpi1_default: adc0_ch1_gpi1_default { 15 pinmuxs = <&pinctrli 1 IT8XXX2_ALT_FUNC_1>; 16 }; 17 adc0_ch2_gpi2_default: adc0_ch2_gpi2_default { 18 pinmuxs = <&pinctrli 2 IT8XXX2_ALT_FUNC_1>; 19 }; 20 adc0_ch3_gpi3_default: adc0_ch3_gpi3_default { 21 pinmuxs = <&pinctrli 3 IT8XXX2_ALT_FUNC_1>; 22 }; 23 adc0_ch4_gpi4_default: adc0_ch4_gpi4_default { 24 pinmuxs = <&pinctrli 4 IT8XXX2_ALT_FUNC_1>; 25 }; 26 adc0_ch5_gpi5_default: adc0_ch5_gpi5_default { 27 pinmuxs = <&pinctrli 5 IT8XXX2_ALT_FUNC_1>; 28 }; 29 adc0_ch6_gpi6_default: adc0_ch6_gpi6_default { 30 pinmuxs = <&pinctrli 6 IT8XXX2_ALT_FUNC_1>; 31 }; 32 adc0_ch7_gpi7_default: adc0_ch7_gpi7_default { 33 pinmuxs = <&pinctrli 7 IT8XXX2_ALT_FUNC_1>; 34 }; 35 adc0_ch13_gpl0_default: adc0_ch13_gpl0_default { 36 pinmuxs = <&pinctrll 0 IT8XXX2_ALT_FUNC_1>; 37 }; 38 adc0_ch14_gpl1_default: adc0_ch14_gpl1_default { 39 pinmuxs = <&pinctrll 1 IT8XXX2_ALT_FUNC_1>; 40 }; 41 adc0_ch15_gpl2_default: adc0_ch15_gpl2_default { 42 pinmuxs = <&pinctrll 2 IT8XXX2_ALT_FUNC_1>; 43 }; 44 adc0_ch16_gpl3_default: adc0_ch16_gpl3_default { 45 pinmuxs = <&pinctrll 3 IT8XXX2_ALT_FUNC_1>; 46 }; 47 48 /* I2C alternate function */ 49 i2c0_clk_gpb3_default: i2c0_clk_gpb3_default { 50 pinmuxs = <&pinctrlb 3 IT8XXX2_ALT_FUNC_1>; 51 }; 52 i2c0_data_gpb4_default: i2c0_data_gpb4_default { 53 pinmuxs = <&pinctrlb 4 IT8XXX2_ALT_FUNC_1>; 54 }; 55 i2c1_clk_gpc1_default: i2c1_clk_gpc1_default { 56 pinmuxs = <&pinctrlc 1 IT8XXX2_ALT_FUNC_1>; 57 }; 58 i2c1_data_gpc2_default: i2c1_data_gpc2_default { 59 pinmuxs = <&pinctrlc 2 IT8XXX2_ALT_FUNC_1>; 60 }; 61 i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { 62 pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_1>; 63 }; 64 i2c2_data_gpf7_default: i2c2_data_gpf7_default { 65 pinmuxs = <&pinctrlf 7 IT8XXX2_ALT_FUNC_1>; 66 }; 67 i2c3_clk_gph1_default: i2c3_clk_gph1_default { 68 pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_3>; 69 }; 70 i2c3_data_gph2_default: i2c3_data_gph2_default { 71 pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_3>; 72 }; 73 i2c3_clk_gpf2_default: i2c3_clk_gpf2_default { 74 pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_FUNC_4>; 75 }; 76 i2c3_data_gpf3_default: i2c3_data_gpf3_default { 77 pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_FUNC_4>; 78 }; 79 i2c4_clk_gpe0_default: i2c4_clk_gpe0_default { 80 pinmuxs = <&pinctrle 0 IT8XXX2_ALT_FUNC_3>; 81 }; 82 i2c4_data_gpe7_default: i2c4_data_gpe7_default { 83 pinmuxs = <&pinctrle 7 IT8XXX2_ALT_FUNC_3>; 84 }; 85 i2c5_clk_gpa4_default: i2c5_clk_gpa4_default { 86 pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_3>; 87 }; 88 i2c5_data_gpa5_default: i2c5_data_gpa5_default { 89 pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_3>; 90 }; 91 92 /* I2C alternate function (Mapping pins for IT82XX2) */ 93 i2c2_clk_gpc7_default: i2c2_clk_gpc7_default { 94 pinmuxs = <&pinctrlc 7 IT8XXX2_ALT_FUNC_4>; 95 }; 96 i2c2_data_gpd0_default: i2c2_data_gpd0_default { 97 pinmuxs = <&pinctrld 0 IT8XXX2_ALT_FUNC_4>; 98 }; 99 i2c3_clk_gpb2_default: i2c3_clk_gpb2_default { 100 pinmuxs = <&pinctrlb 2 IT8XXX2_ALT_FUNC_3>; 101 }; 102 i2c3_data_gpb5_default: i2c3_data_gpb5_default { 103 pinmuxs = <&pinctrlb 5 IT8XXX2_ALT_FUNC_3>; 104 }; 105 i2c5_clk_gpe1_default: i2c5_clk_gpe1_default { 106 pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_3>; 107 }; 108 i2c5_data_gpe2_default: i2c5_data_gpe2_default { 109 pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_3>; 110 }; 111 112 /* Keyboard alternate function */ 113 ksi0_default: ksi0_default { 114 pinmuxs = <&pinctrlksi 0 IT8XXX2_ALT_FUNC_1>; 115 bias-pull-up; 116 }; 117 ksi1_default: ksi1_default { 118 pinmuxs = <&pinctrlksi 1 IT8XXX2_ALT_FUNC_1>; 119 bias-pull-up; 120 }; 121 ksi2_default: ksi2_default { 122 pinmuxs = <&pinctrlksi 2 IT8XXX2_ALT_FUNC_1>; 123 bias-pull-up; 124 }; 125 ksi3_default: ksi3_default { 126 pinmuxs = <&pinctrlksi 3 IT8XXX2_ALT_FUNC_1>; 127 bias-pull-up; 128 }; 129 ksi4_default: ksi4_default { 130 pinmuxs = <&pinctrlksi 4 IT8XXX2_ALT_FUNC_1>; 131 bias-pull-up; 132 }; 133 ksi5_default: ksi5_default { 134 pinmuxs = <&pinctrlksi 5 IT8XXX2_ALT_FUNC_1>; 135 bias-pull-up; 136 }; 137 ksi6_default: ksi6_default { 138 pinmuxs = <&pinctrlksi 6 IT8XXX2_ALT_FUNC_1>; 139 bias-pull-up; 140 }; 141 ksi7_default: ksi7_default { 142 pinmuxs = <&pinctrlksi 7 IT8XXX2_ALT_FUNC_1>; 143 bias-pull-up; 144 }; 145 kso0_default: kso0_default { 146 pinmuxs = <&pinctrlksol 0 IT8XXX2_ALT_FUNC_1>; 147 drive-open-drain; 148 bias-pull-up; 149 }; 150 kso1_default: kso1_default { 151 pinmuxs = <&pinctrlksol 1 IT8XXX2_ALT_FUNC_1>; 152 drive-open-drain; 153 bias-pull-up; 154 }; 155 kso2_default: kso2_default { 156 pinmuxs = <&pinctrlksol 2 IT8XXX2_ALT_FUNC_1>; 157 drive-open-drain; 158 bias-pull-up; 159 }; 160 kso3_default: kso3_default { 161 pinmuxs = <&pinctrlksol 3 IT8XXX2_ALT_FUNC_1>; 162 drive-open-drain; 163 bias-pull-up; 164 }; 165 kso4_default: kso4_default { 166 pinmuxs = <&pinctrlksol 4 IT8XXX2_ALT_FUNC_1>; 167 drive-open-drain; 168 bias-pull-up; 169 }; 170 kso5_default: kso5_default { 171 pinmuxs = <&pinctrlksol 5 IT8XXX2_ALT_FUNC_1>; 172 drive-open-drain; 173 bias-pull-up; 174 }; 175 kso6_default: kso6_default { 176 pinmuxs = <&pinctrlksol 6 IT8XXX2_ALT_FUNC_1>; 177 drive-open-drain; 178 bias-pull-up; 179 }; 180 kso7_default: kso7_default { 181 pinmuxs = <&pinctrlksol 7 IT8XXX2_ALT_FUNC_1>; 182 drive-open-drain; 183 bias-pull-up; 184 }; 185 kso8_default: kso8_default { 186 pinmuxs = <&pinctrlksoh 0 IT8XXX2_ALT_FUNC_1>; 187 drive-open-drain; 188 bias-pull-up; 189 }; 190 kso9_default: kso9_default { 191 pinmuxs = <&pinctrlksoh 1 IT8XXX2_ALT_FUNC_1>; 192 drive-open-drain; 193 bias-pull-up; 194 }; 195 kso10_default: kso10_default { 196 pinmuxs = <&pinctrlksoh 2 IT8XXX2_ALT_FUNC_1>; 197 drive-open-drain; 198 bias-pull-up; 199 }; 200 kso11_default: kso11_default { 201 pinmuxs = <&pinctrlksoh 3 IT8XXX2_ALT_FUNC_1>; 202 drive-open-drain; 203 bias-pull-up; 204 }; 205 kso12_default: kso12_default { 206 pinmuxs = <&pinctrlksoh 4 IT8XXX2_ALT_FUNC_1>; 207 drive-open-drain; 208 bias-pull-up; 209 }; 210 kso13_default: kso13_default { 211 pinmuxs = <&pinctrlksoh 5 IT8XXX2_ALT_FUNC_1>; 212 drive-open-drain; 213 bias-pull-up; 214 }; 215 kso14_default: kso14_default { 216 pinmuxs = <&pinctrlksoh 6 IT8XXX2_ALT_FUNC_1>; 217 drive-open-drain; 218 bias-pull-up; 219 }; 220 kso15_default: kso15_default { 221 pinmuxs = <&pinctrlksoh 7 IT8XXX2_ALT_FUNC_1>; 222 drive-open-drain; 223 bias-pull-up; 224 }; 225 kso16_gpc3_default: kso16_gpc3_default { 226 pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>; 227 bias-pull-up; 228 }; 229 kso17_gpc5_default: kso17_gpc5_default { 230 pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_1>; 231 bias-pull-up; 232 }; 233 234 /* Keyboard sleep function */ 235 ksi0_sleep: ksi0_sleep { 236 pinmuxs = <&pinctrlksi 0 IT8XXX2_ALT_DEFAULT>; 237 }; 238 ksi1_sleep: ksi1_sleep { 239 pinmuxs = <&pinctrlksi 1 IT8XXX2_ALT_DEFAULT>; 240 }; 241 ksi2_sleep: ksi2_sleep { 242 pinmuxs = <&pinctrlksi 2 IT8XXX2_ALT_DEFAULT>; 243 }; 244 ksi3_sleep: ksi3_sleep { 245 pinmuxs = <&pinctrlksi 3 IT8XXX2_ALT_DEFAULT>; 246 }; 247 ksi4_sleep: ksi4_sleep { 248 pinmuxs = <&pinctrlksi 4 IT8XXX2_ALT_DEFAULT>; 249 }; 250 ksi5_sleep: ksi5_sleep { 251 pinmuxs = <&pinctrlksi 5 IT8XXX2_ALT_DEFAULT>; 252 }; 253 ksi6_sleep: ksi6_sleep { 254 pinmuxs = <&pinctrlksi 6 IT8XXX2_ALT_DEFAULT>; 255 }; 256 ksi7_sleep: ksi7_sleep { 257 pinmuxs = <&pinctrlksi 7 IT8XXX2_ALT_DEFAULT>; 258 }; 259 kso0_sleep: kso0_sleep { 260 pinmuxs = <&pinctrlksol 0 IT8XXX2_ALT_DEFAULT>; 261 }; 262 kso1_sleep: kso1_sleep { 263 pinmuxs = <&pinctrlksol 1 IT8XXX2_ALT_DEFAULT>; 264 }; 265 kso2_sleep: kso2_sleep { 266 pinmuxs = <&pinctrlksol 2 IT8XXX2_ALT_DEFAULT>; 267 }; 268 kso3_sleep: kso3_sleep { 269 pinmuxs = <&pinctrlksol 3 IT8XXX2_ALT_DEFAULT>; 270 }; 271 kso4_sleep: kso4_sleep { 272 pinmuxs = <&pinctrlksol 4 IT8XXX2_ALT_DEFAULT>; 273 }; 274 kso5_sleep: kso5_sleep { 275 pinmuxs = <&pinctrlksol 5 IT8XXX2_ALT_DEFAULT>; 276 }; 277 kso6_sleep: kso6_sleep { 278 pinmuxs = <&pinctrlksol 6 IT8XXX2_ALT_DEFAULT>; 279 }; 280 kso7_sleep: kso7_sleep { 281 pinmuxs = <&pinctrlksol 7 IT8XXX2_ALT_DEFAULT>; 282 }; 283 kso8_sleep: kso8_sleep { 284 pinmuxs = <&pinctrlksoh 0 IT8XXX2_ALT_DEFAULT>; 285 }; 286 kso9_sleep: kso9_sleep { 287 pinmuxs = <&pinctrlksoh 1 IT8XXX2_ALT_DEFAULT>; 288 }; 289 kso10_sleep: kso10_sleep { 290 pinmuxs = <&pinctrlksoh 2 IT8XXX2_ALT_DEFAULT>; 291 }; 292 kso11_sleep: kso11_sleep { 293 pinmuxs = <&pinctrlksoh 3 IT8XXX2_ALT_DEFAULT>; 294 }; 295 kso12_sleep: kso12_sleep { 296 pinmuxs = <&pinctrlksoh 4 IT8XXX2_ALT_DEFAULT>; 297 }; 298 kso13_sleep: kso13_sleep { 299 pinmuxs = <&pinctrlksoh 5 IT8XXX2_ALT_DEFAULT>; 300 }; 301 kso14_sleep: kso14_sleep { 302 pinmuxs = <&pinctrlksoh 6 IT8XXX2_ALT_DEFAULT>; 303 }; 304 kso15_sleep: kso15_sleep { 305 pinmuxs = <&pinctrlksoh 7 IT8XXX2_ALT_DEFAULT>; 306 }; 307 kso16_gpc3_sleep: kso16_gpc3_sleep { 308 pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_DEFAULT>; 309 }; 310 kso17_gpc5_sleep: kso17_gpc5_sleep { 311 pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_DEFAULT>; 312 }; 313 314 /* PECI alternate function */ 315 peci_gpf6_default: peci_gpf6_default { 316 pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_3>; 317 }; 318 319 /* PWM alternate function */ 320 pwm0_gpa0_default: pwm0_gpa0_default { 321 pinmuxs = <&pinctrla 0 IT8XXX2_ALT_FUNC_1>; 322 }; 323 pwm1_gpa1_default: pwm1_gpa1_default { 324 pinmuxs = <&pinctrla 1 IT8XXX2_ALT_FUNC_1>; 325 }; 326 pwm2_gpa2_default: pwm2_gpa2_default { 327 pinmuxs = <&pinctrla 2 IT8XXX2_ALT_FUNC_1>; 328 }; 329 pwm3_gpa3_default: pwm3_gpa3_default { 330 pinmuxs = <&pinctrla 3 IT8XXX2_ALT_FUNC_1>; 331 }; 332 pwm4_gpa4_default: pwm4_gpa4_default { 333 pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_1>; 334 }; 335 pwm5_gpa5_default: pwm5_gpa5_default { 336 pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_1>; 337 }; 338 pwm6_gpa6_default: pwm6_gpa6_default { 339 pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_1>; 340 }; 341 pwm7_gpa7_default: pwm7_gpa7_default { 342 pinmuxs = <&pinctrla 7 IT8XXX2_ALT_FUNC_1>; 343 }; 344 345 /* SHI alternate function */ 346 shi_mosi_gpm0_default: shi_mosi_gpm0_default { 347 pinmuxs = <&pinctrlm 0 IT8XXX2_ALT_FUNC_1>; 348 }; 349 shi_miso_gpm1_default: shi_miso_gpm1_default { 350 pinmuxs = <&pinctrlm 1 IT8XXX2_ALT_FUNC_1>; 351 }; 352 shi_clk_gpm4_default: shi_clk_gpm4_default { 353 pinmuxs = <&pinctrlm 4 IT8XXX2_ALT_FUNC_1>; 354 }; 355 shi_cs_gpm5_default: shi_cs_gpm5_default { 356 pinmuxs = <&pinctrlm 5 IT8XXX2_ALT_FUNC_1>; 357 }; 358 359 /* Tachometer alternate function */ 360 tach0a_gpd6_default: tach0a_gpd6_default { 361 pinmuxs = <&pinctrld 6 IT8XXX2_ALT_FUNC_1>; 362 }; 363 tach0b_gpj2_default: tach0b_gpj2_default { 364 pinmuxs = <&pinctrlj 2 IT8XXX2_ALT_FUNC_3>; 365 }; 366 tach1a_gpd7_default: tach1a_gpd7_default { 367 pinmuxs = <&pinctrld 7 IT8XXX2_ALT_FUNC_1>; 368 }; 369 tach1b_gpj3_default: tach1b_gpj3_default { 370 pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_3>; 371 }; 372 373 /* UART alternate function */ 374 uart1_rx_gpb0_default: uart1_rx_gpb0_default { 375 pinmuxs = <&pinctrlb 0 IT8XXX2_ALT_FUNC_3>; 376 }; 377 uart1_tx_gpb1_default: uart1_tx_gpb1_default { 378 pinmuxs = <&pinctrlb 1 IT8XXX2_ALT_FUNC_3>; 379 }; 380 uart2_rx_gph1_default: uart2_rx_gph1_default { 381 pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_4>; 382 }; 383 uart2_tx_gph2_default: uart2_tx_gph2_default { 384 pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_4>; 385 }; 386 uart2_rx_gph5_default: uart2_rx_gph5_default { 387 pinmuxs = <&pinctrlh 5 IT8XXX2_ALT_FUNC_3>; 388 }; 389 uart2_tx_gph6_default: uart2_tx_gph6_default { 390 pinmuxs = <&pinctrlh 6 IT8XXX2_ALT_FUNC_3>; 391 }; 392 uart2_rx_gpf0_default: uart2_rx_gpf0_default { 393 pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_3>; 394 }; 395 uart2_tx_gpf1_default: uart2_tx_gpf1_default { 396 pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_3>; 397 }; 398 399 /* USB alternate function */ 400 usb0_dm_gph5_default: usb0_dm_gph5_default { 401 pinmuxs = <&pinctrlh 5 IT8XXX2_ALT_DEFAULT>; 402 }; 403 usb0_dp_gph6_default: usb0_dp_gph6_default { 404 pinmuxs = <&pinctrlh 6 IT8XXX2_ALT_DEFAULT>; 405 }; 406 407 /* SPI alternate function */ 408 spi_ssce0_default: spi_ssce0_default { 409 pinmuxs = <&pinctrlg 2 IT8XXX2_ALT_FUNC_3>; 410 }; 411 spi_ssce1_default: spi_ssce1_default { 412 pinmuxs = <&pinctrlg 0 IT8XXX2_ALT_FUNC_3>; 413 }; 414 spi_ssck_default: spi_ssck_default { 415 pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_3>; 416 }; 417 spi_smosi_default: spi_smosi_default { 418 pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_3>; 419 }; 420 spi_smiso_default: spi_smiso_default { 421 pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_3>; 422 }; 423 spi_sio2_default: spi_sio2_default { 424 pinmuxs = <&pinctrlc 0 IT8XXX2_ALT_FUNC_1>; 425 }; 426 spi_sio3_default: spi_sio3_default { 427 pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_1>; 428 }; 429 430}; 431
