1# Host Command backend configs
2
3# Copyright (c) 2020 Google LLC
4# SPDX-License-Identifier: Apache-2.0
5
6DT_CHOSEN_ESPI_BACKEND := zephyr,host-cmd-espi-backend
7DT_CHOSEN_SHI_BACKEND := zephyr,host-cmd-shi-backend
8DT_CHOSEN_UART_BACKEND := zephyr,host-cmd-uart-backend
9DT_CHOSEN_SPI_BACKEND := zephyr,host-cmd-spi-backend
10
11config EC_HOST_CMD_BACKEND_SIMULATOR
12	bool "Embedded Controller Host Command Backend Simulator"
13	depends on SOC_POSIX
14	help
15	  Enable the EC host command simulator.
16
17config EC_HOST_CMD_BACKEND_ESPI
18	bool "Host commands support using eSPI bus"
19	default $(dt_chosen_enabled,$(DT_CHOSEN_ESPI_BACKEND))
20	depends on ESPI_PERIPHERAL_EC_HOST_CMD
21	depends on ESPI_PERIPHERAL_CUSTOM_OPCODE
22	help
23	  Enable support for Embedded Controller host commands using
24	  the eSPI bus.
25
26config EC_HOST_CMD_BACKEND_SHI
27	bool "Host commands support using SHI"
28	default $(dt_chosen_enabled,$(DT_CHOSEN_SHI_BACKEND))
29	help
30	  Enable support for Embedded Controller host commands using
31	  the Serial Host Interface.
32
33config EC_HOST_CMD_BACKEND_UART
34	bool "Host commands support using UART"
35	default $(dt_chosen_enabled,$(DT_CHOSEN_UART_BACKEND))
36	depends on UART_ASYNC_API
37	help
38	  Enable support for Embedded Controller host commands using
39	  the UART.
40
41config EC_HOST_CMD_BACKEND_SPI
42	bool "Host commands support using SPI"
43	help
44	  Enable support for Embedded Controller host commands using
45	  the SPI.
46
47if EC_HOST_CMD_BACKEND_SHI
48
49choice EC_HOST_CMD_BACKEND_SHI_DRIVER
50	prompt "SHI driver"
51	default EC_HOST_CMD_BACKEND_SHI_NPCX if SOC_FAMILY_NPCX
52	default EC_HOST_CMD_BACKEND_SHI_ITE if SOC_IT8XXX2
53
54config EC_HOST_CMD_BACKEND_SHI_NPCX
55	bool "SHI by Nuvoton"
56	depends on DT_HAS_NUVOTON_NPCX_SHI_ENABLED || \
57		   DT_HAS_NUVOTON_NPCX_SHI_ENHANCED_ENABLED
58	select PINCTRL
59	help
60	  This option enables the driver for SHI backend in the
61	  Nuvoton NPCX chip.
62
63config EC_HOST_CMD_BACKEND_SHI_ITE
64	bool "SHI by ITE"
65	depends on DT_HAS_ITE_IT8XXX2_SHI_ENABLED
66	select PINCTRL
67	help
68	  This option enables the driver for SHI backend in the
69	  ITE IT8xxx2 chips family.
70
71endchoice
72
73config EC_HOST_CMD_BACKEND_SHI_NPCX_ENHANCED_BUF_MODE
74	def_bool DT_HAS_NUVOTON_NPCX_SHI_ENHANCED_ENABLED
75	help
76	  In this mode, besides the original 128-bytes FIFO, an additional
77	  single-byte output buffer can be selected/switched to generate a
78	  response to simultaneous Read/Write transactions.
79
80config EC_HOST_CMD_BACKEND_SHI_NPCX_CS_DETECT_WORKAROUND
81	bool
82	default y if SOC_NPCX9M7FB
83	help
84	  Workaround the issue "CSnFE and CSnRE bits of EVSTATS2 Register (SHI)"
85	  in the npcx9m7fb SoC errata.
86
87config EC_HOST_CMD_BACKEND_SHI_MAX_REQUEST
88	int "Max data size for the version 3 request packet"
89	default 544 if EC_HOST_CMD_BACKEND_SHI_NPCX
90	default 256 if EC_HOST_CMD_BACKEND_SHI_ITE
91	help
92	  This option indicates maximum data size for a version 3 request
93	  packet. This must be big enough to handle the biggest possible
94	  request.
95
96config EC_HOST_CMD_BACKEND_SHI_MAX_RESPONSE
97	int "Max data size for the version 3 response packet"
98	default 544 if EC_HOST_CMD_BACKEND_SHI_NPCX
99	default 248 if EC_HOST_CMD_BACKEND_SHI_ITE
100	help
101	  This option indicates maximum data size for a version 3 response
102	  packet. This must be big enough to handle the biggest possible
103	  response.
104
105endif # EC_HOST_CMD_BACKEND_SHI
106
107if EC_HOST_CMD_BACKEND_SPI
108
109choice EC_HOST_CMD_BACKEND_SPI_DRIVER
110	prompt "SHI driver"
111	default EC_HOST_CMD_BACKEND_SPI_STM32 if DT_HAS_ST_STM32_SPI_HOST_CMD_ENABLED
112
113config EC_HOST_CMD_BACKEND_SPI_STM32
114	bool "SPI by STM32"
115	select PINCTRL
116	help
117	  This option enables the driver for SPI backend in the
118	  STM32 chip family.
119
120endchoice
121
122endif # EC_HOST_CMD_BACKEND_SPI
123