Searched refs:Region (Results 1 – 25 of 30) sorted by relevance
12
69 bool "Region North America"72 bool "Region Europe"75 bool "Region Asia"
25 Region Address Translation74 | Region | Addr from A53 | MAIN R5F | Size |80 | DDR Shared Region | 0x00A2000000 | 0x00A2000000 | 16MB |84 | Region | Addr from A53 | MCU R5F | Size |90 | DDR Shared Region | 0x00A1000000 | 0x00A1000000 | 16MB |
12 * - Region defined after the image SRAM of Application MCU
20 Region to relocate networking code to
61 Enables Region based address translation support
23 Region Address Translation77 | Region | R5FSS0 Core0 | R5FSS0 Core1 | R5FSS1 Core0 | R5FSS1 Core1 | Size |
41 hex "ARM Non-Secure Callable Region base address"
63 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/Region.c
62 than the requested size. Region priority mechanisms may result in
103 | Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
312 * Region [_estack .. sram_end] should be defined in MPU.
108 Shared Memory Region Organization
29 /* Region of the irq vectors and boot-vector SP/PC */
124 | Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
72 Region Protection Option) contains the "cached" mapping.
117 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
203 | Region | Cortex®-A7 | Cortex®-M4 | Size |
58 Disabling Caching for a Memory Region
188 | Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
214 | Region | Cortex®-A7 | Cortex®-M4 | Size |
200 | Region | Cortex®-A7 | Cortex®-M4 | Size |
144 | Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
161 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
124 | Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size …
