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Searched refs:TIM_AF1_ETRSEL_2 (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_tim_ex.h111 #define TIM_TIM1_ETR_ADC1_AWD2 TIM_AF1_ETRSEL_2 …
112 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
113 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
114 #define TIM_TIM1_ETR_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) …
120 #define TIM_TIM2_ETR_SAI1_FSA TIM_AF1_ETRSEL_2 …
121 #define TIM_TIM2_ETR_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
122 #define TIM_TIM2_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
123 #define TIM_TIM2_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) …
127 #define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
128 #define TIM_TIM2_ETR_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
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Dstm32n6xx_ll_tim.h1050 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 …
1051 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1052 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
1053 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_…
1065 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM_AF1_ETRSEL_2 …
1066 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1067 #define LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
1068 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1072 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1073 #define LL_TIM_TIM2_ETRSOURCE_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0…
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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_tim_ex.h111 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM_AF1_ETRSEL_2) /*!…
112 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
113 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!…
114 #define TIM_TIM1_ETR_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
120 #define TIM_TIM2_ETR_SAI1_FSA (TIM_AF1_ETRSEL_2) /*!…
121 #define TIM_TIM2_ETR_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
122 #define TIM_TIM2_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!…
123 #define TIM_TIM2_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
127 #define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
128 #define TIM_TIM2_ETR_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
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Dstm32h7rsxx_ll_tim.h1034 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 …
1035 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1036 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
1037 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1049 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM_AF1_ETRSEL_2 …
1050 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1051 #define LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
1052 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1056 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1057 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0…
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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_tim_ex.h112 #define TIM_TIM1_ETR_HSI TIM_AF1_ETRSEL_2 /*!…
114 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
115 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
120 #define TIM_TIM2_ETR_HSI TIM_AF1_ETRSEL_2 /*!…
127 #define TIM_TIM3_ETR_HSI TIM_AF1_ETRSEL_2 /*!…
130 #define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
131 #define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
Dstm32wbaxx_ll_tim.h1029 #define LL_TIM_TIM1_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 …
1031 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1032 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1045 #define LL_TIM_TIM2_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 …
1060 #define LL_TIM_TIM3_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 …
1063 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1064 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)…
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_tim_ex.h90 #define TIM_TIM1_ETR_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is con…
91 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is conn…
96 #define TIM_TIM2_ETR_MCO TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is con…
97 #define TIM_TIM2_ETR_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is conn…
Dstm32c0xx_ll_tim.h988 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< ETR inp…
989 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR inp…
992 #define LL_TIM_ETRSOURCE_MCO TIM_AF1_ETRSEL_2 /*!< ETR inp…
993 #define LL_TIM_ETRSOURCE_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR inp…
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_tim_ex.h94 #define TIM_TIM1_ETR_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is co…
95 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is co…
102 #define TIM_TIM2_ETR_MCO TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is co…
103 #define TIM_TIM2_ETR_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is co…
Dstm32u0xx_ll_tim.h998 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< ETR inp…
999 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR inp…
1001 #define LL_TIM_ETRSOURCE_MCO TIM_AF1_ETRSEL_2 /*!< ETR inp…
1002 #define LL_TIM_ETRSOURCE_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR inp…
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h5832 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32c031xx.h5995 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32c071xx.h6499 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8958 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000… macro
Dstm32wba52xx.h13126 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000… macro
Dstm32wba54xx.h13834 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000… macro
Dstm32wba5mxx.h13852 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000… macro
Dstm32wba55xx.h13852 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000… macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h7889 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32u083xx.h8826 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32u073xx.h8556 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h20279 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32h7s7xx.h21594 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32h7s3xx.h21162 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro
Dstm32h7r7xx.h20709 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ macro

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