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Searched refs:RCC_APBENR2_TIM1EN (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h944 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
946 … tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
999 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
1118 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
1127 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
Dstm32c0xx_ll_bus.h120 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h1159 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1161 … tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1211 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
1422 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
1440 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
Dstm32u0xx_ll_bus.h147 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1304 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1306 … tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1440 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
1672 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
1684 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
Dstm32g0xx_ll_bus.h180 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4113 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32c031xx.h4273 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32c071xx.h4741 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h4349 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g050xx.h4383 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g070xx.h4524 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g031xx.h4563 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g041xx.h4811 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g051xx.h4920 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g061xx.h5168 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g071xx.h5285 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g081xx.h5533 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g0b0xx.h5573 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g0c1xx.h6891 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32g0b1xx.h6643 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5434 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32u083xx.h6268 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro
Dstm32u073xx.h6004 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk macro