1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB & APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32C0xx_LL_BUS_H
39 #define STM32C0xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32c0xx.h"
47
48 /** @addtogroup STM32C0xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
76 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
77 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
79 /**
80 * @}
81 */
82
83
84 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
85 * @{
86 */
87 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
88 #if defined(TIM2)
89 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
90 #endif /* TIM2 */
91 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
92 #define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
93 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
94 #if defined (USB_DRD_FS)
95 #define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
96 #endif /* USB_DRD_FS */
97 #if defined(SPI2)
98 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
99 #endif /* SPI2 */
100 #if defined(CRS)
101 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
102 #endif /* CRS */
103 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
104 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
105 #if defined(I2C2)
106 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
107 #endif /* I2C2 */
108 #define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
109 #define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
110
111 /**
112 * @}
113 */
114
115 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
116 * @{
117 */
118 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
119 #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
120 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN
121 #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN
122 #define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN
123 #define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN
124 #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN
125 #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN
126 #define LL_APB1_GRP2_PERIPH_ADC RCC_APBENR2_ADCEN
127 /* defines for legacy purpose */
128 #define LL_APB2_GRP2_PERIPH_ALL LL_APB1_GRP2_PERIPH_ALL
129 #define LL_APB2_GRP1_PERIPH_SYSCFG LL_APB1_GRP2_PERIPH_SYSCFG
130 #define LL_APB2_GRP1_PERIPH_TIM1 LL_APB1_GRP2_PERIPH_TIM1
131 #define LL_APB2_GRP1_PERIPH_SPI1 LL_APB1_GRP2_PERIPH_SPI1
132 #define LL_APB2_GRP1_PERIPH_USART1 LL_APB1_GRP2_PERIPH_USART1
133 #define LL_APB2_GRP1_PERIPH_TIM14 LL_APB1_GRP2_PERIPH_TIM14
134 #define LL_APB2_GRP1_PERIPH_TIM16 LL_APB1_GRP2_PERIPH_TIM16
135 #define LL_APB2_GRP1_PERIPH_TIM17 LL_APB1_GRP2_PERIPH_TIM17
136 #define LL_APB2_GRP1_PERIPH_ADC LL_APB1_GRP2_PERIPH_ADC
137
138 /**
139 * @}
140 */
141
142 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
143 * @{
144 */
145 #define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
146 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
147 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
148 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
149 #if defined(GPIOD)
150 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
151 #endif /* GPIOD */
152 #define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
153
154 /**
155 * @}
156 */
157
158 /**
159 * @}
160 */
161
162 /* Exported macro ------------------------------------------------------------*/
163 /* Exported functions --------------------------------------------------------*/
164 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
165 * @{
166 */
167
168 /** @defgroup BUS_LL_EF_AHB1 AHB1
169 * @{
170 */
171
172 /**
173 * @brief Enable AHB1 peripherals clock.
174 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
175 * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
176 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock
177 * @param Periphs This parameter can be a combination of the following values:
178 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
179 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
180 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
181 * @retval None
182 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)183 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
184 {
185 __IO uint32_t tmpreg;
186 SET_BIT(RCC->AHBENR, Periphs);
187 /* Delay after an RCC peripheral clock enabling */
188 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
189 (void)tmpreg;
190 }
191
192 /**
193 * @brief Check if AHB1 peripheral clock is enabled or not
194 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
195 * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
196 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock
197 * @param Periphs This parameter can be a combination of the following values:
198 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
199 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
200 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
201 * @retval State of Periphs (1 or 0).
202 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)203 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
204 {
205 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
206 }
207
208 /**
209 * @brief Disable AHB1 peripherals clock.
210 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
211 * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
212 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock
213 * @param Periphs This parameter can be a combination of the following values:
214 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
215 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
216 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
217 * @retval None
218 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)219 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
220 {
221 CLEAR_BIT(RCC->AHBENR, Periphs);
222 }
223
224 /**
225 * @brief Force AHB1 peripherals reset.
226 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
227 * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
228 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset
229 * @param Periphs This parameter can be a combination of the following values:
230 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
231 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
232 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
233 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
234 * @retval None
235 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)236 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
237 {
238 SET_BIT(RCC->AHBRSTR, Periphs);
239 }
240
241 /**
242 * @brief Release AHB1 peripherals reset.
243 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
244 * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
245 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset
246 * @param Periphs This parameter can be a combination of the following values:
247 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
248 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
249 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
250 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
251 * @retval None
252 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)253 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
254 {
255 CLEAR_BIT(RCC->AHBRSTR, Periphs);
256 }
257
258 /**
259 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
260 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
261 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
262 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
263 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
264 * @param Periphs This parameter can be a combination of the following values:
265 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
266 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
267 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
268 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
269 * @retval None
270 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)271 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
272 {
273 __IO uint32_t tmpreg;
274 SET_BIT(RCC->AHBSMENR, Periphs);
275 /* Delay after an RCC peripheral clock enabling */
276 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
277 (void)tmpreg;
278 }
279
280 /**
281 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
282 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
283 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
284 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
285 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
286 * @param Periphs This parameter can be a combination of the following values:
287 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
288 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
289 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
290 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
291 * @retval None
292 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)293 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
294 {
295 CLEAR_BIT(RCC->AHBSMENR, Periphs);
296 }
297
298 /**
299 * @}
300 */
301
302 /** @defgroup BUS_LL_EF_APB1_GRP1 APB1_GRP1
303 * @{
304 */
305
306 /**
307 * @brief Enable APB1 peripherals clock.
308 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
309 * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
310 * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
311 * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
312 * APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n
313 * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
314 * APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n (*)
315 * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n (*)
316 * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n (*)
317 * APBENR1 USBEN LL_APB1_GRP1_EnableClock\n (*)
318 * @param Periphs This parameter can be a combination of the following values:
319 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
320 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
321 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
322 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
323 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
324 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
325 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
326 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
327 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
328 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
329 * @note (*) peripheral not available on all devices
330 * @retval None
331 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)332 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
333 {
334 __IO uint32_t tmpreg;
335 SET_BIT(RCC->APBENR1, Periphs);
336 /* Delay after an RCC peripheral clock enabling */
337 tmpreg = READ_BIT(RCC->APBENR1, Periphs);
338 (void)tmpreg;
339 }
340
341 /**
342 * @brief Check if APB1 GRP1 peripheral clock is enabled or not
343 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
344 * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
345 * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
346 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
347 * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
348 * APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n
349 * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
350 * APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n (*)
351 * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n (*)
352 * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n (*)
353 * APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n (*)
354 * @param Periphs This parameter can be a combination of the following values:
355 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
356 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
357 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
358 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
359 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
360 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
361 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
362 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
363 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
364 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
365 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
366 * @note (*) peripheral not available on all devices
367 * @retval State of Periphs (1 or 0).
368 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)369 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
370 {
371 return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
372 }
373
374 /**
375 * @brief Disable APB1 GRP1 peripherals clock.
376 * @rmtoll APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
377 * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
378 * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
379 * APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n
380 * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
381 * APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n
382 * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
383 * APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n (*)
384 * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n (*)
385 * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n (*)
386 * APBENR1 USBEN LL_APB1_GRP1_DisableClock\n (*)
387 * @param Periphs This parameter can be a combination of the following values:
388 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
389 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
390 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
391 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
392 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
393 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
394 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
395 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
396 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
397 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
398 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
399 * @note (*) peripheral not available on all devices
400 * @retval None
401 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)402 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
403 {
404 CLEAR_BIT(RCC->APBENR1, Periphs);
405 }
406
407 /**
408 * @brief Force APB1 GRP1 peripherals reset.
409 * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
410 * APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
411 * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
412 * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
413 * APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n
414 * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
415 * APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n (*)
416 * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n (*)
417 * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n (*)
418 * APBRSTR1 USBRST LL_APB1_GRP1_ForceReset\n (*)
419 * @param Periphs This parameter can be a combination of the following values:
420 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
421 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
422 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
423 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
424 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
425 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
426 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
427 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
428 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
429 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
430 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
431 * @note (*) peripheral not available on all devices
432 * @retval None
433 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)434 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
435 {
436 SET_BIT(RCC->APBRSTR1, Periphs);
437 }
438
439 /**
440 * @brief Release APB1 GRP1 peripherals reset.
441 * @rmtoll APBRSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
442 * APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
443 * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
444 * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
445 * APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n
446 * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
447 * APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n (*)
448 * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n (*)
449 * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n (*)
450 * APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n (*)
451 * @param Periphs This parameter can be a combination of the following values:
452 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
454 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
455 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
456 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
457 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
458 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
459 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
460 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
461 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
462 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
463 * @note (*) peripheral not available on all devices
464 * @retval None
465 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)466 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
467 {
468 CLEAR_BIT(RCC->APBRSTR1, Periphs);
469 }
470
471 /**
472 * @brief Enable APB1 GRP1 peripheral clocks in Sleep and Stop modes
473 * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
474 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
475 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
476 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
477 * APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
478 * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
479 * APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*)
480 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*)
481 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n (*)
482 * APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n (*)
483 * @param Periphs This parameter can be a combination of the following values:
484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
485 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
486 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
487 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
488 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
489 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
490 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
491 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
492 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
493 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
494 * @note (*) peripheral not available on all devices
495 * @retval None
496 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)497 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
498 {
499 __IO uint32_t tmpreg;
500 SET_BIT(RCC->APBSMENR1, Periphs);
501 /* Delay after an RCC peripheral clock enabling */
502 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
503 (void)tmpreg;
504 }
505
506 /**
507 * @brief Disable APB1 GRP1 peripheral clocks in Sleep and Stop modes
508 * @rmtoll APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
509 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
510 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
511 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
512 * APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
513 * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
514 * APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*)
515 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*)
516 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n (*)
517 * APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n (*)
518 * @param Periphs This parameter can be a combination of the following values:
519 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
520 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
521 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
522 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
523 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
524 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
526 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
527 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
528 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
529 * @note (*) peripheral not available on all devices
530 * @retval None
531 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)532 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
533 {
534 CLEAR_BIT(RCC->APBSMENR1, Periphs);
535 }
536
537 /**
538 * @}
539 */
540
541 /** @defgroup BUS_LL_EF_APB1_GRP2 APB1_GRP2
542 * @{
543 */
544
545 /**
546 * @brief Enable APB1 GRP2 peripherals clock.
547 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_EnableClock\n
548 * APBENR2 TIM1EN LL_APB1_GRP2_EnableClock\n
549 * APBENR2 SPI1EN LL_APB1_GRP2_EnableClock\n
550 * APBENR2 USART1EN LL_APB1_GRP2_EnableClock\n
551 * APBENR2 TIM14EN LL_APB1_GRP2_EnableClock\n
552 * APBENR2 TIM16EN LL_APB1_GRP2_EnableClock\n
553 * APBENR2 TIM17EN LL_APB1_GRP2_EnableClock\n
554 * APBENR2 ADCEN LL_APB1_GRP2_EnableClock
555 * @param Periphs This parameter can be a combination of the following values:
556 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
557 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
558 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
559 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
560 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
561 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
562 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
563 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
564 * @retval None
565 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)566 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
567 {
568 __IO uint32_t tmpreg;
569 SET_BIT(RCC->APBENR2, Periphs);
570 /* Delay after an RCC peripheral clock enabling */
571 tmpreg = READ_BIT(RCC->APBENR2, Periphs);
572 (void)tmpreg;
573 }
574 #define LL_APB2_GRP1_EnableClock LL_APB1_GRP2_EnableClock
575
576 /**
577 * @brief Check if APB1 GRP2 peripheral clock is enabled or not
578 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
579 * APBENR2 TIM1EN LL_APB1_GRP2_IsEnabledClock\n
580 * APBENR2 SPI1EN LL_APB1_GRP2_IsEnabledClock\n
581 * APBENR2 USART1EN LL_APB1_GRP2_IsEnabledClock\n
582 * APBENR2 TIM14EN LL_APB1_GRP2_IsEnabledClock\n
583 * APBENR2 TIM16EN LL_APB1_GRP2_IsEnabledClock\n
584 * APBENR2 TIM17EN LL_APB1_GRP2_IsEnabledClock\n
585 * APBENR2 ADCEN LL_APB1_GRP2_IsEnabledClock
586 * @param Periphs This parameter can be a combination of the following values:
587 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
588 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
589 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
590 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
591 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
592 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
593 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
594 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
595 * @retval State of Periphs (1 or 0).
596 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)597 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
598 {
599 return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
600 }
601 #define LL_APB2_GRP1_IsEnabledClock LL_APB1_GRP2_IsEnabledClock
602
603 /**
604 * @brief Disable APB1 GRP2 peripherals clock.
605 * @rmtoll APBENR2 SYSCFGEN LL_APB1_GRP2_DisableClock\n
606 * APBENR2 TIM1EN LL_APB1_GRP2_DisableClock\n
607 * APBENR2 SPI1EN LL_APB1_GRP2_DisableClock\n
608 * APBENR2 USART1EN LL_APB1_GRP2_DisableClock\n
609 * APBENR2 TIM14EN LL_APB1_GRP2_DisableClock\n
610 * APBENR2 TIM16EN LL_APB1_GRP2_DisableClock\n
611 * APBENR2 TIM17EN LL_APB1_GRP2_DisableClock\n
612 * APBENR2 ADCEN LL_APB1_GRP2_DisableClock
613 * @param Periphs This parameter can be a combination of the following values:
614 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
615 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
616 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
617 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
618 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
619 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
620 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
621 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
622 * @retval None
623 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)624 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
625 {
626 CLEAR_BIT(RCC->APBENR2, Periphs);
627 }
628 #define LL_APB2_GRP1_DisableClock LL_APB1_GRP2_DisableClock
629
630 /**
631 * @brief Force APB1 GRP2 peripherals reset.
632 * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ForceReset\n
633 * APBRSTR2 TIM1RST LL_APB1_GRP2_ForceReset\n
634 * APBRSTR2 SPI1RST LL_APB1_GRP2_ForceReset\n
635 * APBRSTR2 USART1RST LL_APB1_GRP2_ForceReset\n
636 * APBRSTR2 TIM14RST LL_APB1_GRP2_ForceReset\n
637 * APBRSTR2 TIM16RST LL_APB1_GRP2_ForceReset\n
638 * APBRSTR2 TIM17RST LL_APB1_GRP2_ForceReset\n
639 * APBRSTR2 ADCRST LL_APB1_GRP2_ForceReset
640 * @param Periphs This parameter can be a combination of the following values:
641 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
642 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
643 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
644 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
645 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
646 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
647 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
648 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
649 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
650 * @retval None
651 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)652 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
653 {
654 SET_BIT(RCC->APBRSTR2, Periphs);
655 }
656 #define LL_APB2_GRP1_ForceReset LL_APB1_GRP2_ForceReset
657
658 /**
659 * @brief Release APB1 GRP2 peripherals reset.
660 * @rmtoll APBRSTR2 SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
661 * APBRSTR2 TIM1RST LL_APB1_GRP2_ReleaseReset\n
662 * APBRSTR2 SPI1RST LL_APB1_GRP2_ReleaseReset\n
663 * APBRSTR2 USART1RST LL_APB1_GRP2_ReleaseReset\n
664 * APBRSTR2 TIM14RST LL_APB1_GRP2_ReleaseReset\n
665 * APBRSTR2 TIM16RST LL_APB1_GRP2_ReleaseReset\n
666 * APBRSTR2 TIM17RST LL_APB1_GRP2_ReleaseReset\n
667 * APBRSTR2 ADCRST LL_APB1_GRP2_ReleaseReset
668 * @param Periphs This parameter can be a combination of the following values:
669 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
670 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
671 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
672 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
673 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
674 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
675 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
676 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
677 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
678 * @retval None
679 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)680 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
681 {
682 CLEAR_BIT(RCC->APBRSTR2, Periphs);
683 }
684 #define LL_APB2_GRP1_ReleaseReset LL_APB1_GRP2_ReleaseReset
685
686 /**
687 * @brief Enable APB1 GRP2 peripheral clocks in Sleep and Stop modes
688 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_EnableClockStopSleep\n
689 * APBSMENR2 TIM1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
690 * APBSMENR2 SPI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
691 * APBSMENR2 USART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
692 * APBSMENR2 TIM14SMEN LL_APB1_GRP2_EnableClockStopSleep\n
693 * APBSMENR2 TIM16SMEN LL_APB1_GRP2_EnableClockStopSleep\n
694 * APBSMENR2 TIM17SMEN LL_APB1_GRP2_EnableClockStopSleep\n
695 * APBSMENR2 ADCSMEN LL_APB1_GRP2_EnableClockStopSleep
696 * @param Periphs This parameter can be a combination of the following values:
697 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
698 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
699 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
700 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
701 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
702 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
703 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
704 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
705 * @retval None
706 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)707 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
708 {
709 __IO uint32_t tmpreg;
710 SET_BIT(RCC->APBSMENR2, Periphs);
711 /* Delay after an RCC peripheral clock enabling */
712 tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
713 (void)tmpreg;
714 }
715 #define LL_APB2_GRP1_EnableClockStopSleep LL_APB1_GRP2_EnableClockStopSleep
716
717 /**
718 * @brief Disable APB1 GRP2 peripheral clocks in Sleep and Stop modes
719 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB1_GRP2_DisableClockStopSleep\n
720 * APBSMENR2 TIM1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
721 * APBSMENR2 SPI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
722 * APBSMENR2 USART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
723 * APBSMENR2 TIM14SMEN LL_APB1_GRP2_DisableClockStopSleep\n
724 * APBSMENR2 TIM16SMEN LL_APB1_GRP2_DisableClockStopSleep\n
725 * APBSMENR2 TIM17SMEN LL_APB1_GRP2_DisableClockStopSleep\n
726 * APBSMENR2 ADCSMEN LL_APB1_GRP2_DisableClockStopSleep
727 * @param Periphs This parameter can be a combination of the following values:
728 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
729 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
730 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
731 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
732 * @arg @ref LL_APB1_GRP2_PERIPH_TIM14
733 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
734 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
735 * @arg @ref LL_APB1_GRP2_PERIPH_ADC
736 * @retval None
737 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)738 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
739 {
740 CLEAR_BIT(RCC->APBSMENR2, Periphs);
741 }
742 #define LL_APB2_GRP1_DisableClockStopSleep LL_APB1_GRP2_DisableClockStopSleep
743
744 /**
745 * @}
746 */
747
748 /** @defgroup BUS_LL_EF_IOP IOP
749 * @{
750 */
751
752 /**
753 * @brief Enable IOP peripherals clock.
754 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
755 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
756 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
757 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
758 * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
759 * @param Periphs This parameter can be a combination of the following values:
760 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
761 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
762 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
763 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
764 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
765 * @retval None
766 */
LL_IOP_GRP1_EnableClock(uint32_t Periphs)767 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
768 {
769 __IO uint32_t tmpreg;
770 SET_BIT(RCC->IOPENR, Periphs);
771 /* Delay after an RCC peripheral clock enabling */
772 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
773 (void)tmpreg;
774 }
775
776 /**
777 * @brief Check if IOP peripheral clock is enabled or not
778 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
779 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
780 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
781 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
782 * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
783 * @param Periphs This parameter can be a combination of the following values:
784 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
785 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
786 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
787 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
788 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
789 * @retval State of Periphs (1 or 0).
790 */
LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)791 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
792 {
793 return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
794 }
795
796 /**
797 * @brief Disable IOP peripherals clock.
798 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
799 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
800 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
801 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
802 * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
803 * @param Periphs This parameter can be a combination of the following values:
804 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
805 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
806 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
807 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
808 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
809 * @retval None
810 */
LL_IOP_GRP1_DisableClock(uint32_t Periphs)811 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
812 {
813 CLEAR_BIT(RCC->IOPENR, Periphs);
814 }
815
816 /**
817 * @brief Disable IOP peripherals clock.
818 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
819 * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
820 * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
821 * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
822 * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
823 * @param Periphs This parameter can be a combination of the following values:
824 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
825 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
826 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
827 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
828 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
829 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
830 * @retval None
831 */
LL_IOP_GRP1_ForceReset(uint32_t Periphs)832 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
833 {
834 SET_BIT(RCC->IOPRSTR, Periphs);
835 }
836
837 /**
838 * @brief Release IOP peripherals reset.
839 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
840 * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
841 * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
842 * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
843 * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
844 * @param Periphs This parameter can be a combination of the following values:
845 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
846 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
847 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
848 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
849 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
850 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
851 * @retval None
852 */
LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)853 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
854 {
855 CLEAR_BIT(RCC->IOPRSTR, Periphs);
856 }
857
858 /**
859 * @brief Enable IOP peripheral clocks in Sleep and Stop modes
860 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
861 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
862 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
863 * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
864 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
865 * @param Periphs This parameter can be a combination of the following values:
866 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
867 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
868 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
869 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
870 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
871 * @retval None
872 */
LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)873 __STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
874 {
875 __IO uint32_t tmpreg;
876 SET_BIT(RCC->IOPSMENR, Periphs);
877 /* Delay after an RCC peripheral clock enabling */
878 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
879 (void)tmpreg;
880 }
881
882 /**
883 * @brief Disable IOP peripheral clocks in Sleep and Stop modes
884 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
885 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
886 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
887 * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
888 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
889 * @param Periphs This parameter can be a combination of the following values:
890 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
891 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
892 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
893 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
894 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
895 * @retval None
896 */
LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)897 __STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
898 {
899 CLEAR_BIT(RCC->IOPSMENR, Periphs);
900 }
901
902 /**
903 * @}
904 */
905
906
907 /**
908 * @}
909 */
910
911 /**
912 * @}
913 */
914
915 #endif /* defined(RCC) */
916
917 /**
918 * @}
919 */
920
921 #ifdef __cplusplus
922 }
923 #endif
924
925 #endif /* STM32C0xx_LL_BUS_H */
926
