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Searched refs:RCC_APBENR1_WWDGEN (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h824 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
826 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
906 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN)
1066 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
1089 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
Dstm32c0xx_ll_bus.h93 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h913 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
915 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1089 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN)
1298 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0…
1360 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0…
Dstm32u0xx_ll_bus.h110 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1073 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1075 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1543 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
1607 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
Dstm32g0xx_ll_bus.h122 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4093 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32c031xx.h4253 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32c071xx.h4709 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h4323 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g050xx.h4357 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g070xx.h4492 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g031xx.h4528 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g041xx.h4776 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g051xx.h4882 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g061xx.h5130 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g071xx.h5232 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g081xx.h5480 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g0b0xx.h5532 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g0c1xx.h6823 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32g0b1xx.h6575 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5387 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32u083xx.h6203 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro
Dstm32u073xx.h5939 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk macro