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Searched refs:RCC_APBENR1_TIM3EN (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h808 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
810 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
904 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
1064 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
1087 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
Dstm32c0xx_ll_bus.h91 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h865 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
867 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1075 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
1284 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0…
1346 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0…
Dstm32u0xx_ll_bus.h102 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1021 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1023 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1371 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
1533 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
1597 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
Dstm32g0xx_ll_bus.h101 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4087 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32c031xx.h4247 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32c071xx.h4703 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h4317 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g050xx.h4345 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g070xx.h4480 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g031xx.h4522 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g041xx.h4770 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g051xx.h4870 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g061xx.h5118 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g071xx.h5220 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g081xx.h5468 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g0b0xx.h5511 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g0c1xx.h6799 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32g0b1xx.h6551 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5372 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32u083xx.h6185 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro
Dstm32u073xx.h5921 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk macro