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Searched refs:OR1 (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c3500 SET_BIT(TIM17->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_EnableHSE32()
3504 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_EnableHSE32()
3507 SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_EnableHSE32()
3528 CLEAR_BIT(TIM17->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_DisableHSE32()
3532 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_DisableHSE32()
3535 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); in HAL_TIMEx_DisableHSE32()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_tim_ex.c2306 tmpor = READ_REG(htim->Instance->OR1); in HAL_TIMEx_RemapConfig()
2333 WRITE_REG(htim->Instance->OR1, tmpor); in HAL_TIMEx_RemapConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h5234 SET_BIT(TIMx->OR1, TIM_OR1_RTCPREEN); in LL_TIM_EnableRTCPRE()
5246 CLEAR_BIT(TIMx->OR1, TIM_OR1_RTCPREEN); in LL_TIM_DisableRTCPRE()
5258 return ((READ_BIT(TIMx->OR1, TIM_OR1_RTCPREEN) == (TIM_OR1_RTCPREEN)) ? 1UL : 0UL); in LL_TIM_IsEnabledRTCPRE()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h5153 SET_BIT(TIMx->OR1, TIM_OR1_HSE32EN); in LL_TIM_EnableHSE32()
5165 CLEAR_BIT(TIMx->OR1, TIM_OR1_HSE32EN); in LL_TIM_DisableHSE32()
5177 return ((READ_BIT(TIMx->OR1, TIM_OR1_HSE32EN) == (TIM_OR1_HSE32EN)) ? 1UL : 0UL); in LL_TIM_IsEnabledHSE32()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c2588 SET_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN); in HAL_TIMEx_TISelection()
2592 CLEAR_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN); in HAL_TIMEx_TISelection()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_tim.c5318 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
5330 MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource); in HAL_TIM_ConfigOCrefClear()
5358 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_tim.c5319 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
5335 MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource); in HAL_TIM_ConfigOCrefClear()
5364 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_hal_tim_ex.c1548 WRITE_REG(htim->Instance->OR1, Remap); in HAL_TIMEx_RemapConfig()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_tim_ex.c2474 htim->Instance->OR1 = tmpor1; in HAL_TIMEx_RemapConfig()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_tim_ex.c2343 htim->Instance->OR1 = tmpor1; in HAL_TIMEx_RemapConfig()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_tim.h3602 WRITE_REG(TIMx->OR1, Remap); in LL_TIM_SetRemap()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_tim.h4035 MODIFY_REG(TIMx->OR1, TIM_OR1_OCREF_CLR, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_tim.h3927 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); in LL_TIM_SetRemap()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_tim.h4247 MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_tim.h4056 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); in LL_TIM_SetRemap()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_tim.h3998 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); in LL_TIM_SetRemap()
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h477 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g050xx.h482 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g070xx.h481 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g031xx.h502 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g041xx.h503 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g051xx.h542 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
Dstm32g061xx.h543 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ member
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h711 __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ member
Dstm32wle5xx.h711 __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ member

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