1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 ******************************************************************************
16 * @attention
17 *
18 * Copyright (c) 2017 STMicroelectronics.
19 * All rights reserved.
20 *
21 * This software is licensed under terms that can be found in the LICENSE file
22 * in the root directory of this software component.
23 * If no LICENSE file comes with this software, it is provided AS-IS.
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### TIMER Extended features #####
29 ==============================================================================
30 [..]
31 The Timer Extended features include:
32 (#) Complementary outputs with programmable dead-time for :
33 (++) Output Compare
34 (++) PWM generation (Edge and Center-aligned Mode)
35 (++) One-pulse mode output
36 (#) Synchronization circuit to control the timer with external signals and to
37 interconnect several timers together.
38 (#) Break input to put the timer output signals in reset state or in a known state.
39 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
40 positioning purposes
41
42 ##### How to use this driver #####
43 ==============================================================================
44 [..]
45 (#) Initialize the TIM low level resources by implementing the following functions
46 depending on the selected feature:
47 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
48
49 (#) Initialize the TIM low level resources :
50 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
51 (##) TIM pins configuration
52 (+++) Enable the clock for the TIM GPIOs using the following function:
53 __HAL_RCC_GPIOx_CLK_ENABLE();
54 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
55
56 (#) The external Clock can be configured, if needed (the default clock is the
57 internal clock from the APBx), using the following function:
58 HAL_TIM_ConfigClockSource, the clock configuration should be done before
59 any start function.
60
61 (#) Configure the TIM in the desired functioning mode using one of the
62 initialization function of this driver:
63 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
64 Timer Hall Sensor Interface and the commutation event with the corresponding
65 Interrupt and DMA request if needed (Note that One Timer is used to interface
66 with the Hall sensor Interface and another Timer should be used to use
67 the commutation event).
68
69 (#) Activate the TIM peripheral using one of the start functions:
70 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
71 HAL_TIMEx_OCN_Start_IT()
72 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
73 HAL_TIMEx_PWMN_Start_IT()
74 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
75 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
76 HAL_TIMEx_HallSensor_Start_IT().
77
78 @endverbatim
79 ******************************************************************************
80 */
81
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32l4xx_hal.h"
84
85 /** @addtogroup STM32L4xx_HAL_Driver
86 * @{
87 */
88
89 /** @defgroup TIMEx TIMEx
90 * @brief TIM Extended HAL module driver
91 * @{
92 */
93
94 #ifdef HAL_TIM_MODULE_ENABLED
95
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98 /* Private macros ------------------------------------------------------------*/
99 /* Private variables ---------------------------------------------------------*/
100 /* Private function prototypes -----------------------------------------------*/
101 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
102 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
103 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
104
105 /* Exported functions --------------------------------------------------------*/
106 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
107 * @{
108 */
109
110 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
111 * @brief Timer Hall Sensor functions
112 *
113 @verbatim
114 ==============================================================================
115 ##### Timer Hall Sensor functions #####
116 ==============================================================================
117 [..]
118 This section provides functions allowing to:
119 (+) Initialize and configure TIM HAL Sensor.
120 (+) De-initialize TIM HAL Sensor.
121 (+) Start the Hall Sensor Interface.
122 (+) Stop the Hall Sensor Interface.
123 (+) Start the Hall Sensor Interface and enable interrupts.
124 (+) Stop the Hall Sensor Interface and disable interrupts.
125 (+) Start the Hall Sensor Interface and enable DMA transfers.
126 (+) Stop the Hall Sensor Interface and disable DMA transfers.
127
128 @endverbatim
129 * @{
130 */
131 /**
132 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
133 * @note When the timer instance is initialized in Hall Sensor Interface mode,
134 * timer channels 1 and channel 2 are reserved and cannot be used for
135 * other purpose.
136 * @param htim TIM Hall Sensor Interface handle
137 * @param sConfig TIM Hall Sensor configuration structure
138 * @retval HAL status
139 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)140 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
141 {
142 TIM_OC_InitTypeDef OC_Config;
143
144 /* Check the TIM handle allocation */
145 if (htim == NULL)
146 {
147 return HAL_ERROR;
148 }
149
150 /* Check the parameters */
151 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
152 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
153 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
154 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
155 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
156 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
157 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
158 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
159
160 if (htim->State == HAL_TIM_STATE_RESET)
161 {
162 /* Allocate lock resource and initialize it */
163 htim->Lock = HAL_UNLOCKED;
164
165 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
166 /* Reset interrupt callbacks to legacy week callbacks */
167 TIM_ResetCallback(htim);
168
169 if (htim->HallSensor_MspInitCallback == NULL)
170 {
171 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
172 }
173 /* Init the low level hardware : GPIO, CLOCK, NVIC */
174 htim->HallSensor_MspInitCallback(htim);
175 #else
176 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
177 HAL_TIMEx_HallSensor_MspInit(htim);
178 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
179 }
180
181 /* Set the TIM state */
182 htim->State = HAL_TIM_STATE_BUSY;
183
184 /* Configure the Time base in the Encoder Mode */
185 TIM_Base_SetConfig(htim->Instance, &htim->Init);
186
187 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
188 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
189
190 /* Reset the IC1PSC Bits */
191 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
192 /* Set the IC1PSC value */
193 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
194
195 /* Enable the Hall sensor interface (XOR function of the three inputs) */
196 htim->Instance->CR2 |= TIM_CR2_TI1S;
197
198 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
199 htim->Instance->SMCR &= ~TIM_SMCR_TS;
200 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
201
202 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
203 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
204 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
205
206 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
207 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
208 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
209 OC_Config.OCMode = TIM_OCMODE_PWM2;
210 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
211 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
212 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
213 OC_Config.Pulse = sConfig->Commutation_Delay;
214
215 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
216
217 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
218 register to 101 */
219 htim->Instance->CR2 &= ~TIM_CR2_MMS;
220 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
221
222 /* Initialize the DMA burst operation state */
223 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
224
225 /* Initialize the TIM channels state */
226 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
227 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
228 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
229 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
230
231 /* Initialize the TIM state*/
232 htim->State = HAL_TIM_STATE_READY;
233
234 return HAL_OK;
235 }
236
237 /**
238 * @brief DeInitializes the TIM Hall Sensor interface
239 * @param htim TIM Hall Sensor Interface handle
240 * @retval HAL status
241 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)242 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
243 {
244 /* Check the parameters */
245 assert_param(IS_TIM_INSTANCE(htim->Instance));
246
247 htim->State = HAL_TIM_STATE_BUSY;
248
249 /* Disable the TIM Peripheral Clock */
250 __HAL_TIM_DISABLE(htim);
251
252 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
253 if (htim->HallSensor_MspDeInitCallback == NULL)
254 {
255 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
256 }
257 /* DeInit the low level hardware */
258 htim->HallSensor_MspDeInitCallback(htim);
259 #else
260 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
261 HAL_TIMEx_HallSensor_MspDeInit(htim);
262 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
263
264 /* Change the DMA burst operation state */
265 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
266
267 /* Change the TIM channels state */
268 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
269 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
270 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
271 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
272
273 /* Change TIM state */
274 htim->State = HAL_TIM_STATE_RESET;
275
276 /* Release Lock */
277 __HAL_UNLOCK(htim);
278
279 return HAL_OK;
280 }
281
282 /**
283 * @brief Initializes the TIM Hall Sensor MSP.
284 * @param htim TIM Hall Sensor Interface handle
285 * @retval None
286 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)287 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
288 {
289 /* Prevent unused argument(s) compilation warning */
290 UNUSED(htim);
291
292 /* NOTE : This function should not be modified, when the callback is needed,
293 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
294 */
295 }
296
297 /**
298 * @brief DeInitializes TIM Hall Sensor MSP.
299 * @param htim TIM Hall Sensor Interface handle
300 * @retval None
301 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)302 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
303 {
304 /* Prevent unused argument(s) compilation warning */
305 UNUSED(htim);
306
307 /* NOTE : This function should not be modified, when the callback is needed,
308 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
309 */
310 }
311
312 /**
313 * @brief Starts the TIM Hall Sensor Interface.
314 * @param htim TIM Hall Sensor Interface handle
315 * @retval HAL status
316 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)317 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
318 {
319 uint32_t tmpsmcr;
320 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
321 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
322 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
323 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
324
325 /* Check the parameters */
326 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
327
328 /* Check the TIM channels state */
329 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
330 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
331 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
332 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
333 {
334 return HAL_ERROR;
335 }
336
337 /* Set the TIM channels state */
338 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
339 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
340 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
341 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
342
343 /* Enable the Input Capture channel 1
344 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
345 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
346 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
347
348 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
349 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
350 {
351 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
352 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
353 {
354 __HAL_TIM_ENABLE(htim);
355 }
356 }
357 else
358 {
359 __HAL_TIM_ENABLE(htim);
360 }
361
362 /* Return function status */
363 return HAL_OK;
364 }
365
366 /**
367 * @brief Stops the TIM Hall sensor Interface.
368 * @param htim TIM Hall Sensor Interface handle
369 * @retval HAL status
370 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)371 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
372 {
373 /* Check the parameters */
374 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
375
376 /* Disable the Input Capture channels 1, 2 and 3
377 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
378 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
379 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
380
381 /* Disable the Peripheral */
382 __HAL_TIM_DISABLE(htim);
383
384 /* Set the TIM channels state */
385 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
386 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
387 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
388 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
389
390 /* Return function status */
391 return HAL_OK;
392 }
393
394 /**
395 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
396 * @param htim TIM Hall Sensor Interface handle
397 * @retval HAL status
398 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)399 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
400 {
401 uint32_t tmpsmcr;
402 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
403 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
404 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
405 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
406
407 /* Check the parameters */
408 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
409
410 /* Check the TIM channels state */
411 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
412 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
413 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
414 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
415 {
416 return HAL_ERROR;
417 }
418
419 /* Set the TIM channels state */
420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
421 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
422 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
423 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
424
425 /* Enable the capture compare Interrupts 1 event */
426 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
427
428 /* Enable the Input Capture channel 1
429 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
430 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
431 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
432
433 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
434 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
435 {
436 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
437 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
438 {
439 __HAL_TIM_ENABLE(htim);
440 }
441 }
442 else
443 {
444 __HAL_TIM_ENABLE(htim);
445 }
446
447 /* Return function status */
448 return HAL_OK;
449 }
450
451 /**
452 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
453 * @param htim TIM Hall Sensor Interface handle
454 * @retval HAL status
455 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)456 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
457 {
458 /* Check the parameters */
459 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
460
461 /* Disable the Input Capture channel 1
462 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
463 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
464 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
465
466 /* Disable the capture compare Interrupts event */
467 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
468
469 /* Disable the Peripheral */
470 __HAL_TIM_DISABLE(htim);
471
472 /* Set the TIM channels state */
473 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
474 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
475 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
476 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
477
478 /* Return function status */
479 return HAL_OK;
480 }
481
482 /**
483 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
484 * @param htim TIM Hall Sensor Interface handle
485 * @param pData The destination Buffer address.
486 * @param Length The length of data to be transferred from TIM peripheral to memory.
487 * @retval HAL status
488 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)489 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
490 {
491 uint32_t tmpsmcr;
492 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
493 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
494
495 /* Check the parameters */
496 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
497
498 /* Set the TIM channel state */
499 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
500 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
501 {
502 return HAL_BUSY;
503 }
504 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
505 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
506 {
507 if ((pData == NULL) || (Length == 0U))
508 {
509 return HAL_ERROR;
510 }
511 else
512 {
513 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
514 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
515 }
516 }
517 else
518 {
519 return HAL_ERROR;
520 }
521
522 /* Enable the Input Capture channel 1
523 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
524 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
525 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
526
527 /* Set the DMA Input Capture 1 Callbacks */
528 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
529 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
530 /* Set the DMA error callback */
531 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
532
533 /* Enable the DMA channel for Capture 1*/
534 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
535 {
536 /* Return error status */
537 return HAL_ERROR;
538 }
539 /* Enable the capture compare 1 Interrupt */
540 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
541
542 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
543 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
544 {
545 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
546 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
547 {
548 __HAL_TIM_ENABLE(htim);
549 }
550 }
551 else
552 {
553 __HAL_TIM_ENABLE(htim);
554 }
555
556 /* Return function status */
557 return HAL_OK;
558 }
559
560 /**
561 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
562 * @param htim TIM Hall Sensor Interface handle
563 * @retval HAL status
564 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)565 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
566 {
567 /* Check the parameters */
568 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
569
570 /* Disable the Input Capture channel 1
571 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
572 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
573 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
574
575
576 /* Disable the capture compare Interrupts 1 event */
577 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
578
579 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
580
581 /* Disable the Peripheral */
582 __HAL_TIM_DISABLE(htim);
583
584 /* Set the TIM channel state */
585 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
586 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
587
588 /* Return function status */
589 return HAL_OK;
590 }
591
592 /**
593 * @}
594 */
595
596 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
597 * @brief Timer Complementary Output Compare functions
598 *
599 @verbatim
600 ==============================================================================
601 ##### Timer Complementary Output Compare functions #####
602 ==============================================================================
603 [..]
604 This section provides functions allowing to:
605 (+) Start the Complementary Output Compare/PWM.
606 (+) Stop the Complementary Output Compare/PWM.
607 (+) Start the Complementary Output Compare/PWM and enable interrupts.
608 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
609 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
610 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
611
612 @endverbatim
613 * @{
614 */
615
616 /**
617 * @brief Starts the TIM Output Compare signal generation on the complementary
618 * output.
619 * @param htim TIM Output Compare handle
620 * @param Channel TIM Channel to be enabled
621 * This parameter can be one of the following values:
622 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
623 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
624 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
625 * @retval HAL status
626 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)627 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
628 {
629 uint32_t tmpsmcr;
630
631 /* Check the parameters */
632 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
633
634 /* Check the TIM complementary channel state */
635 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
636 {
637 return HAL_ERROR;
638 }
639
640 /* Set the TIM complementary channel state */
641 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
642
643 /* Enable the Capture compare channel N */
644 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
645
646 /* Enable the Main Output */
647 __HAL_TIM_MOE_ENABLE(htim);
648
649 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
650 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
651 {
652 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
653 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
654 {
655 __HAL_TIM_ENABLE(htim);
656 }
657 }
658 else
659 {
660 __HAL_TIM_ENABLE(htim);
661 }
662
663 /* Return function status */
664 return HAL_OK;
665 }
666
667 /**
668 * @brief Stops the TIM Output Compare signal generation on the complementary
669 * output.
670 * @param htim TIM handle
671 * @param Channel TIM Channel to be disabled
672 * This parameter can be one of the following values:
673 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
674 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
675 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
676 * @retval HAL status
677 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)678 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
679 {
680 /* Check the parameters */
681 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
682
683 /* Disable the Capture compare channel N */
684 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
685
686 /* Disable the Main Output */
687 __HAL_TIM_MOE_DISABLE(htim);
688
689 /* Disable the Peripheral */
690 __HAL_TIM_DISABLE(htim);
691
692 /* Set the TIM complementary channel state */
693 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
694
695 /* Return function status */
696 return HAL_OK;
697 }
698
699 /**
700 * @brief Starts the TIM Output Compare signal generation in interrupt mode
701 * on the complementary output.
702 * @param htim TIM OC handle
703 * @param Channel TIM Channel to be enabled
704 * This parameter can be one of the following values:
705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
708 * @retval HAL status
709 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)710 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
711 {
712 HAL_StatusTypeDef status = HAL_OK;
713 uint32_t tmpsmcr;
714
715 /* Check the parameters */
716 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
717
718 /* Check the TIM complementary channel state */
719 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
720 {
721 return HAL_ERROR;
722 }
723
724 /* Set the TIM complementary channel state */
725 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
726
727 switch (Channel)
728 {
729 case TIM_CHANNEL_1:
730 {
731 /* Enable the TIM Output Compare interrupt */
732 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
733 break;
734 }
735
736 case TIM_CHANNEL_2:
737 {
738 /* Enable the TIM Output Compare interrupt */
739 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
740 break;
741 }
742
743 case TIM_CHANNEL_3:
744 {
745 /* Enable the TIM Output Compare interrupt */
746 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
747 break;
748 }
749
750
751 default:
752 status = HAL_ERROR;
753 break;
754 }
755
756 if (status == HAL_OK)
757 {
758 /* Enable the TIM Break interrupt */
759 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
760
761 /* Enable the Capture compare channel N */
762 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
763
764 /* Enable the Main Output */
765 __HAL_TIM_MOE_ENABLE(htim);
766
767 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
768 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
769 {
770 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
771 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
772 {
773 __HAL_TIM_ENABLE(htim);
774 }
775 }
776 else
777 {
778 __HAL_TIM_ENABLE(htim);
779 }
780 }
781
782 /* Return function status */
783 return status;
784 }
785
786 /**
787 * @brief Stops the TIM Output Compare signal generation in interrupt mode
788 * on the complementary output.
789 * @param htim TIM Output Compare handle
790 * @param Channel TIM Channel to be disabled
791 * This parameter can be one of the following values:
792 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
793 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
794 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
795 * @retval HAL status
796 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)797 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
798 {
799 HAL_StatusTypeDef status = HAL_OK;
800 uint32_t tmpccer;
801
802 /* Check the parameters */
803 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
804
805 switch (Channel)
806 {
807 case TIM_CHANNEL_1:
808 {
809 /* Disable the TIM Output Compare interrupt */
810 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
811 break;
812 }
813
814 case TIM_CHANNEL_2:
815 {
816 /* Disable the TIM Output Compare interrupt */
817 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
818 break;
819 }
820
821 case TIM_CHANNEL_3:
822 {
823 /* Disable the TIM Output Compare interrupt */
824 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
825 break;
826 }
827
828 default:
829 status = HAL_ERROR;
830 break;
831 }
832
833 if (status == HAL_OK)
834 {
835 /* Disable the Capture compare channel N */
836 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
837
838 /* Disable the TIM Break interrupt (only if no more channel is active) */
839 tmpccer = htim->Instance->CCER;
840 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
841 {
842 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
843 }
844
845 /* Disable the Main Output */
846 __HAL_TIM_MOE_DISABLE(htim);
847
848 /* Disable the Peripheral */
849 __HAL_TIM_DISABLE(htim);
850
851 /* Set the TIM complementary channel state */
852 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
853 }
854
855 /* Return function status */
856 return status;
857 }
858
859 /**
860 * @brief Starts the TIM Output Compare signal generation in DMA mode
861 * on the complementary output.
862 * @param htim TIM Output Compare handle
863 * @param Channel TIM Channel to be enabled
864 * This parameter can be one of the following values:
865 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
866 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
867 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
868 * @param pData The source Buffer address.
869 * @param Length The length of data to be transferred from memory to TIM peripheral
870 * @retval HAL status
871 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)872 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
873 uint16_t Length)
874 {
875 HAL_StatusTypeDef status = HAL_OK;
876 uint32_t tmpsmcr;
877
878 /* Check the parameters */
879 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
880
881 /* Set the TIM complementary channel state */
882 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
883 {
884 return HAL_BUSY;
885 }
886 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
887 {
888 if ((pData == NULL) || (Length == 0U))
889 {
890 return HAL_ERROR;
891 }
892 else
893 {
894 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
895 }
896 }
897 else
898 {
899 return HAL_ERROR;
900 }
901
902 switch (Channel)
903 {
904 case TIM_CHANNEL_1:
905 {
906 /* Set the DMA compare callbacks */
907 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
908 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
909
910 /* Set the DMA error callback */
911 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
912
913 /* Enable the DMA channel */
914 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
915 Length) != HAL_OK)
916 {
917 /* Return error status */
918 return HAL_ERROR;
919 }
920 /* Enable the TIM Output Compare DMA request */
921 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
922 break;
923 }
924
925 case TIM_CHANNEL_2:
926 {
927 /* Set the DMA compare callbacks */
928 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
929 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
930
931 /* Set the DMA error callback */
932 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
933
934 /* Enable the DMA channel */
935 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
936 Length) != HAL_OK)
937 {
938 /* Return error status */
939 return HAL_ERROR;
940 }
941 /* Enable the TIM Output Compare DMA request */
942 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
943 break;
944 }
945
946 case TIM_CHANNEL_3:
947 {
948 /* Set the DMA compare callbacks */
949 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
950 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
951
952 /* Set the DMA error callback */
953 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
954
955 /* Enable the DMA channel */
956 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
957 Length) != HAL_OK)
958 {
959 /* Return error status */
960 return HAL_ERROR;
961 }
962 /* Enable the TIM Output Compare DMA request */
963 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
964 break;
965 }
966
967 default:
968 status = HAL_ERROR;
969 break;
970 }
971
972 if (status == HAL_OK)
973 {
974 /* Enable the Capture compare channel N */
975 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
976
977 /* Enable the Main Output */
978 __HAL_TIM_MOE_ENABLE(htim);
979
980 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
981 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
982 {
983 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
984 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
985 {
986 __HAL_TIM_ENABLE(htim);
987 }
988 }
989 else
990 {
991 __HAL_TIM_ENABLE(htim);
992 }
993 }
994
995 /* Return function status */
996 return status;
997 }
998
999 /**
1000 * @brief Stops the TIM Output Compare signal generation in DMA mode
1001 * on the complementary output.
1002 * @param htim TIM Output Compare handle
1003 * @param Channel TIM Channel to be disabled
1004 * This parameter can be one of the following values:
1005 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1006 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1007 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1008 * @retval HAL status
1009 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1010 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1011 {
1012 HAL_StatusTypeDef status = HAL_OK;
1013
1014 /* Check the parameters */
1015 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1016
1017 switch (Channel)
1018 {
1019 case TIM_CHANNEL_1:
1020 {
1021 /* Disable the TIM Output Compare DMA request */
1022 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1023 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1024 break;
1025 }
1026
1027 case TIM_CHANNEL_2:
1028 {
1029 /* Disable the TIM Output Compare DMA request */
1030 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1031 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1032 break;
1033 }
1034
1035 case TIM_CHANNEL_3:
1036 {
1037 /* Disable the TIM Output Compare DMA request */
1038 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1039 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1040 break;
1041 }
1042
1043 default:
1044 status = HAL_ERROR;
1045 break;
1046 }
1047
1048 if (status == HAL_OK)
1049 {
1050 /* Disable the Capture compare channel N */
1051 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1052
1053 /* Disable the Main Output */
1054 __HAL_TIM_MOE_DISABLE(htim);
1055
1056 /* Disable the Peripheral */
1057 __HAL_TIM_DISABLE(htim);
1058
1059 /* Set the TIM complementary channel state */
1060 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1061 }
1062
1063 /* Return function status */
1064 return status;
1065 }
1066
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1072 * @brief Timer Complementary PWM functions
1073 *
1074 @verbatim
1075 ==============================================================================
1076 ##### Timer Complementary PWM functions #####
1077 ==============================================================================
1078 [..]
1079 This section provides functions allowing to:
1080 (+) Start the Complementary PWM.
1081 (+) Stop the Complementary PWM.
1082 (+) Start the Complementary PWM and enable interrupts.
1083 (+) Stop the Complementary PWM and disable interrupts.
1084 (+) Start the Complementary PWM and enable DMA transfers.
1085 (+) Stop the Complementary PWM and disable DMA transfers.
1086 @endverbatim
1087 * @{
1088 */
1089
1090 /**
1091 * @brief Starts the PWM signal generation on the complementary output.
1092 * @param htim TIM handle
1093 * @param Channel TIM Channel to be enabled
1094 * This parameter can be one of the following values:
1095 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1096 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1097 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1098 * @retval HAL status
1099 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1100 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1101 {
1102 uint32_t tmpsmcr;
1103
1104 /* Check the parameters */
1105 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1106
1107 /* Check the TIM complementary channel state */
1108 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1109 {
1110 return HAL_ERROR;
1111 }
1112
1113 /* Set the TIM complementary channel state */
1114 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1115
1116 /* Enable the complementary PWM output */
1117 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1118
1119 /* Enable the Main Output */
1120 __HAL_TIM_MOE_ENABLE(htim);
1121
1122 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1123 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1124 {
1125 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1126 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1127 {
1128 __HAL_TIM_ENABLE(htim);
1129 }
1130 }
1131 else
1132 {
1133 __HAL_TIM_ENABLE(htim);
1134 }
1135
1136 /* Return function status */
1137 return HAL_OK;
1138 }
1139
1140 /**
1141 * @brief Stops the PWM signal generation on the complementary output.
1142 * @param htim TIM handle
1143 * @param Channel TIM Channel to be disabled
1144 * This parameter can be one of the following values:
1145 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1146 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1147 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1148 * @retval HAL status
1149 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1150 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1151 {
1152 /* Check the parameters */
1153 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1154
1155 /* Disable the complementary PWM output */
1156 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1157
1158 /* Disable the Main Output */
1159 __HAL_TIM_MOE_DISABLE(htim);
1160
1161 /* Disable the Peripheral */
1162 __HAL_TIM_DISABLE(htim);
1163
1164 /* Set the TIM complementary channel state */
1165 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1166
1167 /* Return function status */
1168 return HAL_OK;
1169 }
1170
1171 /**
1172 * @brief Starts the PWM signal generation in interrupt mode on the
1173 * complementary output.
1174 * @param htim TIM handle
1175 * @param Channel TIM Channel to be disabled
1176 * This parameter can be one of the following values:
1177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1179 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1180 * @retval HAL status
1181 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1182 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1183 {
1184 HAL_StatusTypeDef status = HAL_OK;
1185 uint32_t tmpsmcr;
1186
1187 /* Check the parameters */
1188 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1189
1190 /* Check the TIM complementary channel state */
1191 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1192 {
1193 return HAL_ERROR;
1194 }
1195
1196 /* Set the TIM complementary channel state */
1197 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1198
1199 switch (Channel)
1200 {
1201 case TIM_CHANNEL_1:
1202 {
1203 /* Enable the TIM Capture/Compare 1 interrupt */
1204 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1205 break;
1206 }
1207
1208 case TIM_CHANNEL_2:
1209 {
1210 /* Enable the TIM Capture/Compare 2 interrupt */
1211 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1212 break;
1213 }
1214
1215 case TIM_CHANNEL_3:
1216 {
1217 /* Enable the TIM Capture/Compare 3 interrupt */
1218 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1219 break;
1220 }
1221
1222 default:
1223 status = HAL_ERROR;
1224 break;
1225 }
1226
1227 if (status == HAL_OK)
1228 {
1229 /* Enable the TIM Break interrupt */
1230 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1231
1232 /* Enable the complementary PWM output */
1233 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1234
1235 /* Enable the Main Output */
1236 __HAL_TIM_MOE_ENABLE(htim);
1237
1238 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1239 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1240 {
1241 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1242 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1243 {
1244 __HAL_TIM_ENABLE(htim);
1245 }
1246 }
1247 else
1248 {
1249 __HAL_TIM_ENABLE(htim);
1250 }
1251 }
1252
1253 /* Return function status */
1254 return status;
1255 }
1256
1257 /**
1258 * @brief Stops the PWM signal generation in interrupt mode on the
1259 * complementary output.
1260 * @param htim TIM handle
1261 * @param Channel TIM Channel to be disabled
1262 * This parameter can be one of the following values:
1263 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1264 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1265 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1266 * @retval HAL status
1267 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1268 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1269 {
1270 HAL_StatusTypeDef status = HAL_OK;
1271 uint32_t tmpccer;
1272
1273 /* Check the parameters */
1274 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1275
1276 switch (Channel)
1277 {
1278 case TIM_CHANNEL_1:
1279 {
1280 /* Disable the TIM Capture/Compare 1 interrupt */
1281 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1282 break;
1283 }
1284
1285 case TIM_CHANNEL_2:
1286 {
1287 /* Disable the TIM Capture/Compare 2 interrupt */
1288 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1289 break;
1290 }
1291
1292 case TIM_CHANNEL_3:
1293 {
1294 /* Disable the TIM Capture/Compare 3 interrupt */
1295 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1296 break;
1297 }
1298
1299 default:
1300 status = HAL_ERROR;
1301 break;
1302 }
1303
1304 if (status == HAL_OK)
1305 {
1306 /* Disable the complementary PWM output */
1307 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1308
1309 /* Disable the TIM Break interrupt (only if no more channel is active) */
1310 tmpccer = htim->Instance->CCER;
1311 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1312 {
1313 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1314 }
1315
1316 /* Disable the Main Output */
1317 __HAL_TIM_MOE_DISABLE(htim);
1318
1319 /* Disable the Peripheral */
1320 __HAL_TIM_DISABLE(htim);
1321
1322 /* Set the TIM complementary channel state */
1323 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1324 }
1325
1326 /* Return function status */
1327 return status;
1328 }
1329
1330 /**
1331 * @brief Starts the TIM PWM signal generation in DMA mode on the
1332 * complementary output
1333 * @param htim TIM handle
1334 * @param Channel TIM Channel to be enabled
1335 * This parameter can be one of the following values:
1336 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1337 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1338 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1339 * @param pData The source Buffer address.
1340 * @param Length The length of data to be transferred from memory to TIM peripheral
1341 * @retval HAL status
1342 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1343 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1344 uint16_t Length)
1345 {
1346 HAL_StatusTypeDef status = HAL_OK;
1347 uint32_t tmpsmcr;
1348
1349 /* Check the parameters */
1350 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1351
1352 /* Set the TIM complementary channel state */
1353 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1354 {
1355 return HAL_BUSY;
1356 }
1357 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1358 {
1359 if ((pData == NULL) || (Length == 0U))
1360 {
1361 return HAL_ERROR;
1362 }
1363 else
1364 {
1365 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1366 }
1367 }
1368 else
1369 {
1370 return HAL_ERROR;
1371 }
1372
1373 switch (Channel)
1374 {
1375 case TIM_CHANNEL_1:
1376 {
1377 /* Set the DMA compare callbacks */
1378 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1379 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1380
1381 /* Set the DMA error callback */
1382 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1383
1384 /* Enable the DMA channel */
1385 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1386 Length) != HAL_OK)
1387 {
1388 /* Return error status */
1389 return HAL_ERROR;
1390 }
1391 /* Enable the TIM Capture/Compare 1 DMA request */
1392 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1393 break;
1394 }
1395
1396 case TIM_CHANNEL_2:
1397 {
1398 /* Set the DMA compare callbacks */
1399 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1400 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1401
1402 /* Set the DMA error callback */
1403 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1404
1405 /* Enable the DMA channel */
1406 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1407 Length) != HAL_OK)
1408 {
1409 /* Return error status */
1410 return HAL_ERROR;
1411 }
1412 /* Enable the TIM Capture/Compare 2 DMA request */
1413 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1414 break;
1415 }
1416
1417 case TIM_CHANNEL_3:
1418 {
1419 /* Set the DMA compare callbacks */
1420 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1421 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1422
1423 /* Set the DMA error callback */
1424 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1425
1426 /* Enable the DMA channel */
1427 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1428 Length) != HAL_OK)
1429 {
1430 /* Return error status */
1431 return HAL_ERROR;
1432 }
1433 /* Enable the TIM Capture/Compare 3 DMA request */
1434 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1435 break;
1436 }
1437
1438 default:
1439 status = HAL_ERROR;
1440 break;
1441 }
1442
1443 if (status == HAL_OK)
1444 {
1445 /* Enable the complementary PWM output */
1446 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1447
1448 /* Enable the Main Output */
1449 __HAL_TIM_MOE_ENABLE(htim);
1450
1451 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1452 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1453 {
1454 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1455 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1456 {
1457 __HAL_TIM_ENABLE(htim);
1458 }
1459 }
1460 else
1461 {
1462 __HAL_TIM_ENABLE(htim);
1463 }
1464 }
1465
1466 /* Return function status */
1467 return status;
1468 }
1469
1470 /**
1471 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1472 * output
1473 * @param htim TIM handle
1474 * @param Channel TIM Channel to be disabled
1475 * This parameter can be one of the following values:
1476 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1477 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1478 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1479 * @retval HAL status
1480 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1481 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1482 {
1483 HAL_StatusTypeDef status = HAL_OK;
1484
1485 /* Check the parameters */
1486 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1487
1488 switch (Channel)
1489 {
1490 case TIM_CHANNEL_1:
1491 {
1492 /* Disable the TIM Capture/Compare 1 DMA request */
1493 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1494 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1495 break;
1496 }
1497
1498 case TIM_CHANNEL_2:
1499 {
1500 /* Disable the TIM Capture/Compare 2 DMA request */
1501 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1502 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1503 break;
1504 }
1505
1506 case TIM_CHANNEL_3:
1507 {
1508 /* Disable the TIM Capture/Compare 3 DMA request */
1509 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1510 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1511 break;
1512 }
1513
1514 default:
1515 status = HAL_ERROR;
1516 break;
1517 }
1518
1519 if (status == HAL_OK)
1520 {
1521 /* Disable the complementary PWM output */
1522 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1523
1524 /* Disable the Main Output */
1525 __HAL_TIM_MOE_DISABLE(htim);
1526
1527 /* Disable the Peripheral */
1528 __HAL_TIM_DISABLE(htim);
1529
1530 /* Set the TIM complementary channel state */
1531 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1532 }
1533
1534 /* Return function status */
1535 return status;
1536 }
1537
1538 /**
1539 * @}
1540 */
1541
1542 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1543 * @brief Timer Complementary One Pulse functions
1544 *
1545 @verbatim
1546 ==============================================================================
1547 ##### Timer Complementary One Pulse functions #####
1548 ==============================================================================
1549 [..]
1550 This section provides functions allowing to:
1551 (+) Start the Complementary One Pulse generation.
1552 (+) Stop the Complementary One Pulse.
1553 (+) Start the Complementary One Pulse and enable interrupts.
1554 (+) Stop the Complementary One Pulse and disable interrupts.
1555
1556 @endverbatim
1557 * @{
1558 */
1559
1560 /**
1561 * @brief Starts the TIM One Pulse signal generation on the complementary
1562 * output.
1563 * @note OutputChannel must match the pulse output channel chosen when calling
1564 * @ref HAL_TIM_OnePulse_ConfigChannel().
1565 * @param htim TIM One Pulse handle
1566 * @param OutputChannel pulse output channel to enable
1567 * This parameter can be one of the following values:
1568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1570 * @retval HAL status
1571 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1572 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1573 {
1574 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1575 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1576 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1577 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1578 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1579
1580 /* Check the parameters */
1581 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1582
1583 /* Check the TIM channels state */
1584 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1585 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1586 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1587 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1588 {
1589 return HAL_ERROR;
1590 }
1591
1592 /* Set the TIM channels state */
1593 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1594 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1595 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1596 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1597
1598 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1599 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1600 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1601
1602 /* Enable the Main Output */
1603 __HAL_TIM_MOE_ENABLE(htim);
1604
1605 /* Return function status */
1606 return HAL_OK;
1607 }
1608
1609 /**
1610 * @brief Stops the TIM One Pulse signal generation on the complementary
1611 * output.
1612 * @note OutputChannel must match the pulse output channel chosen when calling
1613 * @ref HAL_TIM_OnePulse_ConfigChannel().
1614 * @param htim TIM One Pulse handle
1615 * @param OutputChannel pulse output channel to disable
1616 * This parameter can be one of the following values:
1617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1619 * @retval HAL status
1620 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1621 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1622 {
1623 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1624
1625 /* Check the parameters */
1626 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1627
1628 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1629 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1630 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1631
1632 /* Disable the Main Output */
1633 __HAL_TIM_MOE_DISABLE(htim);
1634
1635 /* Disable the Peripheral */
1636 __HAL_TIM_DISABLE(htim);
1637
1638 /* Set the TIM channels state */
1639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1640 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1641 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1642 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1643
1644 /* Return function status */
1645 return HAL_OK;
1646 }
1647
1648 /**
1649 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1650 * complementary channel.
1651 * @note OutputChannel must match the pulse output channel chosen when calling
1652 * @ref HAL_TIM_OnePulse_ConfigChannel().
1653 * @param htim TIM One Pulse handle
1654 * @param OutputChannel pulse output channel to enable
1655 * This parameter can be one of the following values:
1656 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1657 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1658 * @retval HAL status
1659 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1660 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1661 {
1662 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1663 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1664 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1665 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1666 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1667
1668 /* Check the parameters */
1669 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1670
1671 /* Check the TIM channels state */
1672 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1673 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1674 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1675 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1676 {
1677 return HAL_ERROR;
1678 }
1679
1680 /* Set the TIM channels state */
1681 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1682 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1683 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1684 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1685
1686 /* Enable the TIM Capture/Compare 1 interrupt */
1687 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1688
1689 /* Enable the TIM Capture/Compare 2 interrupt */
1690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1691
1692 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1693 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1694 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1695
1696 /* Enable the Main Output */
1697 __HAL_TIM_MOE_ENABLE(htim);
1698
1699 /* Return function status */
1700 return HAL_OK;
1701 }
1702
1703 /**
1704 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1705 * complementary channel.
1706 * @note OutputChannel must match the pulse output channel chosen when calling
1707 * @ref HAL_TIM_OnePulse_ConfigChannel().
1708 * @param htim TIM One Pulse handle
1709 * @param OutputChannel pulse output channel to disable
1710 * This parameter can be one of the following values:
1711 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1712 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1713 * @retval HAL status
1714 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1715 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1716 {
1717 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1718
1719 /* Check the parameters */
1720 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1721
1722 /* Disable the TIM Capture/Compare 1 interrupt */
1723 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1724
1725 /* Disable the TIM Capture/Compare 2 interrupt */
1726 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1727
1728 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1729 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1730 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1731
1732 /* Disable the Main Output */
1733 __HAL_TIM_MOE_DISABLE(htim);
1734
1735 /* Disable the Peripheral */
1736 __HAL_TIM_DISABLE(htim);
1737
1738 /* Set the TIM channels state */
1739 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1740 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1741 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1742 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1743
1744 /* Return function status */
1745 return HAL_OK;
1746 }
1747
1748 /**
1749 * @}
1750 */
1751
1752 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1753 * @brief Peripheral Control functions
1754 *
1755 @verbatim
1756 ==============================================================================
1757 ##### Peripheral Control functions #####
1758 ==============================================================================
1759 [..]
1760 This section provides functions allowing to:
1761 (+) Configure the commutation event in case of use of the Hall sensor interface.
1762 (+) Configure Output channels for OC and PWM mode.
1763
1764 (+) Configure Complementary channels, break features and dead time.
1765 (+) Configure Master synchronization.
1766 (+) Configure timer remapping capabilities.
1767 (+) Enable or disable channel grouping.
1768
1769 @endverbatim
1770 * @{
1771 */
1772
1773 /**
1774 * @brief Configure the TIM commutation event sequence.
1775 * @note This function is mandatory to use the commutation event in order to
1776 * update the configuration at each commutation detection on the TRGI input of the Timer,
1777 * the typical use of this feature is with the use of another Timer(interface Timer)
1778 * configured in Hall sensor interface, this interface Timer will generate the
1779 * commutation at its TRGO output (connected to Timer used in this function) each time
1780 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1781 * @param htim TIM handle
1782 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1783 * This parameter can be one of the following values:
1784 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1785 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1786 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1787 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1788 * @arg TIM_TS_NONE: No trigger is needed
1789 * @param CommutationSource the Commutation Event source
1790 * This parameter can be one of the following values:
1791 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1792 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1793 * @retval HAL status
1794 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1795 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1796 uint32_t CommutationSource)
1797 {
1798 /* Check the parameters */
1799 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1800 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1801
1802 __HAL_LOCK(htim);
1803
1804 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1805 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1806 {
1807 /* Select the Input trigger */
1808 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1809 htim->Instance->SMCR |= InputTrigger;
1810 }
1811
1812 /* Select the Capture Compare preload feature */
1813 htim->Instance->CR2 |= TIM_CR2_CCPC;
1814 /* Select the Commutation event source */
1815 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1816 htim->Instance->CR2 |= CommutationSource;
1817
1818 /* Disable Commutation Interrupt */
1819 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1820
1821 /* Disable Commutation DMA request */
1822 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1823
1824 __HAL_UNLOCK(htim);
1825
1826 return HAL_OK;
1827 }
1828
1829 /**
1830 * @brief Configure the TIM commutation event sequence with interrupt.
1831 * @note This function is mandatory to use the commutation event in order to
1832 * update the configuration at each commutation detection on the TRGI input of the Timer,
1833 * the typical use of this feature is with the use of another Timer(interface Timer)
1834 * configured in Hall sensor interface, this interface Timer will generate the
1835 * commutation at its TRGO output (connected to Timer used in this function) each time
1836 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1837 * @param htim TIM handle
1838 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1839 * This parameter can be one of the following values:
1840 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1841 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1842 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1843 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1844 * @arg TIM_TS_NONE: No trigger is needed
1845 * @param CommutationSource the Commutation Event source
1846 * This parameter can be one of the following values:
1847 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1848 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1849 * @retval HAL status
1850 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1851 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1852 uint32_t CommutationSource)
1853 {
1854 /* Check the parameters */
1855 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1856 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1857
1858 __HAL_LOCK(htim);
1859
1860 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1861 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1862 {
1863 /* Select the Input trigger */
1864 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1865 htim->Instance->SMCR |= InputTrigger;
1866 }
1867
1868 /* Select the Capture Compare preload feature */
1869 htim->Instance->CR2 |= TIM_CR2_CCPC;
1870 /* Select the Commutation event source */
1871 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1872 htim->Instance->CR2 |= CommutationSource;
1873
1874 /* Disable Commutation DMA request */
1875 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1876
1877 /* Enable the Commutation Interrupt */
1878 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1879
1880 __HAL_UNLOCK(htim);
1881
1882 return HAL_OK;
1883 }
1884
1885 /**
1886 * @brief Configure the TIM commutation event sequence with DMA.
1887 * @note This function is mandatory to use the commutation event in order to
1888 * update the configuration at each commutation detection on the TRGI input of the Timer,
1889 * the typical use of this feature is with the use of another Timer(interface Timer)
1890 * configured in Hall sensor interface, this interface Timer will generate the
1891 * commutation at its TRGO output (connected to Timer used in this function) each time
1892 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1893 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
1894 * @param htim TIM handle
1895 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1896 * This parameter can be one of the following values:
1897 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1898 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1899 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1900 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1901 * @arg TIM_TS_NONE: No trigger is needed
1902 * @param CommutationSource the Commutation Event source
1903 * This parameter can be one of the following values:
1904 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1905 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1906 * @retval HAL status
1907 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1908 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1909 uint32_t CommutationSource)
1910 {
1911 /* Check the parameters */
1912 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1913 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1914
1915 __HAL_LOCK(htim);
1916
1917 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1918 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1919 {
1920 /* Select the Input trigger */
1921 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1922 htim->Instance->SMCR |= InputTrigger;
1923 }
1924
1925 /* Select the Capture Compare preload feature */
1926 htim->Instance->CR2 |= TIM_CR2_CCPC;
1927 /* Select the Commutation event source */
1928 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1929 htim->Instance->CR2 |= CommutationSource;
1930
1931 /* Enable the Commutation DMA Request */
1932 /* Set the DMA Commutation Callback */
1933 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
1934 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
1935 /* Set the DMA error callback */
1936 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
1937
1938 /* Disable Commutation Interrupt */
1939 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1940
1941 /* Enable the Commutation DMA Request */
1942 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1943
1944 __HAL_UNLOCK(htim);
1945
1946 return HAL_OK;
1947 }
1948
1949 /**
1950 * @brief Configures the TIM in master mode.
1951 * @param htim TIM handle.
1952 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
1953 * contains the selected trigger output (TRGO) and the Master/Slave
1954 * mode.
1955 * @retval HAL status
1956 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)1957 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
1958 const TIM_MasterConfigTypeDef *sMasterConfig)
1959 {
1960 uint32_t tmpcr2;
1961 uint32_t tmpsmcr;
1962
1963 /* Check the parameters */
1964 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
1965 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
1966 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
1967
1968 /* Check input state */
1969 __HAL_LOCK(htim);
1970
1971 /* Change the handler state */
1972 htim->State = HAL_TIM_STATE_BUSY;
1973
1974 /* Get the TIMx CR2 register value */
1975 tmpcr2 = htim->Instance->CR2;
1976
1977 /* Get the TIMx SMCR register value */
1978 tmpsmcr = htim->Instance->SMCR;
1979
1980 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
1981 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
1982 {
1983 /* Check the parameters */
1984 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
1985
1986 /* Clear the MMS2 bits */
1987 tmpcr2 &= ~TIM_CR2_MMS2;
1988 /* Select the TRGO2 source*/
1989 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
1990 }
1991
1992 /* Reset the MMS Bits */
1993 tmpcr2 &= ~TIM_CR2_MMS;
1994 /* Select the TRGO source */
1995 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
1996
1997 /* Update TIMx CR2 */
1998 htim->Instance->CR2 = tmpcr2;
1999
2000 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2001 {
2002 /* Reset the MSM Bit */
2003 tmpsmcr &= ~TIM_SMCR_MSM;
2004 /* Set master mode */
2005 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2006
2007 /* Update TIMx SMCR */
2008 htim->Instance->SMCR = tmpsmcr;
2009 }
2010
2011 /* Change the htim state */
2012 htim->State = HAL_TIM_STATE_READY;
2013
2014 __HAL_UNLOCK(htim);
2015
2016 return HAL_OK;
2017 }
2018
2019 /**
2020 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2021 * and the AOE(automatic output enable).
2022 * @param htim TIM handle
2023 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2024 * contains the BDTR Register configuration information for the TIM peripheral.
2025 * @note Interrupts can be generated when an active level is detected on the
2026 * break input, the break 2 input or the system break input. Break
2027 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2028 * @retval HAL status
2029 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2030 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2031 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2032 {
2033 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2034 uint32_t tmpbdtr = 0U;
2035
2036 /* Check the parameters */
2037 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2038 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2039 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2040 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2041 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2042 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2043 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2044 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2045 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2046
2047 /* Check input state */
2048 __HAL_LOCK(htim);
2049
2050 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2051 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2052
2053 /* Set the BDTR bits */
2054 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2055 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2056 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2057 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2058 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2059 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2060 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2061 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2062
2063 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2064 {
2065 /* Check the parameters */
2066 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2067 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2068 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2069
2070 /* Set the BREAK2 input related BDTR bits */
2071 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2072 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2073 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2074 }
2075
2076 /* Set TIMx_BDTR */
2077 htim->Instance->BDTR = tmpbdtr;
2078
2079 __HAL_UNLOCK(htim);
2080
2081 return HAL_OK;
2082 }
2083
2084 /**
2085 * @brief Configures the break input source.
2086 * @param htim TIM handle.
2087 * @param BreakInput Break input to configure
2088 * This parameter can be one of the following values:
2089 * @arg TIM_BREAKINPUT_BRK: Timer break input
2090 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2091 * @param sBreakInputConfig Break input source configuration
2092 * @retval HAL status
2093 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2094 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2095 uint32_t BreakInput,
2096 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2097 {
2098 HAL_StatusTypeDef status = HAL_OK;
2099 uint32_t tmporx;
2100 uint32_t bkin_enable_mask;
2101 uint32_t bkin_polarity_mask;
2102 uint32_t bkin_enable_bitpos;
2103 uint32_t bkin_polarity_bitpos;
2104
2105 /* Check the parameters */
2106 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2107 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2108 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2109 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2110 #if defined(DFSDM1_Channel0)
2111 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2112 {
2113 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2114 }
2115 #else
2116 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2117 #endif /* DFSDM1_Channel0 */
2118
2119 /* Check input state */
2120 __HAL_LOCK(htim);
2121
2122 switch (sBreakInputConfig->Source)
2123 {
2124 case TIM_BREAKINPUTSOURCE_BKIN:
2125 {
2126 bkin_enable_mask = TIM1_OR2_BKINE;
2127 bkin_enable_bitpos = TIM1_OR2_BKINE_Pos;
2128 bkin_polarity_mask = TIM1_OR2_BKINP;
2129 bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos;
2130 break;
2131 }
2132 case TIM_BREAKINPUTSOURCE_COMP1:
2133 {
2134 bkin_enable_mask = TIM1_OR2_BKCMP1E;
2135 bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos;
2136 bkin_polarity_mask = TIM1_OR2_BKCMP1P;
2137 bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos;
2138 break;
2139 }
2140 case TIM_BREAKINPUTSOURCE_COMP2:
2141 {
2142 bkin_enable_mask = TIM1_OR2_BKCMP2E;
2143 bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos;
2144 bkin_polarity_mask = TIM1_OR2_BKCMP2P;
2145 bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos;
2146 break;
2147 }
2148 #if defined(DFSDM1_Channel0)
2149 case TIM_BREAKINPUTSOURCE_DFSDM1:
2150 {
2151 bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
2152 bkin_enable_bitpos = TIM1_OR2_BKDF1BK0E_Pos;
2153 bkin_polarity_mask = 0U;
2154 bkin_polarity_bitpos = 0U;
2155 break;
2156 }
2157 #endif /* DFSDM1_Channel0 */
2158
2159 default:
2160 {
2161 bkin_enable_mask = 0U;
2162 bkin_polarity_mask = 0U;
2163 bkin_enable_bitpos = 0U;
2164 bkin_polarity_bitpos = 0U;
2165 break;
2166 }
2167 }
2168
2169 switch (BreakInput)
2170 {
2171 case TIM_BREAKINPUT_BRK:
2172 {
2173 /* Get the TIMx_OR2 register value */
2174 tmporx = htim->Instance->OR2;
2175
2176 /* Enable the break input */
2177 tmporx &= ~bkin_enable_mask;
2178 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2179
2180 /* Set the break input polarity */
2181 #if defined(DFSDM1_Channel0)
2182 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2183 #endif /* DFSDM1_Channel0 */
2184 {
2185 tmporx &= ~bkin_polarity_mask;
2186 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2187 }
2188
2189 /* Set TIMx_OR2 */
2190 htim->Instance->OR2 = tmporx;
2191 break;
2192 }
2193 case TIM_BREAKINPUT_BRK2:
2194 {
2195 /* Get the TIMx_OR3 register value */
2196 tmporx = htim->Instance->OR3;
2197
2198 /* Enable the break input */
2199 tmporx &= ~bkin_enable_mask;
2200 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2201
2202 /* Set the break input polarity */
2203 #if defined(DFSDM1_Channel0)
2204 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2205 #endif /* DFSDM1_Channel0 */
2206 {
2207 tmporx &= ~bkin_polarity_mask;
2208 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2209 }
2210
2211 /* Set TIMx_OR3 */
2212 htim->Instance->OR3 = tmporx;
2213 break;
2214 }
2215 default:
2216 status = HAL_ERROR;
2217 break;
2218 }
2219
2220 __HAL_UNLOCK(htim);
2221
2222 return status;
2223 }
2224
2225 /**
2226 * @brief Configures the TIMx Remapping input capabilities.
2227 * @param htim TIM handle.
2228 * @param Remap specifies the TIM remapping source.
2229 @if STM32L422xx
2230 * For TIM1, the parameter is a combination of 2 fields (field1 | field2):
2231 *
2232 * field1 can have the following values:
2233 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
2234 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2235 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2236 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2237 *
2238 * field2 can have the following values:
2239 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2240 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2241 *
2242 @endif
2243 @if STM32L486xx
2244 * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
2245 *
2246 * field1 can have the following values:
2247 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
2248 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2249 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2250 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2251 *
2252 * field2 can have the following values:
2253 * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
2254 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
2255 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
2256 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
2257 *
2258 * field3 can have the following values:
2259 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2260 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2261 *
2262 * field4 can have the following values:
2263 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
2264 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
2265 * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
2266 @endif
2267 @if STM32L443xx
2268 * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
2269 *
2270 * field1 can have the following values:
2271 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
2272 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2273 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2274 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2275 *
2276 * field2 can have the following values:
2277 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2278 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2279 *
2280 * field3 can have the following values:
2281 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
2282 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
2283 *
2284 * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant
2285 *
2286 @endif
2287 @if STM32L486xx
2288 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
2289 *
2290 * field1 can have the following values:
2291 * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
2292 * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF
2293 *
2294 * field2 can have the following values:
2295 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
2296 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
2297 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
2298 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
2299 *
2300 * field3 can have the following values:
2301 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2302 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2303 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2304 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
2305 @endif
2306 @if STM32L422xx
2307 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
2308 *
2309 * field1 can have the following values:
2310 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
2311 * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
2312 *
2313 * field2 can have the following values:
2314 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
2315 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
2316 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
2317 *
2318 * field3 can have the following values:
2319 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2320 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2321 *
2322 @endif
2323 @if STM32L443xx
2324 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
2325 *
2326 * field1 can have the following values:
2327 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
2328 * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
2329 *
2330 * field2 can have the following values:
2331 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
2332 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
2333 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
2334 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
2335 *
2336 * field3 can have the following values:
2337 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2338 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2339 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2340 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
2341 *
2342 @endif
2343 @if STM32L486xx
2344 * For TIM3, the parameter is a combination 2 fields(field1 | field2):
2345 *
2346 * field1 can have the following values:
2347 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2348 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2349 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
2350 * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
2351 *
2352 * field2 can have the following values:
2353 * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
2354 * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
2355 *
2356 @endif
2357 @if STM32L486xx
2358 * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
2359 *
2360 * field1 can have the following values:
2361 * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
2362 * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
2363 * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
2364 * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
2365 *
2366 * field2 can have the following values:
2367 * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
2368 * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
2369 * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
2370 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
2371 *
2372 * field3 can have the following values:
2373 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
2374 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
2375 *
2376 * field4 can have the following values:
2377 * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
2378 * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
2379 * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
2380 *
2381 @endif
2382 @if STM32L422xx
2383 * For TIM15, the parameter is a combination of 2 fields (field1 | field2):
2384 *
2385 * field1 can have the following values:
2386 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2387 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
2388 *
2389 * field2 can have the following values:
2390 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
2391 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
2392 *
2393 @endif
2394 @if STM32L443xx
2395 * For TIM15, the parameter is a combination of 2 fields (field1 | field2):
2396 *
2397 * field1 can have the following values:
2398 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2399 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
2400 *
2401 * field2 can have the following values:
2402 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
2403 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
2404 * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
2405 * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
2406 *
2407 @endif
2408 @if STM32L486xx
2409 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2410 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2411 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2412 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
2413 *
2414 @endif
2415 @if STM32L422xx
2416 * For TIM16, the parameter can have the following values:
2417 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2418 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2419 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2420 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
2421 * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
2422 * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
2423 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
2424 *
2425 @endif
2426 @if STM32L443xx
2427 * For TIM16, the parameter can have the following values:
2428 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2429 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2430 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2431 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
2432 * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
2433 * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
2434 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
2435 *
2436 @endif
2437 @if STM32L486xx
2438 * For TIM17, the parameter can have the following values:
2439 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2440 * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
2441 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
2442 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
2443 @endif
2444 *
2445 * @retval HAL status
2446 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2447 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2448 {
2449 uint32_t tmpor1;
2450 uint32_t tmpor2;
2451
2452 /* Check parameters */
2453 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2454 assert_param(IS_TIM_REMAP(Remap));
2455
2456 __HAL_LOCK(htim);
2457
2458 /* Set ETR_SEL bit field (if required) */
2459 if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
2460 {
2461 tmpor2 = htim->Instance->OR2;
2462 tmpor2 &= ~TIM1_OR2_ETRSEL_Msk;
2463 tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk);
2464
2465 /* Set TIMx_OR2 */
2466 htim->Instance->OR2 = tmpor2;
2467 }
2468
2469 /* Set other remapping capabilities */
2470 tmpor1 = Remap;
2471 tmpor1 &= ~TIM1_OR2_ETRSEL_Msk;
2472
2473 /* Set TIMx_OR1 */
2474 htim->Instance->OR1 = tmpor1;
2475
2476 __HAL_UNLOCK(htim);
2477
2478 return HAL_OK;
2479 }
2480
2481 /**
2482 * @brief Group channel 5 and channel 1, 2 or 3
2483 * @param htim TIM handle.
2484 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2485 * This parameter can be any combination of the following values:
2486 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2487 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2488 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2489 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2490 * @retval HAL status
2491 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2492 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2493 {
2494 /* Check parameters */
2495 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2496 assert_param(IS_TIM_GROUPCH5(Channels));
2497
2498 /* Process Locked */
2499 __HAL_LOCK(htim);
2500
2501 htim->State = HAL_TIM_STATE_BUSY;
2502
2503 /* Clear GC5Cx bit fields */
2504 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2505
2506 /* Set GC5Cx bit fields */
2507 htim->Instance->CCR5 |= Channels;
2508
2509 /* Change the htim state */
2510 htim->State = HAL_TIM_STATE_READY;
2511
2512 __HAL_UNLOCK(htim);
2513
2514 return HAL_OK;
2515 }
2516
2517 /**
2518 * @}
2519 */
2520
2521 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2522 * @brief Extended Callbacks functions
2523 *
2524 @verbatim
2525 ==============================================================================
2526 ##### Extended Callbacks functions #####
2527 ==============================================================================
2528 [..]
2529 This section provides Extended TIM callback functions:
2530 (+) Timer Commutation callback
2531 (+) Timer Break callback
2532
2533 @endverbatim
2534 * @{
2535 */
2536
2537 /**
2538 * @brief Commutation callback in non-blocking mode
2539 * @param htim TIM handle
2540 * @retval None
2541 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)2542 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
2543 {
2544 /* Prevent unused argument(s) compilation warning */
2545 UNUSED(htim);
2546
2547 /* NOTE : This function should not be modified, when the callback is needed,
2548 the HAL_TIMEx_CommutCallback could be implemented in the user file
2549 */
2550 }
2551 /**
2552 * @brief Commutation half complete callback in non-blocking mode
2553 * @param htim TIM handle
2554 * @retval None
2555 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)2556 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
2557 {
2558 /* Prevent unused argument(s) compilation warning */
2559 UNUSED(htim);
2560
2561 /* NOTE : This function should not be modified, when the callback is needed,
2562 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
2563 */
2564 }
2565
2566 /**
2567 * @brief Break detection callback in non-blocking mode
2568 * @param htim TIM handle
2569 * @retval None
2570 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)2571 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2572 {
2573 /* Prevent unused argument(s) compilation warning */
2574 UNUSED(htim);
2575
2576 /* NOTE : This function should not be modified, when the callback is needed,
2577 the HAL_TIMEx_BreakCallback could be implemented in the user file
2578 */
2579 }
2580
2581 /**
2582 * @brief Break2 detection callback in non blocking mode
2583 * @param htim: TIM handle
2584 * @retval None
2585 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)2586 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
2587 {
2588 /* Prevent unused argument(s) compilation warning */
2589 UNUSED(htim);
2590
2591 /* NOTE : This function Should not be modified, when the callback is needed,
2592 the HAL_TIMEx_Break2Callback could be implemented in the user file
2593 */
2594 }
2595 /**
2596 * @}
2597 */
2598
2599 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2600 * @brief Extended Peripheral State functions
2601 *
2602 @verbatim
2603 ==============================================================================
2604 ##### Extended Peripheral State functions #####
2605 ==============================================================================
2606 [..]
2607 This subsection permits to get in run-time the status of the peripheral
2608 and the data flow.
2609
2610 @endverbatim
2611 * @{
2612 */
2613
2614 /**
2615 * @brief Return the TIM Hall Sensor interface handle state.
2616 * @param htim TIM Hall Sensor handle
2617 * @retval HAL state
2618 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)2619 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
2620 {
2621 return htim->State;
2622 }
2623
2624 /**
2625 * @brief Return actual state of the TIM complementary channel.
2626 * @param htim TIM handle
2627 * @param ChannelN TIM Complementary channel
2628 * This parameter can be one of the following values:
2629 * @arg TIM_CHANNEL_1: TIM Channel 1
2630 * @arg TIM_CHANNEL_2: TIM Channel 2
2631 * @arg TIM_CHANNEL_3: TIM Channel 3
2632 * @retval TIM Complementary channel state
2633 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)2634 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
2635 {
2636 HAL_TIM_ChannelStateTypeDef channel_state;
2637
2638 /* Check the parameters */
2639 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
2640
2641 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
2642
2643 return channel_state;
2644 }
2645 /**
2646 * @}
2647 */
2648
2649 /**
2650 * @}
2651 */
2652
2653 /* Private functions ---------------------------------------------------------*/
2654 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
2655 * @{
2656 */
2657
2658 /**
2659 * @brief TIM DMA Commutation callback.
2660 * @param hdma pointer to DMA handle.
2661 * @retval None
2662 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)2663 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2664 {
2665 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2666
2667 /* Change the htim state */
2668 htim->State = HAL_TIM_STATE_READY;
2669
2670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2671 htim->CommutationCallback(htim);
2672 #else
2673 HAL_TIMEx_CommutCallback(htim);
2674 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2675 }
2676
2677 /**
2678 * @brief TIM DMA Commutation half complete callback.
2679 * @param hdma pointer to DMA handle.
2680 * @retval None
2681 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)2682 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
2683 {
2684 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2685
2686 /* Change the htim state */
2687 htim->State = HAL_TIM_STATE_READY;
2688
2689 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2690 htim->CommutationHalfCpltCallback(htim);
2691 #else
2692 HAL_TIMEx_CommutHalfCpltCallback(htim);
2693 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2694 }
2695
2696
2697 /**
2698 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
2699 * @param hdma pointer to DMA handle.
2700 * @retval None
2701 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)2702 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
2703 {
2704 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2705
2706 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2707 {
2708 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2709
2710 if (hdma->Init.Mode == DMA_NORMAL)
2711 {
2712 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2713 }
2714 }
2715 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2716 {
2717 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2718
2719 if (hdma->Init.Mode == DMA_NORMAL)
2720 {
2721 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2722 }
2723 }
2724 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2725 {
2726 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2727
2728 if (hdma->Init.Mode == DMA_NORMAL)
2729 {
2730 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2731 }
2732 }
2733 else
2734 {
2735 /* nothing to do */
2736 }
2737
2738 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2739 htim->PWM_PulseFinishedCallback(htim);
2740 #else
2741 HAL_TIM_PWM_PulseFinishedCallback(htim);
2742 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2743
2744 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2745 }
2746
2747 /**
2748 * @brief TIM DMA error callback (complementary channel)
2749 * @param hdma pointer to DMA handle.
2750 * @retval None
2751 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)2752 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
2753 {
2754 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2755
2756 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2757 {
2758 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2759 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2760 }
2761 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2762 {
2763 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2764 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2765 }
2766 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2767 {
2768 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2769 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2770 }
2771 else
2772 {
2773 /* nothing to do */
2774 }
2775
2776 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2777 htim->ErrorCallback(htim);
2778 #else
2779 HAL_TIM_ErrorCallback(htim);
2780 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2781
2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2783 }
2784
2785 /**
2786 * @brief Enables or disables the TIM Capture Compare Channel xN.
2787 * @param TIMx to select the TIM peripheral
2788 * @param Channel specifies the TIM Channel
2789 * This parameter can be one of the following values:
2790 * @arg TIM_CHANNEL_1: TIM Channel 1
2791 * @arg TIM_CHANNEL_2: TIM Channel 2
2792 * @arg TIM_CHANNEL_3: TIM Channel 3
2793 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
2794 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2795 * @retval None
2796 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)2797 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
2798 {
2799 uint32_t tmp;
2800
2801 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
2802
2803 /* Reset the CCxNE Bit */
2804 TIMx->CCER &= ~tmp;
2805
2806 /* Set or reset the CCxNE Bit */
2807 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
2808 }
2809 /**
2810 * @}
2811 */
2812
2813 #endif /* HAL_TIM_MODULE_ENABLED */
2814 /**
2815 * @}
2816 */
2817
2818 /**
2819 * @}
2820 */
2821
