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Searched refs:DMAMUX1_Channel0_BASE (Results 1 – 25 of 104) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h549 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
613 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32c031xx.h551 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
617 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32c071xx.h616 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
690 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h576 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
648 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g050xx.h586 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
665 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g070xx.h587 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
668 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g031xx.h614 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
691 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g041xx.h658 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
738 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g051xx.h663 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
752 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g061xx.h707 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
799 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g071xx.h707 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
801 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g081xx.h751 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
848 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32g0b0xx.h644 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
745 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h851 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
956 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wle5xx.h851 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
956 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32wb0x/soc/
Dstm32wb05.h909 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
972 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wb07.h960 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
1024 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wb09.h909 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
972 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wb06.h960 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
1024 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h793 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
850 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32u083xx.h914 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
989 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h820 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
906 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wb1mxx.h839 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
923 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h827 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
908 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
Dstm32wb15xx.h839 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) macro
923 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

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