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Searched refs:DESC2 (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/Legacy/
Dstm32h7xx_hal_eth.c714 WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2); in HAL_ETH_DescAssignMemory()
1165 WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); in HAL_ETH_IsRxDataAvailable()
1388 …RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCW… in HAL_ETH_GetRxDataInfo()
1389 …RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDES… in HAL_ETH_GetRxDataInfo()
1390 …RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESC… in HAL_ETH_GetRxDataInfo()
1436 WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); in HAL_ETH_BuildRxDescriptors()
2664 WRITE_REG(dmatxdesc->DESC2, 0x0); in ETH_DMATxDescListInit()
2700 WRITE_REG(dmarxdesc->DESC2, 0x0); in ETH_DMARxDescListInit()
2768 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); in ETH_Prepare_Tx_Descriptors()
2786 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); in ETH_Prepare_Tx_Descriptors()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_eth.c1441 CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_ReleaseTxPacket()
1749 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_PTP_InsertTxTimestamp()
3018 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
3055 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3128 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); in ETH_Prepare_Tx_Descriptors()
3146 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); in ETH_Prepare_Tx_Descriptors()
3189 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); in ETH_Prepare_Tx_Descriptors()
3197 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); in ETH_Prepare_Tx_Descriptors()
3203 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); in ETH_Prepare_Tx_Descriptors()
3233 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); in ETH_Prepare_Tx_Descriptors()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_eth.c1441 CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_ReleaseTxPacket()
1749 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_PTP_InsertTxTimestamp()
2970 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
3007 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3080 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); in ETH_Prepare_Tx_Descriptors()
3098 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); in ETH_Prepare_Tx_Descriptors()
3141 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); in ETH_Prepare_Tx_Descriptors()
3149 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); in ETH_Prepare_Tx_Descriptors()
3155 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); in ETH_Prepare_Tx_Descriptors()
3185 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); in ETH_Prepare_Tx_Descriptors()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_eth.c1731 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_PTP_InsertTxTimestamp()
2952 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
2989 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3062 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); in ETH_Prepare_Tx_Descriptors()
3080 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); in ETH_Prepare_Tx_Descriptors()
3123 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); in ETH_Prepare_Tx_Descriptors()
3131 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); in ETH_Prepare_Tx_Descriptors()
3137 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); in ETH_Prepare_Tx_Descriptors()
3167 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); in ETH_Prepare_Tx_Descriptors()
3230 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); in ETH_Prepare_Tx_Descriptors()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_eth.c1488 CLEAR_BIT(heth->Init.TxDesc[ch][idx].DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_ReleaseTxPacket()
1794 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); in HAL_ETH_PTP_InsertTxTimestamp()
3197 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
3241 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3320 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); in ETH_Prepare_Tx_Descriptors()
3338 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); in ETH_Prepare_Tx_Descriptors()
3381 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); in ETH_Prepare_Tx_Descriptors()
3389 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); in ETH_Prepare_Tx_Descriptors()
3395 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); in ETH_Prepare_Tx_Descriptors()
3425 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); in ETH_Prepare_Tx_Descriptors()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_eth.c1141 WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); in HAL_ETH_ReadData()
1229 WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); in ETH_UpdateDescriptor()
2962 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
3007 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3077 WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); in ETH_Prepare_Tx_Descriptors()
3155 WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); in ETH_Prepare_Tx_Descriptors()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_eth.c1141 WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); in HAL_ETH_ReadData()
1229 WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); in ETH_UpdateDescriptor()
2962 WRITE_REG(dmatxdesc->DESC2, 0x0U); in ETH_DMATxDescListInit()
3007 WRITE_REG(dmarxdesc->DESC2, 0x0U); in ETH_DMARxDescListInit()
3077 WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); in ETH_Prepare_Tx_Descriptors()
3155 WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); in ETH_Prepare_Tx_Descriptors()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_eth.h73 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_eth.h73 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_eth.h62 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_eth.h62 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_eth.h73 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/Legacy/
Dstm32h7xx_hal_eth_legacy.h62 __IO uint32_t DESC2; member
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_eth.h96 __IO uint32_t DESC2; member