1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_hal_eth.h
4   * @author  MCD Application Team
5   * @brief   Header file of ETH HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2022 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_HAL_ETH_H
21 #define STM32H7RSxx_HAL_ETH_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx_hal_def.h"
29 
30 #if defined(ETH)
31 
32 /** @addtogroup STM32H7RSxx_HAL_Driver
33   * @{
34   */
35 
36 /** @addtogroup ETH
37   * @{
38   */
39 
40 /* Exported types ------------------------------------------------------------*/
41 #ifndef ETH_TX_DESC_CNT
42 #define ETH_TX_DESC_CNT         4U
43 #endif /* ETH_TX_DESC_CNT */
44 
45 #ifndef ETH_RX_DESC_CNT
46 #define ETH_RX_DESC_CNT         4U
47 #endif /* ETH_RX_DESC_CNT */
48 
49 #ifndef ETH_SWRESET_TIMEOUT
50 #define ETH_SWRESET_TIMEOUT     500U
51 #endif /* ETH_SWRESET_TIMEOUT */
52 
53 #ifndef ETH_MDIO_BUS_TIMEOUT
54 #define ETH_MDIO_BUS_TIMEOUT    1000U
55 #endif /* ETH_MDIO_BUS_TIMEOUT */
56 
57 #ifndef ETH_MAC_US_TICK
58 #define ETH_MAC_US_TICK         1000000U
59 #endif /* ETH_MAC_US_TICK */
60 
61 /*********************** Descriptors struct def section ************************/
62 /** @defgroup ETH_Exported_Types ETH Exported Types
63   * @{
64   */
65 
66 /**
67   * @brief  ETH DMA Descriptor structure definition
68   */
69 typedef struct
70 {
71   __IO uint32_t DESC0;
72   __IO uint32_t DESC1;
73   __IO uint32_t DESC2;
74   __IO uint32_t DESC3;
75   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
76   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
77 } ETH_DMADescTypeDef;
78 /**
79   *
80   */
81 
82 /**
83   * @brief  ETH Buffers List structure definition
84   */
85 typedef struct __ETH_BufferTypeDef
86 {
87   uint8_t *buffer;                /*<! buffer address */
88 
89   uint32_t len;                   /*<! buffer length */
90 
91   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
92 } ETH_BufferTypeDef;
93 /**
94   *
95   */
96 
97 /**
98   * @brief  DMA Transmit Descriptors Wrapper structure definition
99   */
100 typedef struct
101 {
102   uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
103 
104   uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
105 
106   uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
107 
108   uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
109 
110   uint32_t BuffersInUse;                   /*<! Buffers in Use */
111 
112   uint32_t releaseIndex;                  /*<! Release index */
113 } ETH_TxDescListTypeDef;
114 /**
115   *
116   */
117 
118 /**
119   * @brief  Transmit Packet Configuration structure definition
120   */
121 typedef struct
122 {
123   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
124                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
125 
126   uint32_t Length;                  /*!< Total packet length   */
127 
128   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
129 
130   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
131                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
132 
133   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
134                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
135 
136   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
137                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
138 
139   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
140                                         This parameter can be a value from 0x0 to 0x3FFF */
141 
142   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
143                                         This parameter can be a value from 0x0 to 0x3FFFF */
144 
145   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
146                                         This parameter can be a value from 0x5 to 0xF */
147 
148   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
149                                         This parameter can be a value from 0x0 to 0xFFFF*/
150 
151   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
152                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
153 
154   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
155                                         This parameter can be a value from 0x0 to 0x3FFFF */
156 
157   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
158                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
159 
160   void *pData;                     /*!< Specifies Application packet pointer to save   */
161 
162 } ETH_TxPacketConfigTypeDef;
163 /**
164   *
165   */
166 
167 /**
168   * @brief  ETH Timestamp structure definition
169   */
170 typedef struct
171 {
172   uint32_t TimeStampLow;
173   uint32_t TimeStampHigh;
174 
175 } ETH_TimeStampTypeDef;
176 /**
177   *
178   */
179 
180 #ifdef HAL_ETH_USE_PTP
181 /**
182   * @brief  ETH Timeupdate structure definition
183   */
184 typedef struct
185 {
186   uint32_t Seconds;
187   uint32_t NanoSeconds;
188 } ETH_TimeTypeDef;
189 /**
190   *
191   */
192 #endif  /* HAL_ETH_USE_PTP */
193 
194 /**
195   * @brief  DMA Receive Descriptors Wrapper structure definition
196   */
197 typedef struct
198 {
199   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
200 
201   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
202                                              If 0, DMA will not generate the Rx complete interrupt. */
203 
204   uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
205 
206   uint32_t RxDescCnt;                 /*<! Number of descriptors . */
207 
208   uint32_t RxDataLength;              /*<! Received Data Length. */
209 
210   uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
211 
212   uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
213 
214   uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
215 
216   ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
217 
218   void *pRxStart;                     /*<! Pointer to the first buff. */
219 
220   void *pRxEnd;                       /*<! Pointer to the last buff. */
221 
222 } ETH_RxDescListTypeDef;
223 /**
224   *
225   */
226 
227 /**
228   * @brief  ETH MAC Configuration Structure definition
229   */
230 typedef struct
231 {
232   uint32_t
233   SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
234                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
235 
236   FunctionalState
237   ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
238 
239   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
240                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
241 
242   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
243 
244   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
245 
246   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
247 
248   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
249 
250   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
251 
252   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
253 
254   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
255                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
256                                                            without reporting a giant packet error */
257 
258   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
259                                                            This parameter can be a value of @ref ETH_Speed */
260 
261   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
262                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
263 
264   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
265 
266   FunctionalState
267   CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
268 
269   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
270 
271   FunctionalState
272   CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
273 
274   FunctionalState
275   RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
276 
277   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
278                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
279 
280   FunctionalState
281   DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
282 
283   uint32_t
284   PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
285                                                            This parameter can be a value of @ref ETH_Preamble_Length */
286 
287   FunctionalState
288   UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
289 
290   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
291 
292   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
293 
294   uint32_t
295   GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
296                                                     greater than the value programmed in this field in units of bytes
297                                                     This parameter must be a number between
298                                                     Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
299 
300   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
301 
302   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
303                                                            This parameter can be a value from 0x0 to 0xFF */
304 
305   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
306 
307   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
308                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
309 
310   uint32_t
311   PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
312                                                    This parameter must be a number between
313                                                    Min_Data = 0x0 and Max_Data = 0xFFFF.*/
314 
315   FunctionalState
316   ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
317 
318   uint32_t
319   PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
320                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
321 
322   FunctionalState
323   TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
324                                                    or the MAC back pressure operation in Half Duplex mode */
325 
326   FunctionalState
327   UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
328 
329   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
330                                                   and disables its transmitter for a specified (Pause) time */
331 
332   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
333                                                       This parameter can be a value of @ref ETH_Transmit_Mode */
334 
335   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
336                                                              This parameter can be a value of @ref ETH_Receive_Mode */
337 
338   FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
339 
340   FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
341 
342   FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
343 } ETH_MACConfigTypeDef;
344 /**
345   *
346   */
347 
348 /**
349   * @brief  ETH DMA Configuration Structure definition
350   */
351 typedef struct
352 {
353   uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
354                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
355 
356   FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
357                                                             burst transfers on Read and Write channels  */
358 
359   uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
360                                                      This parameter can be a value of @ref ETH_Burst_Mode */
361   FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
362                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
363 
364   FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
365 
366   uint32_t
367   TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
368                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
369 
370   FunctionalState
371   SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
372                                                       Packet of Transmit data even before
373                                                       obtaining the status for the first one. */
374 
375   uint32_t
376   RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
377                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
378 
379   FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
380 
381   FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
382 
383   uint32_t
384   MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
385                                                   This parameter can be a value from 0x40 to 0x3FFF */
386 
387 } ETH_DMAConfigTypeDef;
388 /**
389   *
390   */
391 
392 /**
393   * @brief  HAL ETH Media Interfaces enum definition
394   */
395 typedef enum
396 {
397   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
398   HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
399 } ETH_MediaInterfaceTypeDef;
400 /**
401   *
402   */
403 
404 #ifdef HAL_ETH_USE_PTP
405 /**
406   * @brief  HAL ETH PTP Update type enum definition
407   */
408 typedef enum
409 {
410   HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
411   HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
412 } ETH_PtpUpdateTypeDef;
413 /**
414   *
415   */
416 #endif  /* HAL_ETH_USE_PTP */
417 
418 /**
419   * @brief  ETH Init Structure definition
420   */
421 typedef struct
422 {
423   uint8_t
424   *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
425 
426   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
427 
428   ETH_DMADescTypeDef
429   *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
430 
431   ETH_DMADescTypeDef
432   *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
433 
434   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
435 
436 } ETH_InitTypeDef;
437 /**
438   *
439   */
440 
441 #ifdef HAL_ETH_USE_PTP
442 /**
443   * @brief  ETH PTP Init Structure definition
444   */
445 typedef struct
446 {
447   uint32_t                    Timestamp;                    /*!< Enable Timestamp */
448   uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
449   uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
450   uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
451   uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
452   uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
453   uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
454   uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
455   uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
456   uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
457   uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
458   uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
459   uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
460   uint32_t                    TimestampSnapshots;           /*!< Select PTP packets for Taking Snapshots */
461   uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
462   uint32_t
463   TimestampChecksumCorrection;  /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
464   uint32_t                    TimestampStatusMode;          /*!< Transmit Timestamp Status Mode */
465   uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
466   uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
467 
468 } ETH_PTP_ConfigTypeDef;
469 /**
470   *
471   */
472 #endif  /* HAL_ETH_USE_PTP */
473 
474 /**
475   * @brief  HAL State structures definition
476   */
477 typedef uint32_t HAL_ETH_StateTypeDef;
478 /**
479   *
480   */
481 
482 /**
483   * @brief  HAL ETH Rx Get Buffer Function definition
484   */
485 typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
486 /**
487   *
488   */
489 
490 /**
491   * @brief  HAL ETH Rx Set App Data Function definition
492   */
493 typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
494                                             uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
495 /**
496   *
497   */
498 
499 /**
500   * @brief  HAL ETH Tx Free Function definition
501   */
502 typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
503 /**
504   *
505   */
506 
507 /**
508   * @brief  HAL ETH Tx Free Function definition
509   */
510 typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
511                                            ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
512 /**
513   *
514   */
515 
516 /**
517   * @brief  ETH Handle Structure definition
518   */
519 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
520 typedef struct __ETH_HandleTypeDef
521 #else
522 typedef struct
523 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
524 {
525   ETH_TypeDef                *Instance;                 /*!< Register base address       */
526 
527   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
528 
529   ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
530                                                             addresses and current descriptor index  */
531 
532   ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
533                                                             addresses and current descriptor index  */
534 
535 #ifdef HAL_ETH_USE_PTP
536   ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
537 #endif /* HAL_ETH_USE_PTP */
538 
539   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
540                                                               and also related to Tx operations. This parameter can
541                                                               be a value of @ref ETH_State_Codes */
542 
543   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
544                                                              This parameter can be a value of @ref ETH_Error_Code.*/
545 
546   __IO uint32_t
547   DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
548                                                              This parameter can be a combination of
549                                                              @ref ETH_DMA_Status_Flags */
550 
551   __IO uint32_t
552   MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
553                                                              This parameter can be a combination of
554                                                              @ref ETH_MAC_Rx_Tx_Status */
555 
556   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
557                                                              This parameter can be a value of
558                                                              @ref ETH_MAC_Wake_Up_Event */
559 
560   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
561                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
562 
563   __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
564                                                              This parameter can be a value of
565                                                              @ref ETH_PTP_Config_Status */
566 
567 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
568 
569   void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
570   void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
571   void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
572   void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
573   void (* EEECallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH EEE Callback   */
574   void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
575 
576   void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
577   void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
578 
579 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
580 
581   pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
582   pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
583   pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
584   pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
585 
586 } ETH_HandleTypeDef;
587 /**
588   *
589   */
590 
591 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
592 /**
593   * @brief  HAL ETH Callback ID enumeration definition
594   */
595 typedef enum
596 {
597   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
598   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
599   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
600   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
601   HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
602   HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
603   HAL_ETH_EEE_CB_ID                = 0x07U,    /*!< ETH EEE Callback ID               */
604   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
605 
606 } HAL_ETH_CallbackIDTypeDef;
607 
608 /**
609   * @brief  HAL ETH Callback pointer definition
610   */
611 typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
612 
613 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
614 
615 /**
616   * @brief  ETH MAC filter structure definition
617   */
618 typedef struct
619 {
620   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
621 
622   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
623 
624   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
625 
626   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
627 
628   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
629 
630   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
631 
632   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
633 
634   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
635 
636   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
637 
638   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
639 
640   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
641                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
642 } ETH_MACFilterConfigTypeDef;
643 /**
644   *
645   */
646 
647 /**
648   * @brief  ETH Power Down structure definition
649   */
650 typedef struct
651 {
652   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
653 
654   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
655 
656   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
657 
658   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
659 
660 } ETH_PowerDownConfigTypeDef;
661 /**
662   *
663   */
664 
665 /**
666   * @}
667   */
668 
669 /* Exported constants --------------------------------------------------------*/
670 /** @defgroup ETH_Exported_Constants ETH Exported Constants
671   * @{
672   */
673 
674 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
675   * @{
676   */
677 
678 /*
679    DMA Tx Normal Descriptor Read Format
680   -----------------------------------------------------------------------------------------------
681   TDES0 |                         Buffer1 or Header Address  [31:0]                              |
682   -----------------------------------------------------------------------------------------------
683   TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
684   -----------------------------------------------------------------------------------------------
685   TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
686   -----------------------------------------------------------------------------------------------
687   TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
688   -----------------------------------------------------------------------------------------------
689 */
690 
691 /**
692   * @brief  Bit definition of TDES0 RF register
693   */
694 #define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
695 
696 /**
697   * @brief  Bit definition of TDES1 RF register
698   */
699 #define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
700 
701 /**
702   * @brief  Bit definition of TDES2 RF register
703   */
704 #define ETH_DMATXNDESCRF_IOC          0x80000000U  /*!< Interrupt on Completion */
705 #define ETH_DMATXNDESCRF_TTSE         0x40000000U  /*!< Transmit Timestamp Enable */
706 #define ETH_DMATXNDESCRF_B2L          0x3FFF0000U  /*!< Buffer 2 Length */
707 #define ETH_DMATXNDESCRF_VTIR         0x0000C000U  /*!< VLAN Tag Insertion or Replacement mask */
708 #define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U  /*!< Do not add a VLAN tag. */
709 #define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U  /*!< Remove the VLAN tag from the packets before transmission. */
710 #define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U  /*!< Insert a VLAN tag. */
711 #define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U  /*!< Replace the VLAN tag. */
712 #define ETH_DMATXNDESCRF_B1L          0x00003FFFU  /*!< Buffer 1 Length */
713 #define ETH_DMATXNDESCRF_HL           0x000003FFU  /*!< Header Length */
714 
715 /**
716   * @brief  Bit definition of TDES3 RF register
717   */
718 #define ETH_DMATXNDESCRF_OWN                                 0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
719 #define ETH_DMATXNDESCRF_CTXT                                0x40000000U  /*!< Context Type */
720 #define ETH_DMATXNDESCRF_FD                                  0x20000000U  /*!< First Descriptor */
721 #define ETH_DMATXNDESCRF_LD                                  0x10000000U  /*!< Last Descriptor */
722 #define ETH_DMATXNDESCRF_CPC                                 0x0C000000U  /*!< CRC Pad Control mask */
723 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U  /*!< CRC Pad Control: CRC and Pad Insertion */
724 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
725 #define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U  /*!< CRC Pad Control: Disable CRC Insertion */
726 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U  /*!< CRC Pad Control: CRC Replacement */
727 #define ETH_DMATXNDESCRF_SAIC                                0x03800000U  /*!< SA Insertion Control mask*/
728 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U  /*!< SA Insertion Control: Do not include the source address */
729 #define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U  /*!< SA Insertion Control: Include or insert the source address */
730 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U  /*!< SA Insertion Control: Replace the source address */
731 #define ETH_DMATXNDESCRF_THL                                 0x00780000U  /*!< TCP Header Length */
732 #define ETH_DMATXNDESCRF_TSE                                 0x00040000U  /*!< TCP segmentation enable */
733 #define ETH_DMATXNDESCRF_CIC                                 0x00030000U  /*!< Checksum Insertion Control: 4 cases */
734 #define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U  /*!< Do Nothing: Checksum Engine is disabled */
735 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U  /*!< Only IP header checksum calculation and insertion are enabled. */
736 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U  /*!< IP header checksum and payload checksum calculation and insertion are
737                                                                                         enabled, but pseudo header
738                                                                                         checksum is not
739                                                                                         calculated in hardware */
740 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U  /*!< IP Header checksum and payload checksum calculation and insertion are
741                                                                                         enabled, and pseudo header
742                                                                                         checksum is
743                                                                                         calculated in hardware. */
744 #define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU  /*!< TCP Payload Length */
745 #define ETH_DMATXNDESCRF_FL                                  0x00007FFFU  /*!< Transmit End of Ring */
746 
747 /*
748    DMA Tx Normal Descriptor Write Back Format
749   -----------------------------------------------------------------------------------------------
750   TDES0 |                         Timestamp Low                                                  |
751   -----------------------------------------------------------------------------------------------
752   TDES1 |                         Timestamp High                                                 |
753   -----------------------------------------------------------------------------------------------
754   TDES2 |                           Reserved[31:0]                                               |
755   -----------------------------------------------------------------------------------------------
756   TDES3 | OWN(31) |                          Status[30:0]                                        |
757   -----------------------------------------------------------------------------------------------
758 */
759 
760 /**
761   * @brief  Bit definition of TDES0 WBF register
762   */
763 #define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
764 
765 /**
766   * @brief  Bit definition of TDES1 WBF register
767   */
768 #define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
769 
770 /**
771   * @brief  Bit definition of TDES3 WBF register
772   */
773 #define ETH_DMATXNDESCWBF_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
774 #define ETH_DMATXNDESCWBF_CTXT                    0x40000000U  /*!< Context Type */
775 #define ETH_DMATXNDESCWBF_FD                      0x20000000U  /*!< First Descriptor */
776 #define ETH_DMATXNDESCWBF_LD                      0x10000000U  /*!< Last Descriptor */
777 #define ETH_DMATXNDESCWBF_TTSS                    0x00020000U  /*!< Tx Timestamp Status */
778 #define ETH_DMATXNDESCWBF_DP                      0x04000000U  /*!< Disable Padding */
779 #define ETH_DMATXNDESCWBF_TTSE                    0x02000000U  /*!< Transmit Timestamp Enable */
780 #define ETH_DMATXNDESCWBF_ES                      0x00008000U  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
781 #define ETH_DMATXNDESCWBF_JT                      0x00004000U  /*!< Jabber Timeout */
782 #define ETH_DMATXNDESCWBF_FF                      0x00002000U  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
783 #define ETH_DMATXNDESCWBF_PCE                     0x00001000U  /*!< Payload Checksum Error */
784 #define ETH_DMATXNDESCWBF_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
785 #define ETH_DMATXNDESCWBF_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
786 #define ETH_DMATXNDESCWBF_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
787 #define ETH_DMATXNDESCWBF_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
788 #define ETH_DMATXNDESCWBF_CC                      0x000000F0U  /*!< Collision Count */
789 #define ETH_DMATXNDESCWBF_ED                      0x00000008U  /*!< Excessive Deferral */
790 #define ETH_DMATXNDESCWBF_UF                      0x00000004U  /*!< Underflow Error: late data arrival from the memory */
791 #define ETH_DMATXNDESCWBF_DB                      0x00000002U  /*!< Deferred Bit */
792 #define ETH_DMATXNDESCWBF_IHE                     0x00000004U  /*!< IP Header Error */
793 
794 /*
795    DMA Tx Context Descriptor
796   -----------------------------------------------------------------------------------------------
797   TDES0 |                               Timestamp Low                                            |
798   -----------------------------------------------------------------------------------------------
799   TDES1 |                               Timestamp High                                           |
800   -----------------------------------------------------------------------------------------------
801   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
802   -----------------------------------------------------------------------------------------------
803   TDES3 | OWN(31) |                          Status[30:0]                                        |
804   -----------------------------------------------------------------------------------------------
805 */
806 
807 /**
808   * @brief  Bit definition of Tx context descriptor register 0
809   */
810 #define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
811 
812 /**
813   * @brief  Bit definition of Tx context descriptor register 1
814   */
815 #define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
816 
817 /**
818   * @brief  Bit definition of Tx context descriptor register 2
819   */
820 #define ETH_DMATXCDESC_IVT                     0xFFFF0000U  /*!< Inner VLAN Tag */
821 #define ETH_DMATXCDESC_MSS                     0x00003FFFU  /*!< Maximum Segment Size */
822 
823 /**
824   * @brief  Bit definition of Tx context descriptor register 3
825   */
826 #define ETH_DMATXCDESC_OWN                     0x80000000U     /*!< OWN bit: descriptor is owned by DMA engine */
827 #define ETH_DMATXCDESC_CTXT                    0x40000000U     /*!< Context Type */
828 #define ETH_DMATXCDESC_OSTC                    0x08000000U     /*!< One-Step Timestamp Correction Enable */
829 #define ETH_DMATXCDESC_TCMSSV                  0x04000000U     /*!< One-Step Timestamp Correction Input or MSS Valid */
830 #define ETH_DMATXCDESC_CDE                     0x00800000U     /*!< Context Descriptor Error */
831 #define ETH_DMATXCDESC_IVTIR                   0x000C0000U     /*!< Inner VLAN Tag Insert or Replace Mask */
832 #define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U     /*!< Do not add the inner VLAN tag. */
833 #define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U     /*!< Remove the inner VLAN tag from the packets before transmission. */
834 #define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U     /*!< Insert the inner VLAN tag. */
835 #define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U     /*!< Replace the inner VLAN tag. */
836 #define ETH_DMATXCDESC_IVLTV                   0x00020000U     /*!< Inner VLAN Tag Valid */
837 #define ETH_DMATXCDESC_VLTV                    0x00010000U     /*!< VLAN Tag Valid */
838 #define ETH_DMATXCDESC_VT                      0x0000FFFFU     /*!< VLAN Tag */
839 
840 /**
841   * @}
842   */
843 
844 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
845   * @{
846   */
847 
848 /*
849   DMA Rx Normal Descriptor read format
850   -----------------------------------------------------------------------------------------------------------
851   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
852   -----------------------------------------------------------------------------------------------------------
853   RDES1 |                                            Reserved                                               |
854   -----------------------------------------------------------------------------------------------------------
855   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
856   -----------------------------------------------------------------------------------------------------------
857   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
858   -----------------------------------------------------------------------------------------------------------
859 */
860 
861 /**
862   * @brief  Bit definition of Rx normal descriptor register 0 read format
863   */
864 #define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU  /*!< Header or Buffer 1 Address Pointer  */
865 
866 /**
867   * @brief  Bit definition of Rx normal descriptor register 2 read format
868   */
869 #define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU  /*!< Buffer 2 Address Pointer  */
870 
871 /**
872   * @brief  Bit definition of Rx normal descriptor register 3 read format
873   */
874 #define ETH_DMARXNDESCRF_OWN              0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
875 #define ETH_DMARXNDESCRF_IOC              0x40000000U  /*!< Interrupt Enabled on Completion  */
876 #define ETH_DMARXNDESCRF_BUF2V            0x02000000U  /*!< Buffer 2 Address Valid */
877 #define ETH_DMARXNDESCRF_BUF1V            0x01000000U  /*!< Buffer 1 Address Valid */
878 
879 /*
880   DMA Rx Normal Descriptor write back format
881   ---------------------------------------------------------------------------------------------------------------------
882   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
883   ---------------------------------------------------------------------------------------------------------------------
884   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
885   ---------------------------------------------------------------------------------------------------------------------
886   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
887   ---------------------------------------------------------------------------------------------------------------------
888   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
889   ---------------------------------------------------------------------------------------------------------------------
890 */
891 
892 /**
893   * @brief  Bit definition of Rx normal descriptor register 0 write back format
894   */
895 #define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U  /*!< Inner VLAN Tag  */
896 #define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU  /*!< Outer VLAN Tag  */
897 
898 /**
899   * @brief  Bit definition of Rx normal descriptor register 1 write back format
900   */
901 #define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
902 #define ETH_DMARXNDESCWBF_TD              0x00008000U  /*!< Timestamp Dropped  */
903 #define ETH_DMARXNDESCWBF_TSA             0x00004000U  /*!< Timestamp Available  */
904 #define ETH_DMARXNDESCWBF_PV              0x00002000U  /*!< PTP Version  */
905 #define ETH_DMARXNDESCWBF_PFT             0x00001000U  /*!< PTP Packet Type  */
906 #define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U  /*!< PTP Message Type: No PTP message received  */
907 #define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U  /*!< PTP Message Type: SYNC (all clock types)  */
908 #define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U  /*!< PTP Message Type: Follow_Up (all clock types)  */
909 #define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U  /*!< PTP Message Type: Delay_Req (all clock types)  */
910 #define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U  /*!< PTP Message Type: Delay_Resp (all clock types)  */
911 #define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
912 #define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
913 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
914 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U  /*!< PTP Message Type: Announce  */
915 #define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U  /*!< PTP Message Type: Management  */
916 #define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U  /*!< PTP Message Type: Signaling  */
917 #define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U  /*!< PTP Message Type: PTP packet with Reserved message type  */
918 #define ETH_DMARXNDESCWBF_IPCE            0x00000080U  /*!< IP Payload Error */
919 #define ETH_DMARXNDESCWBF_IPCB            0x00000040U  /*!< IP Checksum Bypassed */
920 #define ETH_DMARXNDESCWBF_IPV6            0x00000020U  /*!< IPv6 header Present */
921 #define ETH_DMARXNDESCWBF_IPV4            0x00000010U  /*!< IPv4 header Present */
922 #define ETH_DMARXNDESCWBF_IPHE            0x00000008U  /*!< IP Header Error */
923 #define ETH_DMARXNDESCWBF_PT              0x00000003U  /*!< Payload Type mask */
924 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U  /*!< Payload Type: Unknown type or IP/AV payload not processed */
925 #define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U  /*!< Payload Type: UDP */
926 #define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U  /*!< Payload Type: TCP  */
927 #define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U  /*!< Payload Type: ICMP */
928 
929 /**
930   * @brief  Bit definition of Rx normal descriptor register 2 write back format
931   */
932 #define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
933 #define ETH_DMARXNDESCWBF_L4FM            0x10000000U  /*!< Layer 4 Filter Match                  */
934 #define ETH_DMARXNDESCWBF_L3FM            0x08000000U  /*!< Layer 3 Filter Match                  */
935 #define ETH_DMARXNDESCWBF_MADRM           0x07F80000U  /*!< MAC Address Match or Hash Value       */
936 #define ETH_DMARXNDESCWBF_HF              0x00040000U  /*!< Hash Filter Status                    */
937 #define ETH_DMARXNDESCWBF_DAF             0x00020000U  /*!< Destination Address Filter Fail       */
938 #define ETH_DMARXNDESCWBF_SAF             0x00010000U  /*!< SA Address Filter Fail                */
939 #define ETH_DMARXNDESCWBF_VF              0x00008000U  /*!< VLAN Filter Status                    */
940 #define ETH_DMARXNDESCWBF_ARPNR           0x00000400U  /*!< ARP Reply Not Generated               */
941 
942 /**
943   * @brief  Bit definition of Rx normal descriptor register 3 write back format
944   */
945 #define ETH_DMARXNDESCWBF_OWN             0x80000000U  /*!< Own Bit */
946 #define ETH_DMARXNDESCWBF_CTXT            0x40000000U  /*!< Receive Context Descriptor */
947 #define ETH_DMARXNDESCWBF_FD              0x20000000U  /*!< First Descriptor */
948 #define ETH_DMARXNDESCWBF_LD              0x10000000U  /*!< Last Descriptor */
949 #define ETH_DMARXNDESCWBF_RS2V            0x08000000U  /*!< Receive Status RDES2 Valid */
950 #define ETH_DMARXNDESCWBF_RS1V            0x04000000U  /*!< Receive Status RDES1 Valid */
951 #define ETH_DMARXNDESCWBF_RS0V            0x02000000U  /*!< Receive Status RDES0 Valid */
952 #define ETH_DMARXNDESCWBF_CE              0x01000000U  /*!< CRC Error */
953 #define ETH_DMARXNDESCWBF_GP              0x00800000U  /*!< Giant Packet */
954 #define ETH_DMARXNDESCWBF_RWT             0x00400000U  /*!< Receive Watchdog Timeout */
955 #define ETH_DMARXNDESCWBF_OE              0x00200000U  /*!< Overflow Error */
956 #define ETH_DMARXNDESCWBF_RE              0x00100000U  /*!< Receive Error */
957 #define ETH_DMARXNDESCWBF_DE              0x00080000U  /*!< Dribble Bit Error */
958 #define ETH_DMARXNDESCWBF_LT              0x00070000U  /*!< Length/Type Field */
959 #define ETH_DMARXNDESCWBF_LT_LP           0x00000000U  /*!< The packet is a length packet */
960 #define ETH_DMARXNDESCWBF_LT_TP           0x00010000U  /*!< The packet is a type packet */
961 #define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U  /*!< The packet is a ARP Request packet type */
962 #define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U  /*!< The packet is a type packet with VLAN Tag */
963 #define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U  /*!< The packet is a type packet with Double VLAN Tag */
964 #define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U  /*!< The packet is a MAC Control packet type */
965 #define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U  /*!< The packet is a OAM packet type */
966 #define ETH_DMARXNDESCWBF_ES              0x00008000U  /*!< Error Summary */
967 #define ETH_DMARXNDESCWBF_PL              0x00007FFFU  /*!< Packet Length */
968 
969 /*
970   DMA Rx context Descriptor
971   ---------------------------------------------------------------------------------------------------------------------
972   RDES0 |                                     Timestamp Low[31:0]                                                     |
973   ---------------------------------------------------------------------------------------------------------------------
974   RDES1 |                                     Timestamp High[31:0]                                                    |
975   ---------------------------------------------------------------------------------------------------------------------
976   RDES2 |                                          Reserved                                                           |
977   ---------------------------------------------------------------------------------------------------------------------
978   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
979   ---------------------------------------------------------------------------------------------------------------------
980 */
981 
982 /**
983   * @brief  Bit definition of Rx context descriptor register 0
984   */
985 #define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU  /*!< Receive Packet Timestamp Low  */
986 
987 /**
988   * @brief  Bit definition of Rx context descriptor register 1
989   */
990 #define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU  /*!< Receive Packet Timestamp High  */
991 
992 /**
993   * @brief  Bit definition of Rx context descriptor register 3
994   */
995 #define ETH_DMARXCDESC_OWN                    0x80000000U  /*!< Own Bit  */
996 #define ETH_DMARXCDESC_CTXT                   0x40000000U  /*!< Receive Context Descriptor  */
997 
998 /**
999   * @}
1000   */
1001 
1002 /** @defgroup ETH_Frame_settings ETH frame settings
1003   * @{
1004   */
1005 #define ETH_MAX_PACKET_SIZE                   1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
1006 #define ETH_HEADER                            14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
1007 #define ETH_CRC                               4U    /*!< Ethernet CRC */
1008 #define ETH_VLAN_TAG                          4U    /*!< optional 802.1q VLAN Tag */
1009 #define ETH_MIN_PAYLOAD                       46U    /*!< Minimum Ethernet payload size */
1010 #define ETH_MAX_PAYLOAD                       1500U    /*!< Maximum Ethernet payload size */
1011 #define ETH_JUMBO_FRAME_PAYLOAD               9000U    /*!< Jumbo frame payload size */
1012 /**
1013   * @}
1014   */
1015 
1016 /** @defgroup ETH_Error_Code ETH Error Code
1017   * @{
1018   */
1019 #define HAL_ETH_ERROR_NONE                    0x00000000U   /*!< No error            */
1020 #define HAL_ETH_ERROR_PARAM                   0x00000001U   /*!< Busy error          */
1021 #define HAL_ETH_ERROR_BUSY                    0x00000002U   /*!< Parameter error     */
1022 #define HAL_ETH_ERROR_TIMEOUT                 0x00000004U   /*!< Timeout error       */
1023 #define HAL_ETH_ERROR_DMA                     0x00000008U   /*!< DMA transfer error  */
1024 #define HAL_ETH_ERROR_MAC                     0x00000010U   /*!< MAC transfer error  */
1025 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1026 #define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U    /*!< Invalid Callback error  */
1027 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1028 /**
1029   * @}
1030   */
1031 
1032 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
1033   * @{
1034   */
1035 #define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
1036 #define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
1037 #define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
1038 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
1039 #define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
1040 #define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
1041 /**
1042   * @}
1043   */
1044 
1045 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
1046   * @{
1047   */
1048 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
1049 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
1050 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
1051 /**
1052   * @}
1053   */
1054 
1055 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
1056   * @{
1057   */
1058 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
1059 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
1060 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
1061 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
1062 /**
1063   * @}
1064   */
1065 
1066 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
1067   * @{
1068   */
1069 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
1070 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
1071 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
1072 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
1073 /**
1074   * @}
1075   */
1076 
1077 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
1078   * @{
1079   */
1080 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
1081 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
1082 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
1083 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
1084 /**
1085   * @}
1086   */
1087 
1088 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
1089   * @{
1090   */
1091 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
1092 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
1093 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
1094 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
1095 /**
1096   * @}
1097   */
1098 
1099 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
1100   * @{
1101   */
1102 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
1103 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
1104 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
1105 /**
1106   * @}
1107   */
1108 
1109 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
1110   * @{
1111   */
1112 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
1113 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
1114 /**
1115   * @}
1116   */
1117 
1118 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
1119   * @{
1120   */
1121 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
1122 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
1123 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
1124 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
1125 /**
1126   * @}
1127   */
1128 
1129 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
1130   * @{
1131   */
1132 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
1133 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
1134 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
1135 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
1136 /**
1137   * @}
1138   */
1139 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1140   * @{
1141   */
1142 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
1143 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1144 /**
1145   * @}
1146   */
1147 
1148 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1149   * @{
1150   */
1151 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
1152 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1153 /**
1154   * @}
1155   */
1156 
1157 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1158   * @{
1159   */
1160 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
1161 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
1162 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
1163 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
1164 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
1165 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
1166 /**
1167   * @}
1168   */
1169 
1170 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1171   * @{
1172   */
1173 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
1174 #define ETH_DMAARBITRATION_RX1_TX1   0x00000000U
1175 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
1176 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
1177 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
1178 #define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
1179 #define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
1180 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
1181 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
1182 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1183 #define ETH_DMAARBITRATION_TX1_RX1   0x00000000U
1184 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1185 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1186 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1187 #define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1188 #define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1189 #define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1190 #define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1191 /**
1192   * @}
1193   */
1194 
1195 /** @defgroup ETH_Burst_Mode ETH Burst Mode
1196   * @{
1197   */
1198 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
1199 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
1200 #define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
1201 /**
1202   * @}
1203   */
1204 
1205 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1206   * @{
1207   */
1208 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
1209 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
1210 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
1211 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
1212 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
1213 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
1214 /**
1215   * @}
1216   */
1217 
1218 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1219   * @{
1220   */
1221 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
1222 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
1223 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
1224 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
1225 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
1226 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
1227 /**
1228   * @}
1229   */
1230 
1231 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1232   * @{
1233   */
1234 #define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
1235 #define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
1236 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
1237 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
1238 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
1239 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
1240 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
1241 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
1242 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
1243 #define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
1244 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
1245 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
1246 #define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
1247 /**
1248   * @}
1249   */
1250 
1251 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1252   * @{
1253   */
1254 #define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U
1255 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG          0x00380000U
1256 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         0x00300000U
1257 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        0x00280000U
1258 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG       0x00200000U
1259 #define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U
1260 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG          0x00070000U
1261 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         0x00060000U
1262 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        0x00050000U
1263 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG       0x00040000U
1264 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG          ETH_DMACSR_CDE
1265 #define ETH_DMA_FATAL_BUS_ERROR_FLAG             ETH_DMACSR_FBE
1266 #define ETH_DMA_EARLY_TX_IT_FLAG                 ETH_DMACSR_ERI
1267 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG         ETH_DMACSR_RWT
1268 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG          ETH_DMACSR_RPS
1269 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG       ETH_DMACSR_RBU
1270 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG          ETH_DMACSR_TPS
1271 /**
1272   * @}
1273   */
1274 
1275 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1276   * @{
1277   */
1278 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
1279 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
1280 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
1281 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
1282 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
1283 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
1284 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
1285 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
1286 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
1287 /**
1288   * @}
1289   */
1290 
1291 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1292   * @{
1293   */
1294 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
1295 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
1296 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
1297 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
1298 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
1299 /**
1300   * @}
1301   */
1302 
1303 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
1304   * @{
1305   */
1306 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
1307 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
1308 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
1309 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
1310 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
1311 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
1312 /**
1313   * @}
1314   */
1315 
1316 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1317   * @{
1318   */
1319 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
1320 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
1321 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
1322 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
1323 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
1324 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
1325 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
1326 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
1327 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
1328 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
1329 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
1330 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
1331 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
1332 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
1333 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
1334 /**
1335   * @}
1336   */
1337 
1338 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1339   * @{
1340   */
1341 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
1342 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
1343 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
1344 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
1345 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
1346 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
1347 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
1348 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
1349 /**
1350   * @}
1351   */
1352 
1353 /** @defgroup ETH_Speed  ETH Speed
1354   * @{
1355   */
1356 #define ETH_SPEED_10M        0x00000000U
1357 #define ETH_SPEED_100M       ETH_MACCR_FES
1358 /**
1359   * @}
1360   */
1361 
1362 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1363   * @{
1364   */
1365 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
1366 #define ETH_HALFDUPLEX_MODE       0x00000000U
1367 /**
1368   * @}
1369   */
1370 
1371 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1372   * @{
1373   */
1374 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
1375 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
1376 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
1377 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
1378 /**
1379   * @}
1380   */
1381 
1382 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1383   * @{
1384   */
1385 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
1386 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
1387 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
1388 /**
1389   * @}
1390   */
1391 
1392 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1393   * @{
1394   */
1395 #define ETH_SOURCEADDRESS_DISABLE           0x00000000U
1396 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
1397 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
1398 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
1399 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
1400 /**
1401   * @}
1402   */
1403 
1404 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1405   * @{
1406   */
1407 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
1408 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1409 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
1410 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1411 /**
1412   * @}
1413   */
1414 
1415 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1416   * @{
1417   */
1418 #define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U
1419 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
1420 /**
1421   * @}
1422   */
1423 
1424 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1425   * @{
1426   */
1427 #define ETH_MAC_ADDRESS0     0x00000000U
1428 #define ETH_MAC_ADDRESS1     0x00000008U
1429 #define ETH_MAC_ADDRESS2     0x00000010U
1430 #define ETH_MAC_ADDRESS3     0x00000018U
1431 /**
1432   * @}
1433   */
1434 
1435 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1436   * @{
1437   */
1438 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
1439 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
1440 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
1441 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
1442 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
1443 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
1444 /**
1445   * @}
1446   */
1447 
1448 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1449   * @{
1450   */
1451 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
1452 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
1453 /**
1454   * @}
1455   */
1456 
1457 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1458   * @{
1459   */
1460 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
1461 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
1462 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
1463 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
1464 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
1465 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
1466 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
1467 /**
1468   * @}
1469   */
1470 
1471 /** @defgroup ETH_State_Codes ETH States
1472   * @{
1473   */
1474 #define HAL_ETH_STATE_RESET                0x00000000U    /*!< Peripheral not yet Initialized or disabled */
1475 #define HAL_ETH_STATE_READY                0x00000010U    /*!< Peripheral Communication started           */
1476 #define HAL_ETH_STATE_BUSY                 0x00000023U    /*!< an internal process is ongoing             */
1477 #define HAL_ETH_STATE_STARTED              0x00000023U    /*!< an internal process is started             */
1478 #define HAL_ETH_STATE_ERROR                0x000000E0U    /*!< Error State                                */
1479 /**
1480   * @}
1481   */
1482 
1483 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
1484   * @{
1485   */
1486 #define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
1487 #define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
1488 /**
1489   * @}
1490   */
1491 
1492 /**
1493   * @}
1494   */
1495 
1496 /* Exported macro ------------------------------------------------------------*/
1497 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1498   * @{
1499   */
1500 
1501 /** @brief Reset ETH handle state
1502   * @param  __HANDLE__: specifies the ETH handle.
1503   * @retval None
1504   */
1505 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1506 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1507                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1508                                                       (__HANDLE__)->MspInitCallback = NULL;             \
1509                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
1510                                                     } while(0)
1511 #else
1512 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1513                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1514                                                     } while(0)
1515 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1516 
1517 /**
1518   * @brief  Enables the specified ETHERNET DMA interrupts.
1519   * @param  __HANDLE__   : ETH Handle
1520   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1521   *   enabled @ref ETH_DMA_Interrupts
1522   * @retval None
1523   */
1524 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1525 
1526 /**
1527   * @brief  Disables the specified ETHERNET DMA interrupts.
1528   * @param  __HANDLE__   : ETH Handle
1529   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1530   *   disabled. @ref ETH_DMA_Interrupts
1531   * @retval None
1532   */
1533 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1534 
1535 /**
1536   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
1537   * @param  __HANDLE__   : ETH Handle
1538   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1539   * @retval The ETH DMA IT Source enabled or disabled
1540   */
1541 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1542   (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
1543 
1544 /**
1545   * @brief  Gets the ETHERNET DMA IT pending bit.
1546   * @param  __HANDLE__   : ETH Handle
1547   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1548   * @retval The state of ETH DMA IT (SET or RESET)
1549   */
1550 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \
1551   (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
1552 
1553 /**
1554   * @brief  Clears the ETHERNET DMA IT pending bit.
1555   * @param  __HANDLE__   : ETH Handle
1556   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1557   * @retval None
1558   */
1559 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1560 
1561 /**
1562   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
1563   * @param  __HANDLE__: ETH Handle
1564   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1565   * @retval The state of ETH DMA FLAG (SET or RESET).
1566   */
1567 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1568 
1569 /**
1570   * @brief  Clears the specified ETHERNET DMA flag.
1571   * @param  __HANDLE__: ETH Handle
1572   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1573   * @retval The state of ETH DMA FLAG (SET or RESET).
1574   */
1575 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1576 
1577 /**
1578   * @brief  Enables the specified ETHERNET MAC interrupts.
1579   * @param  __HANDLE__   : ETH Handle
1580   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1581   *   enabled @ref ETH_MAC_Interrupts
1582   * @retval None
1583   */
1584 
1585 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1586 
1587 /**
1588   * @brief  Disables the specified ETHERNET MAC interrupts.
1589   * @param  __HANDLE__   : ETH Handle
1590   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1591   *   enabled @ref ETH_MAC_Interrupts
1592   * @retval None
1593   */
1594 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1595 
1596 /**
1597   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
1598   * @param  __HANDLE__: ETH Handle
1599   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1600   * @retval The state of ETH MAC IT (SET or RESET).
1601   */
1602 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\
1603                                                                               ( __INTERRUPT__)) == ( __INTERRUPT__))
1604 
1605 /*!< External interrupt line 46 Connected to the ETH wakeup EXTI Line */
1606 #define ETH_WAKEUP_EXTI_LINE  0x00004000U  /* !<  46 - 32 = 14 */
1607 
1608 /**
1609   * @brief Enable the ETH WAKEUP Exti Line.
1610   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1611   *   @arg ETH_WAKEUP_EXTI_LINE
1612   * @retval None.
1613   */
1614 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR2 |= (__EXTI_LINE__))
1615 
1616 /**
1617   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1618   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1619   *   @arg ETH_WAKEUP_EXTI_LINE
1620   * @retval EXTI ETH WAKEUP Line Status.
1621   */
1622 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->PR2 & (__EXTI_LINE__))
1623 
1624 /**
1625   * @brief Clear the ETH WAKEUP Exti flag.
1626   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1627   *   @arg ETH_WAKEUP_EXTI_LINE
1628   * @retval None.
1629   */
1630 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (EXTI->PR2 = (__EXTI_LINE__))
1631 
1632 /**
1633   * @brief  enable rising edge interrupt on selected EXTI line.
1634   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1635   *  @arg ETH_WAKEUP_EXTI_LINE
1636   * @retval None
1637   */
1638 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
1639   (EXTI->RTSR2 |= (__EXTI_LINE__))
1640 
1641 /**
1642   * @brief  enable falling edge interrupt on selected EXTI line.
1643   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1644   *  @arg ETH_WAKEUP_EXTI_LINE
1645   * @retval None
1646   */
1647 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
1648   (EXTI->FTSR2 |= (__EXTI_LINE__))
1649 
1650 /**
1651   * @brief  enable falling edge interrupt on selected EXTI line.
1652   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1653   *  @arg ETH_WAKEUP_EXTI_LINE
1654   * @retval None
1655   */
1656 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
1657   (EXTI->FTSR2 |= (__EXTI_LINE__))
1658 
1659 /**
1660   * @brief  Generates a Software interrupt on selected EXTI line.
1661   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1662   *  @arg ETH_WAKEUP_EXTI_LINE
1663   * @retval None
1664   */
1665 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
1666 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
1667                                                            (__FLAG__)) == (__FLAG__)) ? SET : RESET)
1668 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
1669 
1670 /**
1671   * @}
1672   */
1673 
1674 /* Include ETH HAL Extension module */
1675 #include "stm32h7rsxx_hal_eth_ex.h"
1676 
1677 /* Exported functions --------------------------------------------------------*/
1678 
1679 /** @addtogroup ETH_Exported_Functions
1680   * @{
1681   */
1682 
1683 /** @addtogroup ETH_Exported_Functions_Group1
1684   * @{
1685   */
1686 /* Initialization and de initialization functions  **********************************/
1687 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1688 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1689 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1690 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1691 
1692 /* Callbacks Register/UnRegister functions  ***********************************/
1693 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1694 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
1695                                            pETH_CallbackTypeDef pCallback);
1696 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1697 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1698 
1699 /**
1700   * @}
1701   */
1702 
1703 /** @addtogroup ETH_Exported_Functions_Group2
1704   * @{
1705   */
1706 /* IO operation functions *******************************************************/
1707 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1708 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1709 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1710 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1711 
1712 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
1713 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
1714                                                      pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
1715 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
1716 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
1717 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
1718 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
1719 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
1720 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
1721 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
1722 
1723 #ifdef HAL_ETH_USE_PTP
1724 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
1725 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
1726 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
1727 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
1728 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
1729                                             ETH_TimeTypeDef *timeoffset);
1730 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
1731 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
1732 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
1733 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
1734 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
1735 #endif /* HAL_ETH_USE_PTP */
1736 
1737 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
1738 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
1739 
1740 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
1741                                            uint32_t RegValue);
1742 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
1743                                           uint32_t *pRegValue);
1744 
1745 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1746 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1747 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1748 void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
1749 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1750 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1751 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1752 void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
1753 void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
1754 void              HAL_ETH_TxFreeCallback(uint32_t *buff);
1755 void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
1756 /**
1757   * @}
1758   */
1759 
1760 /** @addtogroup ETH_Exported_Functions_Group3
1761   * @{
1762   */
1763 /* Peripheral Control functions  **********************************************/
1764 /* MAC & DMA Configuration APIs  **********************************************/
1765 HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1766 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1767 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1768 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1769 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1770 
1771 /* MAC VLAN Processing APIs    ************************************************/
1772 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
1773                                               uint32_t VLANIdentifier);
1774 
1775 /* MAC L2 Packet Filtering APIs  **********************************************/
1776 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1777 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
1778 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1779 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
1780                                                 const uint8_t *pMACAddr);
1781 
1782 /* MAC Power Down APIs    *****************************************************/
1783 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
1784                                              const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1785 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1786 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1787 
1788 /**
1789   * @}
1790   */
1791 
1792 /** @addtogroup ETH_Exported_Functions_Group4
1793   * @{
1794   */
1795 /* Peripheral State functions  **************************************************/
1796 HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
1797 uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
1798 uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
1799 uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
1800 uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
1801 /**
1802   * @}
1803   */
1804 
1805 /**
1806   * @}
1807   */
1808 
1809 /**
1810   * @}
1811   */
1812 
1813 /**
1814   * @}
1815   */
1816 
1817 #endif /* ETH */
1818 
1819 #ifdef __cplusplus
1820 }
1821 #endif
1822 
1823 #endif /* STM32H7RSxx_HAL_ETH_H */
1824