1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_ETH_H 21 #define STM32F7xx_HAL_ETH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 #if defined(ETH) 31 32 /** @addtogroup STM32F7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup ETH 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 #ifndef ETH_TX_DESC_CNT 42 #define ETH_TX_DESC_CNT 4U 43 #endif /* ETH_TX_DESC_CNT */ 44 45 #ifndef ETH_RX_DESC_CNT 46 #define ETH_RX_DESC_CNT 4U 47 #endif /* ETH_RX_DESC_CNT */ 48 49 50 /*********************** Descriptors struct def section ************************/ 51 /** @defgroup ETH_Exported_Types ETH Exported Types 52 * @{ 53 */ 54 55 /** 56 * @brief ETH DMA Descriptor structure definition 57 */ 58 typedef struct 59 { 60 __IO uint32_t DESC0; 61 __IO uint32_t DESC1; 62 __IO uint32_t DESC2; 63 __IO uint32_t DESC3; 64 __IO uint32_t DESC4; 65 __IO uint32_t DESC5; 66 __IO uint32_t DESC6; 67 __IO uint32_t DESC7; 68 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 69 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 70 } ETH_DMADescTypeDef; 71 /** 72 * 73 */ 74 75 /** 76 * @brief ETH Buffers List structure definition 77 */ 78 typedef struct __ETH_BufferTypeDef 79 { 80 uint8_t *buffer; /*<! buffer address */ 81 82 uint32_t len; /*<! buffer length */ 83 84 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */ 85 } ETH_BufferTypeDef; 86 /** 87 * 88 */ 89 90 /** 91 * @brief DMA Transmit Descriptors Wrapper structure definition 92 */ 93 typedef struct 94 { 95 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */ 96 97 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 98 99 uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */ 100 101 uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */ 102 103 uint32_t BuffersInUse; /*<! Buffers in Use */ 104 105 uint32_t releaseIndex; /*<! Release index */ 106 } ETH_TxDescListTypeDef; 107 /** 108 * 109 */ 110 111 /** 112 * @brief Transmit Packet Configuration structure definition 113 */ 114 typedef struct 115 { 116 uint32_t Attributes; /*!< Tx packet HW features capabilities. 117 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 118 119 uint32_t Length; /*!< Total packet length */ 120 121 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */ 122 123 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 124 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 125 126 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 127 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 128 129 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 130 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 131 132 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 133 This parameter can be a value from 0x0 to 0x3FFF */ 134 135 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 136 This parameter can be a value from 0x0 to 0x3FFFF */ 137 138 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 139 This parameter can be a value from 0x5 to 0xF */ 140 141 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 142 This parameter can be a value from 0x0 to 0xFFFF*/ 143 144 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 145 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 146 147 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 148 This parameter can be a value from 0x0 to 0x3FFFF */ 149 150 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 151 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 152 153 void *pData; /*!< Specifies Application packet pointer to save */ 154 155 } ETH_TxPacketConfigTypeDef; 156 /** 157 * 158 */ 159 160 /** 161 * @brief ETH Timestamp structure definition 162 */ 163 typedef struct 164 { 165 uint32_t TimeStampLow; 166 uint32_t TimeStampHigh; 167 168 } ETH_TimeStampTypeDef; 169 /** 170 * 171 */ 172 173 #ifdef HAL_ETH_USE_PTP 174 /** 175 * @brief ETH Timeupdate structure definition 176 */ 177 typedef struct 178 { 179 uint32_t Seconds; 180 uint32_t NanoSeconds; 181 } ETH_TimeTypeDef; 182 /** 183 * 184 */ 185 #endif /* HAL_ETH_USE_PTP */ 186 187 /** 188 * @brief DMA Receive Descriptors Wrapper structure definition 189 */ 190 typedef struct 191 { 192 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */ 193 194 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 195 If 0, DMA will not generate the Rx complete interrupt. */ 196 197 uint32_t RxDescIdx; /*<! Current Rx descriptor. */ 198 199 uint32_t RxDescCnt; /*<! Number of descriptors . */ 200 201 uint32_t RxDataLength; /*<! Received Data Length. */ 202 203 uint32_t RxBuildDescIdx; /*<! Current Rx Descriptor for building descriptors. */ 204 205 uint32_t RxBuildDescCnt; /*<! Number of Rx Descriptors awaiting building. */ 206 207 uint32_t pRxLastRxDesc; /*<! Last received descriptor. */ 208 209 ETH_TimeStampTypeDef TimeStamp; /*<! Time Stamp Low value for receive. */ 210 211 void *pRxStart; /*<! Pointer to the first buff. */ 212 213 void *pRxEnd; /*<! Pointer to the last buff. */ 214 215 } ETH_RxDescListTypeDef; 216 /** 217 * 218 */ 219 220 /** 221 * @brief ETH MAC Configuration Structure definition 222 */ 223 typedef struct 224 { 225 uint32_t 226 SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 227 This parameter can be a value of @ref ETH_Source_Addr_Control */ 228 229 FunctionalState 230 ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 231 232 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 233 This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 234 235 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 236 237 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 238 239 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 240 241 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 242 243 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/ 244 245 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path.*/ 246 247 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 248 When enabled, the MAC allows jumbo packets of 9,018 bytes 249 without reporting a giant packet error */ 250 251 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 252 This parameter can be a value of @ref ETH_Speed */ 253 254 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 255 This parameter can be a value of @ref ETH_Duplex_Mode */ 256 257 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 258 259 FunctionalState 260 CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 261 262 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 263 264 FunctionalState 265 CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 266 267 FunctionalState 268 RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 269 270 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 271 This parameter can be a value of @ref ETH_Back_Off_Limit */ 272 273 FunctionalState 274 DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 275 276 uint32_t 277 PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 278 This parameter can be a value of @ref ETH_Preamble_Length */ 279 280 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 281 282 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 283 284 uint32_t 285 GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 286 greater than the value programmed in this field in units of bytes 287 This parameter must be a number between 288 Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */ 289 290 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 291 292 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 293 This parameter can be a value from 0x0 to 0xFF */ 294 295 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 296 297 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 298 This parameter can be a value of @ref ETH_Watchdog_Timeout */ 299 300 uint32_t 301 PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 302 This parameter must be a number between 303 Min_Data = 0x0 and Max_Data = 0xFFFF.*/ 304 305 FunctionalState 306 ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 307 308 uint32_t 309 PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 310 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 311 312 FunctionalState 313 TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 314 or the MAC back pressure operation in Half Duplex mode */ 315 316 FunctionalState 317 UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 318 319 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 320 and disables its transmitter for a specified (Pause) time */ 321 322 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 323 This parameter can be a value of @ref ETH_Transmit_Mode */ 324 325 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 326 This parameter can be a value of @ref ETH_Receive_Mode */ 327 328 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 329 330 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 331 332 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 333 } ETH_MACConfigTypeDef; 334 /** 335 * 336 */ 337 338 /** 339 * @brief ETH DMA Configuration Structure definition 340 */ 341 typedef struct 342 { 343 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 344 This parameter can be a value of @ref ETH_DMA_Arbitration */ 345 346 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 347 burst transfers on Read and Write channels */ 348 349 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 350 This parameter can be a value of @ref ETH_Burst_Mode */ 351 FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ 352 353 FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ 354 355 FunctionalState TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode */ 356 357 358 uint32_t 359 TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 360 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 361 362 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 363 This parameter can be a value of 364 @ref ETH_Transmit_Threshold_Control */ 365 366 uint32_t 367 RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 368 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 369 370 FunctionalState ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames */ 371 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 372 373 FunctionalState 374 ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 375 and length less than 64 bytes) 376 including pad-bytes and CRC) */ 377 378 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 379 This parameter can be a value of 380 @ref ETH_Receive_Threshold_Control */ 381 382 FunctionalState 383 SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 384 frame of Transmit data even before obtaining 385 the status for the first frame */ 386 387 FunctionalState EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format */ 388 389 uint32_t 390 DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 391 This parameter must be a number between 392 Min_Data = 0 and Max_Data = 32 */ 393 } ETH_DMAConfigTypeDef; 394 /** 395 * 396 */ 397 398 /** 399 * @brief HAL ETH Media Interfaces enum definition 400 */ 401 typedef enum 402 { 403 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 404 HAL_ETH_RMII_MODE = SYSCFG_PMC_MII_RMII_SEL /*!< Reduced Media Independent Interface */ 405 } ETH_MediaInterfaceTypeDef; 406 /** 407 * 408 */ 409 410 #ifdef HAL_ETH_USE_PTP 411 /** 412 * @brief HAL ETH PTP Update type enum definition 413 */ 414 typedef enum 415 { 416 HAL_ETH_PTP_POSITIVE_UPDATE = 0x00000000U, /*!< PTP positive time update */ 417 HAL_ETH_PTP_NEGATIVE_UPDATE = 0x00000001U /*!< PTP negative time update */ 418 } ETH_PtpUpdateTypeDef; 419 /** 420 * 421 */ 422 #endif /* HAL_ETH_USE_PTP */ 423 424 /** 425 * @brief ETH Init Structure definition 426 */ 427 typedef struct 428 { 429 uint8_t 430 *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 431 432 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 433 434 ETH_DMADescTypeDef 435 *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 436 437 ETH_DMADescTypeDef 438 *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 439 440 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 441 442 } ETH_InitTypeDef; 443 /** 444 * 445 */ 446 447 #ifdef HAL_ETH_USE_PTP 448 /** 449 * @brief ETH PTP Init Structure definition 450 */ 451 typedef struct 452 { 453 uint32_t Timestamp; /*!< Enable Timestamp */ 454 uint32_t TimestampUpdateMode; /*!< Fine or Coarse Timestamp Update */ 455 uint32_t TimestampInitialize; /*!< Initialize Timestamp */ 456 uint32_t TimestampUpdate; /*!< Timestamp Update */ 457 uint32_t TimestampAddendUpdate; /*!< Timestamp Addend Update */ 458 uint32_t TimestampAll; /*!< Enable Timestamp for All Packets */ 459 uint32_t TimestampRolloverMode; /*!< Timestamp Digital or Binary Rollover Control */ 460 uint32_t TimestampV2; /*!< Enable PTP Packet Processing for Version 2 Format */ 461 uint32_t TimestampEthernet; /*!< Enable Processing of PTP over Ethernet Packets */ 462 uint32_t TimestampIPv6; /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */ 463 uint32_t TimestampIPv4; /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */ 464 uint32_t TimestampEvent; /*!< Enable Timestamp Snapshot for Event Messages */ 465 uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */ 466 uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */ 467 uint32_t TimestampClockType; /*!< Time stamp clock node type */ 468 uint32_t TimestampAddend; /*!< Timestamp addend value */ 469 uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */ 470 471 } ETH_PTP_ConfigTypeDef; 472 /** 473 * 474 */ 475 #endif /* HAL_ETH_USE_PTP */ 476 477 /** 478 * @brief HAL State structures definition 479 */ 480 typedef uint32_t HAL_ETH_StateTypeDef; 481 /** 482 * 483 */ 484 485 /** 486 * @brief HAL ETH Rx Get Buffer Function definition 487 */ 488 typedef void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer); /*!< pointer to an ETH Rx Get Buffer Function */ 489 /** 490 * 491 */ 492 493 /** 494 * @brief HAL ETH Rx Set App Data Function definition 495 */ 496 typedef void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff, 497 uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */ 498 /** 499 * 500 */ 501 502 /** 503 * @brief HAL ETH Tx Free Function definition 504 */ 505 typedef void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer); /*!< pointer to an ETH Tx Free function */ 506 /** 507 * 508 */ 509 510 /** 511 * @brief HAL ETH Tx Free Function definition 512 */ 513 typedef void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer, 514 ETH_TimeStampTypeDef *timestamp); /*!< pointer to an ETH Tx Free function */ 515 /** 516 * 517 */ 518 519 /** 520 * @brief ETH Handle Structure definition 521 */ 522 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 523 typedef struct __ETH_HandleTypeDef 524 #else 525 typedef struct 526 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 527 { 528 ETH_TypeDef *Instance; /*!< Register base address */ 529 530 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 531 532 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 533 addresses and current descriptor index */ 534 535 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 536 addresses and current descriptor index */ 537 538 #ifdef HAL_ETH_USE_PTP 539 ETH_TimeStampTypeDef TxTimestamp; /*!< Tx Timestamp */ 540 #endif /* HAL_ETH_USE_PTP */ 541 542 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 543 and also related to Tx operations. This parameter can 544 be a value of @ref ETH_State_Codes */ 545 546 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 547 This parameter can be a value of @ref ETH_Error_Code.*/ 548 549 __IO uint32_t 550 DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 551 This parameter can be a combination of 552 @ref ETH_DMA_Status_Flags */ 553 554 __IO uint32_t 555 MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 556 This parameter can be a combination of 557 @ref ETH_MAC_Rx_Tx_Status */ 558 559 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 560 This parameter can be a value of 561 @ref ETH_MAC_Wake_Up_Event */ 562 563 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 564 This parameter can be a value of @ref ETHEx_LPI_Event */ 565 566 __IO uint32_t IsPtpConfigured; /*!< Holds the PTP configuration status. 567 This parameter can be a value of 568 @ref ETH_PTP_Config_Status */ 569 570 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 571 572 void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ 573 void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ 574 void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Error Callback */ 575 void (* PMTCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Power Management Callback */ 576 void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Wake UP Callback */ 577 578 void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ 579 void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ 580 581 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 582 583 pETH_rxAllocateCallbackTypeDef rxAllocateCallback; /*!< ETH Rx Get Buffer Function */ 584 pETH_rxLinkCallbackTypeDef rxLinkCallback; /*!< ETH Rx Set App Data Function */ 585 pETH_txFreeCallbackTypeDef txFreeCallback; /*!< ETH Tx Free Function */ 586 pETH_txPtpCallbackTypeDef txPtpCallback; /*!< ETH Tx Handle Ptp Function */ 587 588 } ETH_HandleTypeDef; 589 /** 590 * 591 */ 592 593 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 594 /** 595 * @brief HAL ETH Callback ID enumeration definition 596 */ 597 typedef enum 598 { 599 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 600 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 601 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 602 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 603 HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */ 604 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 605 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 606 607 } HAL_ETH_CallbackIDTypeDef; 608 609 /** 610 * @brief HAL ETH Callback pointer definition 611 */ 612 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ 613 614 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 615 616 /** 617 * @brief ETH MAC filter structure definition 618 */ 619 typedef struct 620 { 621 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 622 623 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 624 625 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 626 627 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 628 629 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 630 631 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 632 633 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 634 635 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 636 637 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 638 639 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 640 641 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 642 This parameter can be a value of @ref ETH_Control_Packets_Filter */ 643 } ETH_MACFilterConfigTypeDef; 644 /** 645 * 646 */ 647 648 /** 649 * @brief ETH Power Down structure definition 650 */ 651 typedef struct 652 { 653 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 654 655 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 656 657 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 658 659 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 660 661 } ETH_PowerDownConfigTypeDef; 662 /** 663 * 664 */ 665 666 /** 667 * @} 668 */ 669 670 /* Exported constants --------------------------------------------------------*/ 671 /** @defgroup ETH_Exported_Constants ETH Exported Constants 672 * @{ 673 */ 674 675 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 676 * @{ 677 */ 678 679 /* 680 DMA Tx Normal Descriptor Read Format 681 ----------------------------------------------------------------------------------------------- 682 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 683 ----------------------------------------------------------------------------------------------- 684 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 685 ----------------------------------------------------------------------------------------------- 686 TDES2 | Buffer1 Address [31:0] | 687 ----------------------------------------------------------------------------------------------- 688 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 689 ----------------------------------------------------------------------------------------------- 690 */ 691 692 /** 693 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 694 */ 695 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 696 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 697 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 698 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 699 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 700 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 701 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 702 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 703 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 704 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 705 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 706 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 707 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 708 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 709 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 710 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 711 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 712 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 713 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 714 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 715 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 716 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 717 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 718 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 719 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 720 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 721 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 722 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 723 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 724 725 /** 726 * @brief Bit definition of TDES1 register 727 */ 728 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 729 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 730 731 /** 732 * @brief Bit definition of TDES2 register 733 */ 734 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 735 736 /** 737 * @brief Bit definition of TDES3 register 738 */ 739 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 740 741 /*--------------------------------------------------------------------------------------------- 742 TDES6 | Transmit Time Stamp Low [31:0] | 743 ----------------------------------------------------------------------------------------------- 744 TDES7 | Transmit Time Stamp High [31:0] | 745 ----------------------------------------------------------------------------------------------*/ 746 747 /* Bit definition of TDES6 register */ 748 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 749 750 /* Bit definition of TDES7 register */ 751 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 752 753 /** 754 * @} 755 */ 756 757 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 758 * @{ 759 */ 760 761 /* 762 DMA Rx Normal Descriptor read format 763 -------------------------------------------------------------------------------------------------------------------- 764 RDES0 | OWN(31) | Status [30:0] | 765 --------------------------------------------------------------------------------------------------------------------- 766 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 767 --------------------------------------------------------------------------------------------------------------------- 768 RDES2 | Buffer1 Address [31:0] | 769 --------------------------------------------------------------------------------------------------------------------- 770 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 771 --------------------------------------------------------------------------------------------------------------------- 772 */ 773 774 /** 775 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 776 */ 777 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 778 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 779 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 780 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 781 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 782 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 783 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 784 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 785 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 786 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 787 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 788 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 789 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 790 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 791 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 792 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 793 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 794 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 795 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 796 797 /** 798 * @brief Bit definition of RDES1 register 799 */ 800 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 801 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 802 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 803 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 804 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 805 806 /** 807 * @brief Bit definition of RDES2 register 808 */ 809 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 810 811 /** 812 * @brief Bit definition of RDES3 register 813 */ 814 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 815 816 /*--------------------------------------------------------------------------------------------------------------------- 817 RDES4 | Reserved[31:15] | Extended Status [14:0] | 818 --------------------------------------------------------------------------------------------------------------------- 819 RDES5 | Reserved[31:0] | 820 --------------------------------------------------------------------------------------------------------------------- 821 RDES6 | Receive Time Stamp Low [31:0] | 822 --------------------------------------------------------------------------------------------------------------------- 823 RDES7 | Receive Time Stamp High [31:0] | 824 --------------------------------------------------------------------------------------------------------------------*/ 825 826 /* Bit definition of RDES4 register */ 827 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 828 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 829 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 830 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message 831 (all clock types) */ 832 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message 833 (all clock types) */ 834 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message 835 (all clock types) */ 836 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message 837 (all clock types) */ 838 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message 839 (peer-to-peer transparent clock) 840 or Announce message (Ordinary 841 or Boundary clock) */ 842 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message 843 (peer-to-peer transparent clock) 844 or Management message (Ordinary 845 or Boundary clock) */ 846 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message 847 (peer-to-peer transparent clock) 848 or Signaling message (Ordinary 849 or Boundary clock) */ 850 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 851 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 852 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 853 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 854 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 855 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 856 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in 857 the IP datagram */ 858 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in 859 the IP datagram */ 860 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in 861 the IP datagram */ 862 863 /* Bit definition of RDES6 register */ 864 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 865 866 /* Bit definition of RDES7 register */ 867 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 868 869 /** 870 * @} 871 */ 872 873 /** @defgroup ETH_Frame_settings ETH frame settings 874 * @{ 875 */ 876 #define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 877 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 878 #define ETH_CRC 4U /*!< Ethernet CRC */ 879 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 880 #define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 881 #define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 882 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup ETH_Error_Code ETH Error Code 888 * @{ 889 */ 890 #define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ 891 #define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */ 892 #define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */ 893 #define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ 894 #define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */ 895 #define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */ 896 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 897 #define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ 898 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 899 /** 900 * @} 901 */ 902 903 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 904 * @{ 905 */ 906 #define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U 907 #define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U 908 #define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U 909 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U 910 #define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U 911 #define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U 912 /** 913 * @} 914 */ 915 916 917 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 918 * @{ 919 */ 920 #define ETH_CRC_PAD_DISABLE (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC) 921 #define ETH_CRC_PAD_INSERT 0x00000000U 922 #define ETH_CRC_INSERT ETH_DMATXDESC_DP 923 /** 924 * @} 925 */ 926 927 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 928 * @{ 929 */ 930 #define ETH_CHECKSUM_DISABLE ETH_DMATXDESC_CIC_BYPASS 931 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXDESC_CIC_IPV4HEADER 932 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 933 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 934 /** 935 * @} 936 */ 937 938 939 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 940 * @{ 941 */ 942 #define ETH_VLAN_FILTER_PASS ETH_DMARXDESC_VLAN 943 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXDESC_AFM 944 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXDESC_SAF 945 /** 946 * @} 947 */ 948 949 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 950 * @{ 951 */ 952 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXDESC_DBE 953 #define ETH_RECEIVE_ERROR ETH_DMARXDESC_RE 954 #define ETH_RECEIVE_OVERFLOW ETH_DMARXDESC_OE 955 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXDESC_RWT 956 #define ETH_GIANT_PACKET ETH_DMARXDESC_IPV4HC 957 #define ETH_CRC_ERROR ETH_DMARXDESC_CE 958 /** 959 * @} 960 */ 961 962 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 963 * @{ 964 */ 965 #define ETH_DMAARBITRATION_RX ETH_DMABMR_DA 966 #define ETH_DMAARBITRATION_RX1_TX1 0x00000000U 967 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMABMR_RTPR_2_1 968 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMABMR_RTPR_3_1 969 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMABMR_RTPR_4_1 970 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) 971 #define ETH_DMAARBITRATION_TX1_RX1 0x00000000U 972 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) 973 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) 974 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) 975 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1) 976 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1) 977 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1) 978 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1) 979 /** 980 * @} 981 */ 982 983 /** @defgroup ETH_Burst_Mode ETH Burst Mode 984 * @{ 985 */ 986 #define ETH_BURSTLENGTH_FIXED ETH_DMABMR_FB 987 #define ETH_BURSTLENGTH_MIXED ETH_DMABMR_MB 988 #define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U 989 /** 990 * @} 991 */ 992 993 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 994 * @{ 995 */ 996 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 997 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 998 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 999 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1000 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1001 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1002 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1003 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1004 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1005 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1006 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1007 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1008 /** 1009 * @} 1010 */ 1011 1012 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1013 * @{ 1014 */ 1015 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1016 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1017 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1018 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1019 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1020 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1021 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1022 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1023 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1024 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1025 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1026 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1032 * @{ 1033 */ 1034 #define ETH_DMA_NORMAL_IT ETH_DMAIER_NISE 1035 #define ETH_DMA_ABNORMAL_IT ETH_DMAIER_AISE 1036 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMAIER_FBEIE 1037 #define ETH_DMA_EARLY_RX_IT ETH_DMAIER_ERIE 1038 #define ETH_DMA_EARLY_TX_IT ETH_DMAIER_ETIE 1039 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMAIER_RWTIE 1040 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMAIER_RPSIE 1041 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMAIER_RBUIE 1042 #define ETH_DMA_RX_IT ETH_DMAIER_RIE 1043 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMAIER_TBUIE 1044 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMAIER_TPSIE 1045 #define ETH_DMA_TX_IT ETH_DMAIER_TIE 1046 /** 1047 * @} 1048 */ 1049 1050 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 1051 * @{ 1052 */ 1053 #define ETH_DMA_NO_ERROR_FLAG 0x00000000U 1054 #define ETH_DMA_TX_DATA_TRANS_ERROR_FLAG ETH_DMASR_EBS_DataTransfTx 1055 #define ETH_DMA_RX_DATA_TRANS_ERROR_FLAG 0x00000000U 1056 #define ETH_DMA_READ_TRANS_ERROR_FLAG ETH_DMASR_EBS_ReadTransf 1057 #define ETH_DMA_WRITE_TRANS_ERROR_FLAG 0x00000000U 1058 #define ETH_DMA_DESC_ACCESS_ERROR_FLAG ETH_DMASR_EBS_DescAccess 1059 #define ETH_DMA_DATA_BUFF_ACCESS_ERROR_FLAG 0x00000000U 1060 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMASR_FBES 1061 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMASR_ETS 1062 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMASR_RWTS 1063 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMASR_RPSS 1064 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMASR_RBUS 1065 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMASR_TPS 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 1071 * @{ 1072 */ 1073 #define ETH_TRANSMITSTOREFORWARD ETH_DMAOMR_TSF 1074 #define ETH_TRANSMITTHRESHOLD_16 ETH_DMAOMR_TTC_16Bytes 1075 #define ETH_TRANSMITTHRESHOLD_24 ETH_DMAOMR_TTC_24Bytes 1076 #define ETH_TRANSMITTHRESHOLD_32 ETH_DMAOMR_TTC_32Bytes 1077 #define ETH_TRANSMITTHRESHOLD_40 ETH_DMAOMR_TTC_40Bytes 1078 #define ETH_TRANSMITTHRESHOLD_64 ETH_DMAOMR_TTC_64Bytes 1079 #define ETH_TRANSMITTHRESHOLD_128 ETH_DMAOMR_TTC_128Bytes 1080 #define ETH_TRANSMITTHRESHOLD_192 ETH_DMAOMR_TTC_192Bytes 1081 #define ETH_TRANSMITTHRESHOLD_256 ETH_DMAOMR_TTC_256Bytes 1082 /** 1083 * @} 1084 */ 1085 1086 /** @defgroup ETH_Receive_Mode ETH Receive Mode 1087 * @{ 1088 */ 1089 #define ETH_RECEIVESTOREFORWARD ETH_DMAOMR_RSF 1090 #define ETH_RECEIVETHRESHOLD8_64 ETH_DMAOMR_RTC_64Bytes 1091 #define ETH_RECEIVETHRESHOLD8_32 ETH_DMAOMR_RTC_32Bytes 1092 #define ETH_RECEIVETHRESHOLD8_96 ETH_DMAOMR_RTC_96Bytes 1093 #define ETH_RECEIVETHRESHOLD8_128 ETH_DMAOMR_RTC_128Bytes 1094 /** 1095 * @} 1096 */ 1097 1098 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1099 * @{ 1100 */ 1101 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACFCR_PLT_Minus4 1102 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACFCR_PLT_Minus28 1103 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACFCR_PLT_Minus144 1104 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACFCR_PLT_Minus256 1105 /** 1106 * @} 1107 */ 1108 1109 1110 /** @defgroup ETH_Speed ETH Speed 1111 * @{ 1112 */ 1113 #define ETH_SPEED_10M 0x00000000U 1114 #define ETH_SPEED_100M 0x00004000U 1115 /** 1116 * @} 1117 */ 1118 1119 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 1120 * @{ 1121 */ 1122 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 1123 #define ETH_HALFDUPLEX_MODE 0x00000000U 1124 /** 1125 * @} 1126 */ 1127 1128 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1129 * @{ 1130 */ 1131 #define ETH_BACKOFFLIMIT_10 0x00000000U 1132 #define ETH_BACKOFFLIMIT_8 0x00000020U 1133 #define ETH_BACKOFFLIMIT_4 0x00000040U 1134 #define ETH_BACKOFFLIMIT_1 0x00000060U 1135 /** 1136 * @} 1137 */ 1138 1139 1140 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 1141 * @{ 1142 */ 1143 #define ETH_SOURCEADDRESS_DISABLE 0x00000000U 1144 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 1145 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 1146 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 1147 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 1148 /** 1149 * @} 1150 */ 1151 1152 1153 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1154 * @{ 1155 */ 1156 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 1157 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1158 /** 1159 * @} 1160 */ 1161 1162 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1163 * @{ 1164 */ 1165 #define ETH_MAC_ADDRESS0 0x00000000U 1166 #define ETH_MAC_ADDRESS1 0x00000008U 1167 #define ETH_MAC_ADDRESS2 0x00000010U 1168 #define ETH_MAC_ADDRESS3 0x00000018U 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1174 * @{ 1175 */ 1176 #define ETH_MAC_PMT_IT ETH_MACSR_PMTS 1177 /** 1178 * @} 1179 */ 1180 1181 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 1182 * @{ 1183 */ 1184 #define ETH_WAKEUP_FRAME_RECIEVED ETH_MACPMTCSR_WFR 1185 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPMTCSR_MPR 1186 /** 1187 * @} 1188 */ 1189 1190 1191 /** @defgroup ETH_State_Codes ETH States 1192 * @{ 1193 */ 1194 #define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ 1195 #define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */ 1196 #define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */ 1197 #define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */ 1198 #define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */ 1199 /** 1200 * @} 1201 */ 1202 1203 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 1204 * @{ 1205 */ 1206 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 1207 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 1208 1209 /** 1210 * @} 1211 */ 1212 /** @defgroup ETH_Rx_Mode ETH Rx Mode 1213 * @{ 1214 */ 1215 #define ETH_RXPOLLING_MODE 0x00000000U 1216 #define ETH_RXINTERRUPT_MODE 0x00000001U 1217 /** 1218 * @} 1219 */ 1220 1221 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 1222 * @{ 1223 */ 1224 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 1225 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 1226 /** 1227 * @} 1228 */ 1229 1230 /** @defgroup ETH_Media_Interface ETH Media Interface 1231 * @{ 1232 */ 1233 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 1234 #define ETH_MEDIA_INTERFACE_RMII (SYSCFG_PMC_MII_RMII_SEL) 1235 /** 1236 * @} 1237 */ 1238 1239 /** @defgroup ETH_Watchdog ETH Watchdog 1240 * @{ 1241 */ 1242 #define ETH_WATCHDOG_ENABLE 0x00000000U 1243 #define ETH_WATCHDOG_DISABLE 0x00800000U 1244 /** 1245 * @} 1246 */ 1247 1248 /** @defgroup ETH_Jabber ETH Jabber 1249 * @{ 1250 */ 1251 #define ETH_JABBER_ENABLE 0x00000000U 1252 #define ETH_JABBER_DISABLE 0x00400000U 1253 /** 1254 * @} 1255 */ 1256 1257 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 1258 * @{ 1259 */ 1260 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 1261 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 1262 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 1263 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 1264 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 1265 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 1266 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 1267 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 1268 /** 1269 * @} 1270 */ 1271 1272 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1273 * @{ 1274 */ 1275 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 1276 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 1277 /** 1278 * @} 1279 */ 1280 1281 /** @defgroup ETH_Receive_Own ETH Receive Own 1282 * @{ 1283 */ 1284 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 1285 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 1286 /** 1287 * @} 1288 */ 1289 1290 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1291 * @{ 1292 */ 1293 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 1294 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 1295 /** 1296 * @} 1297 */ 1298 1299 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1300 * @{ 1301 */ 1302 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 1303 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 1304 /** 1305 * @} 1306 */ 1307 1308 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1309 * @{ 1310 */ 1311 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 1312 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1318 * @{ 1319 */ 1320 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 1321 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 1322 /** 1323 * @} 1324 */ 1325 1326 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1327 * @{ 1328 */ 1329 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 1330 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 1331 /** 1332 * @} 1333 */ 1334 1335 /** @defgroup ETH_Receive_All ETH Receive All 1336 * @{ 1337 */ 1338 #define ETH_RECEIVEALL_ENABLE 0x80000000U 1339 #define ETH_RECEIVEALL_DISABLE 0x00000000U 1340 /** 1341 * @} 1342 */ 1343 1344 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1345 * @{ 1346 */ 1347 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 1348 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 1349 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1355 * @{ 1356 */ 1357 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 1358 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1359 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1365 * @{ 1366 */ 1367 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 1368 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 1369 /** 1370 * @} 1371 */ 1372 1373 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1374 * @{ 1375 */ 1376 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 1377 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 1378 /** 1379 * @} 1380 */ 1381 1382 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1383 * @{ 1384 */ 1385 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 1386 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 1387 /** 1388 * @} 1389 */ 1390 1391 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1392 * @{ 1393 */ 1394 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 1395 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 1396 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 1397 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 1398 /** 1399 * @} 1400 */ 1401 1402 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1403 * @{ 1404 */ 1405 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 1406 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 1407 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 1408 /** 1409 * @} 1410 */ 1411 1412 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1413 * @{ 1414 */ 1415 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 1416 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 1417 /** 1418 * @} 1419 */ 1420 1421 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1422 * @{ 1423 */ 1424 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 1425 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 1426 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 1427 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 1428 /** 1429 * @} 1430 */ 1431 1432 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1433 * @{ 1434 */ 1435 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 1436 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 1437 /** 1438 * @} 1439 */ 1440 1441 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1442 * @{ 1443 */ 1444 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 1445 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 1446 /** 1447 * @} 1448 */ 1449 1450 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1451 * @{ 1452 */ 1453 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 1454 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 1455 /** 1456 * @} 1457 */ 1458 1459 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1460 * @{ 1461 */ 1462 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 1463 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 1464 /** 1465 * @} 1466 */ 1467 1468 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1469 * @{ 1470 */ 1471 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 1472 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 1473 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 1474 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 1475 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 1476 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 1477 /** 1478 * @} 1479 */ 1480 1481 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1482 * @{ 1483 */ 1484 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1485 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1486 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1487 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1488 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1489 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1490 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1491 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1492 /** 1493 * @} 1494 */ 1495 1496 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1497 * @{ 1498 */ 1499 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1500 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1501 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1502 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1503 /** 1504 * @} 1505 */ 1506 1507 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1508 * @{ 1509 */ 1510 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 1511 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 1512 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 1513 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 1514 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 1515 /** 1516 * @} 1517 */ 1518 1519 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1520 * @{ 1521 */ 1522 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 1523 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 1524 /** 1525 * @} 1526 */ 1527 1528 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1529 * @{ 1530 */ 1531 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 1532 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 1533 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1534 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1535 /** 1536 * @} 1537 */ 1538 1539 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1540 * @{ 1541 */ 1542 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 1543 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 1544 /** 1545 * @} 1546 */ 1547 1548 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1549 * @{ 1550 */ 1551 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 1552 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 1553 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 1554 /** 1555 * @} 1556 */ 1557 1558 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1559 * @{ 1560 */ 1561 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 1562 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 1563 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 1564 /** 1565 * @} 1566 */ 1567 1568 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1569 * @{ 1570 */ 1571 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 1572 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 1573 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 1574 /** 1575 * @} 1576 */ 1577 1578 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1579 * @{ 1580 */ 1581 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 1582 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 1583 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 1584 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 1585 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 1586 /** 1587 * @} 1588 */ 1589 1590 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1591 * @{ 1592 */ 1593 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1594 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1595 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1596 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1597 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 1598 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 1599 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 1600 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 1601 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 1602 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 1603 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 1604 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 1605 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 1606 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 1607 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 1608 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 1609 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 1610 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 1611 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 1612 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 1613 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 1614 /** 1615 * @} 1616 */ 1617 1618 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1619 * @{ 1620 */ 1621 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 1622 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 1623 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 1624 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 1625 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 1626 /** 1627 * @} 1628 */ 1629 1630 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1631 * @{ 1632 */ 1633 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1634 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1635 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1636 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 1637 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 1638 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 1639 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 1640 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 1641 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 1642 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 1643 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 1644 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 1645 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 1646 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 1647 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 1648 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 1649 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 1650 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 1651 /** 1652 * @} 1653 */ 1654 1655 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1656 * @{ 1657 */ 1658 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 1659 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 1660 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 1661 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 1662 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 1663 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 1664 1665 /** 1666 * @} 1667 */ 1668 1669 1670 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1671 * @{ 1672 */ 1673 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 1674 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 1675 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 1676 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 1677 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 1678 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 1679 1680 /** 1681 * @} 1682 */ 1683 1684 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1685 * @{ 1686 */ 1687 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 1688 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 1689 /** 1690 * @} 1691 */ 1692 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status 1693 * @{ 1694 */ 1695 #define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */ 1696 #define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */ 1697 /** 1698 * @} 1699 */ 1700 1701 /** 1702 * @} 1703 */ 1704 1705 /* Exported macro ------------------------------------------------------------*/ 1706 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1707 * @{ 1708 */ 1709 1710 /** @brief Reset ETH handle state 1711 * @param __HANDLE__: specifies the ETH handle. 1712 * @retval None 1713 */ 1714 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1715 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1716 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1717 (__HANDLE__)->MspInitCallback = NULL; \ 1718 (__HANDLE__)->MspDeInitCallback = NULL; \ 1719 } while(0) 1720 #else 1721 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1722 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1723 } while(0) 1724 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1725 1726 /** 1727 * @brief Enables the specified ETHERNET DMA interrupts. 1728 * @param __HANDLE__ : ETH Handle 1729 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1730 * enabled @ref ETH_DMA_Interrupts 1731 * @retval None 1732 */ 1733 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ 1734 |= (__INTERRUPT__)) 1735 1736 /** 1737 * @brief Disables the specified ETHERNET DMA interrupts. 1738 * @param __HANDLE__ : ETH Handle 1739 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1740 * disabled. @ref ETH_DMA_Interrupts 1741 * @retval None 1742 */ 1743 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ 1744 &= ~(__INTERRUPT__)) 1745 1746 /** 1747 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 1748 * @param __HANDLE__ : ETH Handle 1749 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1750 * @retval The ETH DMA IT Source enabled or disabled 1751 */ 1752 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\ 1753 (__INTERRUPT__)) == (__INTERRUPT__)) 1754 1755 /** 1756 * @brief Gets the ETHERNET DMA IT pending bit. 1757 * @param __HANDLE__ : ETH Handle 1758 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1759 * @retval The state of ETH DMA IT (SET or RESET) 1760 */ 1761 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\ 1762 (__INTERRUPT__)) == (__INTERRUPT__)) 1763 1764 /** 1765 * @brief Clears the ETHERNET DMA IT pending bit. 1766 * @param __HANDLE__ : ETH Handle 1767 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1768 * @retval None 1769 */ 1770 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__)) 1771 1772 /** 1773 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1774 * @param __HANDLE__: ETH Handle 1775 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1776 * @retval The state of ETH DMA FLAG (SET or RESET). 1777 */ 1778 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &\ 1779 ( __FLAG__)) == ( __FLAG__)) 1780 1781 /** 1782 * @brief Clears the specified ETHERNET DMA flag. 1783 * @param __HANDLE__: ETH Handle 1784 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1785 * @retval The state of ETH DMA FLAG (SET or RESET). 1786 */ 1787 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = ( __FLAG__)) 1788 1789 1790 1791 /** 1792 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1793 * @param __HANDLE__: ETH Handle 1794 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 1795 * @retval The state of ETH MAC IT (SET or RESET). 1796 */ 1797 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ 1798 ( __INTERRUPT__)) == ( __INTERRUPT__)) 1799 1800 /*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ 1801 #define ETH_WAKEUP_EXTI_LINE 0x00080000U 1802 1803 /** 1804 * @brief Enable the ETH WAKEUP Exti Line. 1805 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1806 * @arg ETH_WAKEUP_EXTI_LINE 1807 * @retval None. 1808 */ 1809 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) 1810 1811 /** 1812 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1813 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1814 * @arg ETH_WAKEUP_EXTI_LINE 1815 * @retval EXTI ETH WAKEUP Line Status. 1816 */ 1817 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 1818 1819 /** 1820 * @brief Clear the ETH WAKEUP Exti flag. 1821 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1822 * @arg ETH_WAKEUP_EXTI_LINE 1823 * @retval None. 1824 */ 1825 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 1826 1827 /** 1828 * @brief enable rising edge interrupt on selected EXTI line. 1829 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1830 * @arg ETH_WAKEUP_EXTI_LINE 1831 * @retval None 1832 */ 1833 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ 1834 (EXTI->RTSR |= (__EXTI_LINE__)) 1835 1836 /** 1837 * @brief enable falling edge interrupt on selected EXTI line. 1838 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1839 * @arg ETH_WAKEUP_EXTI_LINE 1840 * @retval None 1841 */ 1842 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ 1843 (EXTI->FTSR |= (__EXTI_LINE__)) 1844 1845 /** 1846 * @brief enable falling edge interrupt on selected EXTI line. 1847 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1848 * @arg ETH_WAKEUP_EXTI_LINE 1849 * @retval None 1850 */ 1851 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ 1852 (EXTI->FTSR |= (__EXTI_LINE__)) 1853 1854 /** 1855 * @brief Generates a Software interrupt on selected EXTI line. 1856 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1857 * @arg ETH_WAKEUP_EXTI_LINE 1858 * @retval None 1859 */ 1860 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 1861 1862 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \ 1863 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1864 1865 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) 1866 1867 /** 1868 * @} 1869 */ 1870 1871 1872 /* Exported functions --------------------------------------------------------*/ 1873 1874 /** @addtogroup ETH_Exported_Functions 1875 * @{ 1876 */ 1877 1878 /** @addtogroup ETH_Exported_Functions_Group1 1879 * @{ 1880 */ 1881 /* Initialization and de initialization functions **********************************/ 1882 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 1883 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 1884 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 1885 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 1886 1887 /* Callbacks Register/UnRegister functions ***********************************/ 1888 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1889 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, 1890 pETH_CallbackTypeDef pCallback); 1891 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 1892 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1893 1894 /** 1895 * @} 1896 */ 1897 1898 /** @addtogroup ETH_Exported_Functions_Group2 1899 * @{ 1900 */ 1901 /* IO operation functions *******************************************************/ 1902 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 1903 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); 1904 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 1905 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); 1906 1907 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); 1908 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, 1909 pETH_rxAllocateCallbackTypeDef rxAllocateCallback); 1910 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); 1911 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); 1912 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); 1913 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode); 1914 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); 1915 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); 1916 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); 1917 1918 #ifdef HAL_ETH_USE_PTP 1919 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 1920 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 1921 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 1922 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 1923 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, 1924 ETH_TimeTypeDef *timeoffset); 1925 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); 1926 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 1927 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 1928 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); 1929 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); 1930 #endif /* HAL_ETH_USE_PTP */ 1931 1932 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout); 1933 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig); 1934 1935 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 1936 uint32_t RegValue); 1937 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 1938 uint32_t *pRegValue); 1939 1940 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 1941 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 1942 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 1943 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 1944 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); 1945 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); 1946 void HAL_ETH_RxAllocateCallback(uint8_t **buff); 1947 void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); 1948 void HAL_ETH_TxFreeCallback(uint32_t *buff); 1949 void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); 1950 /** 1951 * @} 1952 */ 1953 1954 /** @addtogroup ETH_Exported_Functions_Group3 1955 * @{ 1956 */ 1957 /* Peripheral Control functions **********************************************/ 1958 /* MAC & DMA Configuration APIs **********************************************/ 1959 HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1960 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1961 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1962 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1963 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); 1964 1965 /* MAC VLAN Processing APIs ************************************************/ 1966 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, 1967 uint32_t VLANIdentifier); 1968 1969 /* MAC L2 Packet Filtering APIs **********************************************/ 1970 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 1971 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); 1972 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); 1973 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, 1974 const uint8_t *pMACAddr); 1975 1976 /* MAC Power Down APIs *****************************************************/ 1977 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, 1978 const ETH_PowerDownConfigTypeDef *pPowerDownConfig); 1979 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); 1980 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); 1981 1982 /** 1983 * @} 1984 */ 1985 1986 /** @addtogroup ETH_Exported_Functions_Group4 1987 * @{ 1988 */ 1989 /* Peripheral State functions **************************************************/ 1990 HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth); 1991 uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth); 1992 uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth); 1993 uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth); 1994 uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); 1995 /** 1996 * @} 1997 */ 1998 1999 /** 2000 * @} 2001 */ 2002 2003 /** 2004 * @} 2005 */ 2006 2007 /** 2008 * @} 2009 */ 2010 2011 #endif /* ETH */ 2012 2013 #ifdef __cplusplus 2014 } 2015 #endif 2016 2017 #endif /* STM32F7xx_HAL_ETH_H */ 2018
