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Searched refs:Configuration (Results 1 – 25 of 60) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_mdma.h817 …d LL_MDMA_ConfigXferEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) in LL_MDMA_ConfigXferEndianness() argument
822 MDMA_CCR_WEX | MDMA_CCR_HEX | MDMA_CCR_BEX, Configuration); in LL_MDMA_ConfigXferEndianness()
1146 …_ConfigTransfer(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t Buff… in LL_MDMA_ConfigTransfer() argument
1151 Configuration | ((BufferXferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk)); in LL_MDMA_ConfigTransfer()
2361 …MDMA_ConfigBlkRepeatAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) in LL_MDMA_ConfigBlkRepeatAddrUpdate() argument
2367 Configuration); in LL_MDMA_ConfigBlkRepeatAddrUpdate()
2909 …oid LL_MDMA_ConfigBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) in LL_MDMA_ConfigBusSelection() argument
2915 Configuration); in LL_MDMA_ConfigBusSelection()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h1216 …INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigControl() argument
1220 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); in LL_DMA_ConfigControl()
1410 …NLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
1415 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
1468 …INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelSecure() argument
1471 …MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << … in LL_DMA_ConfigChannelSecure()
1473 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
2231 …oid LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelTransfer() argument
2236 Configuration); in LL_DMA_ConfigChannelTransfer()
Dstm32wbaxx_ll_tim.h2338 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2344 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2346 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3165 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3170 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3173 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
4682 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
4684 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h1855 …INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigControl() argument
1859 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); in LL_DMA_ConfigControl()
2049 …NLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
2054 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2107 …INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelSecure() argument
2110 …MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << … in LL_DMA_ConfigChannelSecure()
2112 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
2873 …oid LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelTransfer() argument
2878 DMA_CTR2_PFREQ), Configuration); in LL_DMA_ConfigChannelTransfer()
4071 …id LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigBlkRptAddrUpdate() argument
[all …]
Dstm32h5xx_ll_tim.h2647 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2653 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2655 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3474 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3479 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3482 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
5067 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
5069 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h1711 …INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigControl() argument
1715 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); in LL_DMA_ConfigControl()
1965 …NLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
1970 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2040 …INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelSecure() argument
2043 …MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << … in LL_DMA_ConfigChannelSecure()
2045 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
3065 …oid LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelTransfer() argument
3070 Configuration); in LL_DMA_ConfigChannelTransfer()
4053 …id LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigBlkRptAddrUpdate() argument
[all …]
Dstm32u5xx_ll_tim.h2578 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2584 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2586 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3405 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3410 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3413 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
5018 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
5020 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma.h2103 …INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigControl() argument
2107 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); in LL_DMA_ConfigControl()
2355 …NLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
2360 …MA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2599 …INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelSecure() argument
2602 …MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << … in LL_DMA_ConfigChannelSecure()
2604 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); in LL_DMA_ConfigChannelSecure()
3677 …oid LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelTransfer() argument
3682 DMA_CTR2_PFREQ), Configuration); in LL_DMA_ConfigChannelTransfer()
5191 …id LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigBlkRptAddrUpdate() argument
[all …]
Dstm32n6xx_ll_tim.h2435 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2441 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2443 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3262 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3267 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3270 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
4880 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
4882 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h1681 …INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigControl() argument
1685 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); in LL_DMA_ConfigControl()
1933 …NLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
1938 …MA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); in LL_DMA_ConfigTransfer()
2861 …oid LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelTransfer() argument
2866 DMA_CTR2_PFREQ), Configuration); in LL_DMA_ConfigChannelTransfer()
3873 …id LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigBlkRptAddrUpdate() argument
3877 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); in LL_DMA_ConfigBlkRptAddrUpdate()
Dstm32h7rsxx_ll_tim.h2351 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2357 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2359 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3178 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3183 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3186 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
4742 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
4744 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_tim.h1656 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1662 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1664 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2239 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2244 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2247 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_tim.h1677 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1683 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1685 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2260 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2265 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2268 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_tim.h1629 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1635 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1637 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2187 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2192 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2195 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_tim.h1699 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1705 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1707 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2282 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2287 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2290 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_tim.h1351 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1357 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1819 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
1824 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
1827 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_tim.h1341 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1347 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1833 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
1838 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
1841 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_tim.h1898 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1904 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1906 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2613 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2618 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2621 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h2711 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2717 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2719 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
3538 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
3543 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
3546 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
5148 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) in LL_TIM_ConfigIDX() argument
5150 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_tim.h2099 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2105 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2107 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2828 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2833 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2836 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_tim.h2101 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2107 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2109 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2830 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2835 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2838 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_tim.h1951 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
1957 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
1959 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2680 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2685 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2688 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_tim.h2026 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2032 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2034 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2755 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2760 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2763 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_tim.h2045 …TIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_OC_ConfigOutput() argument
2051 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_OC_ConfigOutput()
2053 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); in LL_TIM_OC_ConfigOutput()
2774 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2779 … ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ in LL_TIM_IC_Config()
2782 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
Dstm32wlxx_ll_dma.h554 …INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigChannelSecure() argument
559 Configuration); in LL_DMA_ConfigChannelSecure()
641 …ATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) in LL_DMA_ConfigTransfer() argument
646 Configuration); in LL_DMA_ConfigTransfer()

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