1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32WBAxx_LL_DMA_H
41 #define STM32WBAxx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32wbaxx.h"
49
50 /** @addtogroup STM32WBAxx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74
75 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
76 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
77 {
78 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
79 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
80 };
81
82 /**
83 * @}
84 */
85
86 /* Private constants ---------------------------------------------------------*/
87 /* Private macros ------------------------------------------------------------*/
88 /* Exported types ------------------------------------------------------------*/
89
90 #if defined (USE_FULL_LL_DRIVER)
91 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
92 * @{
93 */
94
95 /**
96 * @brief LL DMA init structure definition.
97 */
98 typedef struct
99 {
100 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
101 Programming this field is mandatory for all available DMA channels.
102 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
103 This feature can be modified afterwards using unitary function
104 @ref LL_DMA_SetSrcAddress(). */
105
106 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
107 Programming this field is mandatory for all available DMA channels.
108 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
109 This feature can be modified afterwards using unitary function
110 @ref LL_DMA_SetDestAddress(). */
111
112 uint32_t Direction; /*!< This field specify the data transfer direction.
113 Programming this field is mandatory for all available DMA channels.
114 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
115 This feature can be modified afterwards using unitary function
116 @ref LL_DMA_SetDataTransferDirection(). */
117
118 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
119 Programming this field is mandatory for all available DMA channels.
120 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
121 This feature can be modified afterwards using unitary function
122 @ref LL_DMA_SetBlkHWRequest(). */
123
124 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
125 Programming this field is mandatory for all available DMA channels.
126 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
127 This feature can be modified afterwards using unitary function
128 @ref LL_DMA_SetDataAlignment(). */
129
130 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
131 Programming this field is mandatory for all available DMA channels.
132 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
133 This feature can be modified afterwards using unitary function
134 @ref LL_DMA_SetSrcBurstLength(). */
135
136 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
137 Programming this field is mandatory for all available DMA channels.
138 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
139 This feature can be modified afterwards using unitary function
140 @ref LL_DMA_SetDestBurstLength(). */
141
142 uint32_t SrcDataWidth; /*!< This field specify the source data width.
143 Programming this field is mandatory for all available DMA channels.
144 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
145 This feature can be modified afterwards using unitary function
146 @ref LL_DMA_SetSrcDataWidth(). */
147
148 uint32_t DestDataWidth; /*!< This field specify the destination data width.
149 Programming this field is mandatory for all available DMA channels.
150 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
151 This feature can be modified afterwards using unitary function
152 @ref LL_DMA_SetDestDataWidth(). */
153
154 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
155 Programming this field is mandatory for all available DMA channels.
156 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
157 This feature can be modified afterwards using unitary function
158 @ref LL_DMA_SetSrcIncMode(). */
159
160 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
161 Programming this field is mandatory for all available DMA channels.
162 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
163 This feature can be modified afterwards using unitary function
164 @ref LL_DMA_SetDestIncMode(). */
165
166 uint32_t Priority; /*!< This field specify the channel priority level.
167 Programming this field is mandatory for all available DMA channels.
168 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
169 This feature can be modified afterwards using unitary function
170 @ref LL_DMA_SetChannelPriorityLevel(). */
171
172 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
173 Programming this field is mandatory for all available DMA channels.
174 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
175 This feature can be modified afterwards using unitary function
176 @ref LL_DMA_SetBlkDataLength(). */
177
178 uint32_t TriggerMode; /*!< This field specify the trigger mode.
179 Programming this field is mandatory for all available DMA channels.
180 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
181 This feature can be modified afterwards using unitary function
182 @ref LL_DMA_SetTriggerMode(). */
183
184 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
185 Programming this field is mandatory for all available DMA channels.
186 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
187 This feature can be modified afterwards using unitary function
188 @ref LL_DMA_SetTriggerPolarity(). */
189
190 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
191 Programming this field is mandatory for all available DMA channels.
192 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
193 This feature can be modified afterwards using unitary function
194 @ref LL_DMA_SetHWTrigger(). */
195
196 uint32_t Request; /*!< This field specify the peripheral request selection.
197 Programming this field is mandatory for all available DMA channels.
198 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
199 This feature can be modified afterwards using unitary function
200 @ref LL_DMA_SetPeriphRequest(). */
201
202 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
203 Programming this field is mandatory for all available DMA channels.
204 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
205 This feature can be modified afterwards using unitary function
206 @ref LL_DMA_SetTransferEventMode(). */
207
208 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
209 Programming this field is mandatory for all available DMA channels.
210 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
211 This feature can be modified afterwards using unitary function
212 @ref LL_DMA_SetDestHWordExchange(). */
213
214 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
215 Programming this field is mandatory for all available DMA channels.
216 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
217 This feature can be modified afterwards using unitary function
218 @ref LL_DMA_SetDestByteExchange(). */
219
220 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
221 Programming this field is mandatory for all available DMA channels.
222 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
223 This feature can be modified afterwards using unitary function
224 @ref LL_DMA_SetSrcByteExchange(). */
225
226 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
227 Programming this field is mandatory for all available DMA channels.
228 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
229 This feature can be modified afterwards using unitary function
230 @ref LL_DMA_SetSrcAllocatedPort(). */
231
232 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
233 Programming this field is mandatory for all available DMA channels.
234 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
235 This feature can be modified afterwards using unitary function
236 @ref LL_DMA_SetDestAllocatedPort(). */
237
238 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
239 Programming this field is mandatory for all available DMA channels.
240 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
241 This feature can be modified afterwards using unitary function
242 @ref LL_DMA_SetLinkAllocatedPort(). */
243
244 uint32_t LinkStepMode; /*!< This field specify the link step mode.
245 Programming this field is mandatory for all available DMA channels.
246 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
247 This feature can be modified afterwards using unitary function
248 @ref LL_DMA_SetLinkStepMode(). */
249
250 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
251 Programming this field is mandatory for all available DMA channels.
252 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
253 bytes are always forced to 0).
254 This feature can be modified afterwards using unitary function
255 @ref LL_DMA_SetLinkedListBaseAddr(). */
256
257 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
258 Programming this field is mandatory for all available DMA channels.
259 This parameter can be a value Between 0 to 0x0000FFFC.
260 This feature can be modified afterwards using unitary function
261 @ref LL_DMA_SetLinkedListAddrOffset(). */
262
263 } LL_DMA_InitTypeDef;
264
265
266 /**
267 * @brief LL DMA init linked list structure definition.
268 */
269 typedef struct
270 {
271 uint32_t Priority; /*!< This field specify the channel priority level.
272 Programming this field is mandatory for all available DMA channels.
273 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
274 This feature can be modified afterwards using unitary function
275 @ref LL_DMA_SetChannelPriorityLevel(). */
276
277 uint32_t LinkStepMode; /*!< This field specify the link step mode.
278 Programming this field is mandatory for all available DMA channels.
279 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
280 This feature can be modified afterwards using unitary function
281 @ref LL_DMA_SetLinkStepMode(). */
282
283 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
284 Programming this field is mandatory for all available DMA channels.
285 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
286 This feature can be modified afterwards using unitary function
287 @ref LL_DMA_SetLinkAllocatedPort(). */
288
289 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
290 Programming this field is mandatory for all available DMA channels.
291 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
292 This feature can be modified afterwards using unitary function
293 @ref LL_DMA_SetTransferEventMode(). */
294 } LL_DMA_InitLinkedListTypeDef;
295
296
297 /**
298 * @brief LL DMA node init structure definition.
299 */
300 typedef struct
301 {
302 /* CTR1 register fields ******************************************************
303 If any CTR1 fields need to be updated comparing to previous node, it is
304 mandatory to update the new value in CTR1 register fields and enable update
305 CTR1 register in UpdateRegisters fields if it is not enabled in the
306 previous node.
307
308 */
309 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
310 uint32_t DestSecure; /*!< This field specify the destination secure.
311 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
312 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
313
314 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
315 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
316
317 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
318 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
319
320 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
321 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
322
323 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
324 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
325
326 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
327 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
328
329 uint32_t DestDataWidth; /*!< This field specify the destination data width.
330 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
331
332 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
333 uint32_t SrcSecure; /*!< This field specify the source secure.
334 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
335 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
336
337 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
338 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
339
340 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
341 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
342
343 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
344 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
345
346 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
347 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
348
349 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
350 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
351
352 uint32_t SrcDataWidth; /*!< This field specify the source data width.
353 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
354
355
356 /* CTR2 register fields ******************************************************
357 If any CTR2 fields need to be updated comparing to previous node, it is
358 mandatory to update the new value in CTR2 register fields and enable update
359 CTR2 register in UpdateRegisters fields if it is not enabled in the
360 previous node.
361
362 For all node created, filling all fields is mandatory.
363 */
364 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
365 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
366
367 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
368 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
369
370 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
371 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
372
373 uint32_t TriggerMode; /*!< This field specify the trigger mode.
374 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
375
376 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
377 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
378
379 uint32_t Direction; /*!< This field specify the transfer direction.
380 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
381
382 uint32_t Request; /*!< This field specify the peripheral request selection.
383 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
384
385
386 /* CBR1 register fields ******************************************************
387 If any CBR1 fields need to be updated comparing to previous node, it is
388 mandatory to update the new value in CBR1 register fields and enable update
389 CBR1 register in UpdateRegisters fields if it is not enabled in the
390 previous node.
391 */
392
393 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
394 This parameter must be a value between Min_Data = 0
395 and Max_Data = 0x0000FFFF. */
396
397 /* CSAR register fields ******************************************************
398 If any CSAR fields need to be updated comparing to previous node, it is
399 mandatory to update the new value in CSAR register fields and enable update
400 CSAR register in UpdateRegisters fields if it is not enabled in the
401 previous node.
402
403 For all node created, filling all fields is mandatory.
404 */
405 uint32_t SrcAddress; /*!< This field specify the transfer source address.
406 This parameter must be a value between Min_Data = 0
407 and Max_Data = 0xFFFFFFFF. */
408
409
410 /* CDAR register fields ******************************************************
411 If any CDAR fields need to be updated comparing to previous node, it is
412 mandatory to update the new value in CDAR register fields and enable update
413 CDAR register in UpdateRegisters fields if it is not enabled in the
414 previous node.
415
416 For all node created, filling all fields is mandatory.
417 */
418 uint32_t DestAddress; /*!< This field specify the transfer destination address.
419 This parameter must be a value between Min_Data = 0
420 and Max_Data = 0xFFFFFFFF. */
421
422 /* CLLR register fields ******************************************************
423 If any CLLR fields need to be updated comparing to previous node, it is
424 mandatory to update the new value in CLLR register fields and enable update
425 CLLR register in UpdateRegisters fields if it is not enabled in the
426 previous node.
427 */
428 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
429 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
430
431 /* DMA Node type field *******************************************************
432 This parameter defines node types as node size and node content varies
433 between channels.
434 Thanks to this fields, linked list queue could be created independently
435 from channel selection. So, one queue could be executed by all DMA channels.
436 */
437 uint32_t NodeType; /*!< Specifies the node type to be created.
438 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
439 } LL_DMA_InitNodeTypeDef;
440
441 /**
442 * @brief LL DMA linked list node structure definition.
443 * @note For GPDMA linear addressing channels, the maximum node size is :
444 * (4 Bytes * 6 registers = 24 Bytes).
445 */
446 typedef struct
447 {
448 __IO uint32_t LinkRegisters[6U];
449
450 } LL_DMA_LinkNodeTypeDef;
451 /**
452 * @}
453 */
454
455 #endif /* USE_FULL_LL_DRIVER */
456
457 /* Exported constants --------------------------------------------------------*/
458
459 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
460 * @{
461 */
462
463 /** @defgroup DMA_LL_EC_CHANNEL Channel
464 * @{
465 */
466 #define LL_DMA_CHANNEL_0 (0x00U)
467 #define LL_DMA_CHANNEL_1 (0x01U)
468 #define LL_DMA_CHANNEL_2 (0x02U)
469 #define LL_DMA_CHANNEL_3 (0x03U)
470 #define LL_DMA_CHANNEL_4 (0x04U)
471 #define LL_DMA_CHANNEL_5 (0x05U)
472 #define LL_DMA_CHANNEL_6 (0x06U)
473 #define LL_DMA_CHANNEL_7 (0x07U)
474 #define LL_DMA_CHANNEL_8 (0x08U)
475 #define LL_DMA_CHANNEL_9 (0x09U)
476 #define LL_DMA_CHANNEL_10 (0x0AU)
477 #define LL_DMA_CHANNEL_11 (0x0BU)
478 #define LL_DMA_CHANNEL_12 (0x0CU)
479 #define LL_DMA_CHANNEL_13 (0x0DU)
480 #define LL_DMA_CHANNEL_14 (0x0EU)
481 #define LL_DMA_CHANNEL_15 (0x0FU)
482 #if defined (USE_FULL_LL_DRIVER)
483 #define LL_DMA_CHANNEL_ALL (0x10U)
484 #endif /* USE_FULL_LL_DRIVER */
485 /**
486 * @}
487 */
488
489 #if defined (USE_FULL_LL_DRIVER)
490 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
491 * @{
492 */
493 #define LL_DMA_CLLR_OFFSET0 (0x00U)
494 #define LL_DMA_CLLR_OFFSET1 (0x01U)
495 #define LL_DMA_CLLR_OFFSET2 (0x02U)
496 #define LL_DMA_CLLR_OFFSET3 (0x03U)
497 #define LL_DMA_CLLR_OFFSET4 (0x04U)
498 #define LL_DMA_CLLR_OFFSET5 (0x05U)
499 #define LL_DMA_CLLR_OFFSET6 (0x06U)
500 #define LL_DMA_CLLR_OFFSET7 (0x07U)
501 /**
502 * @}
503 */
504 #endif /* USE_FULL_LL_DRIVER */
505
506 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
507 * @{
508 */
509 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
510 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
511 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
512 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
513 /**
514 * @}
515 */
516
517 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
518 * @{
519 */
520 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
521 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
522 /**
523 * @}
524 */
525
526 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
527 * @{
528 */
529 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
530 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
531 /**
532 * @}
533 */
534
535 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
536 * @{
537 */
538 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
539 is word */
540 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
541 is word */
542 /**
543 * @}
544 */
545
546 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
547 * @{
548 */
549 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
550 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
551 /**
552 * @}
553 */
554
555 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
556 * @{
557 */
558 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
559 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
560 /**
561 * @}
562 */
563
564 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
565 * @{
566 */
567 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
568 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
569 /**
570 * @}
571 */
572
573 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
574 * @{
575 */
576 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
577 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
578 /**
579 * @}
580 */
581
582 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
583 * @{
584 */
585 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
586 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
587 /**
588 * @}
589 */
590
591 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
592 * @{
593 */
594 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
595 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
596 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
597 /**
598 * @}
599 */
600
601 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
602 * @{
603 */
604 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
605 => Right Aligned padded with 0 up to destination
606 data width.
607 If src data width > dest data width :
608 => Right Aligned Left Truncated down to destination
609 data width. */
610 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
611 => Right Aligned padded with sign extended up to destination
612 data width.
613 If src data width > dest data width :
614 => Left Aligned Right Truncated down to the destination
615 data width */
616 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
617 => Packed at the destination data width
618 If src data width > dest data width :
619 => Unpacked at the destination data width */
620 /**
621 * @}
622 */
623
624 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
625 * @{
626 */
627 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
628 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
629 /**
630 * @}
631 */
632
633 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
634 * @{
635 */
636 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
637 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
638 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
639 /**
640 * @}
641 */
642
643 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
644 * @{
645 */
646 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
647 request/acknowledge protocol at a burst level */
648 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
649 request/acknowledge protocol at a block level */
650 /**
651 * @}
652 */
653
654 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
655 * @{
656 */
657 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
658 (respectively half) end of each block */
659 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
660 (respectively half) end of the repeated block */
661 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
662 (respectively half) end of each linked-list item */
663 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
664 (respectively half) end of the last linked-list item */
665 /**
666 * @}
667 */
668
669 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
670 * @{
671 */
672 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
673 Masked trigger event */
674 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
675 edge of the selected trigger event input */
676 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
677 edge of the selected trigger event input */
678 /**
679 * @}
680 */
681
682 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
683 * @{
684 */
685 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
686 one hit trigger */
687 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
688 one hit trigger */
689 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
690 one hit trigger */
691 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
692 one hit trigger */
693 /**
694 * @}
695 */
696
697 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
698 * @{
699 */
700 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
701 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
702 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
703 /**
704 * @}
705 */
706
707
708 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
709 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
710 * @{
711 */
712 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
713 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
714 /**
715 * @}
716 */
717
718 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
719 * @{
720 */
721 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
722 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
723 /**
724 * @}
725 */
726
727 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
728 * @{
729 */
730 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
731 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
732 /**
733 * @}
734 */
735 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
736
737 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
738 * @{
739 */
740 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
741
742 /**
743 * @}
744 */
745
746 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
747 * @{
748 */
749 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
750 available for all DMA channels */
751 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
752 available for all DMA channels */
753 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
754 available for all DMA channels */
755 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
756 available for all DMA channels */
757 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
758 available for all DMA channels */
759 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
760 available for all DMA channels */
761 /**
762 * @}
763 */
764
765 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
766 * @{
767 */
768 /* GPDMA1 Hardware Requests */
769 #define LL_GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */
770 #if defined (SPI1)
771 #define LL_GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */
772 #define LL_GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */
773 #endif /* SPI1 */
774 #define LL_GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */
775 #define LL_GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */
776 #if defined (I2C1)
777 #define LL_GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */
778 #define LL_GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */
779 #define LL_GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */
780 #endif /* I2C1 */
781 #define LL_GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */
782 #define LL_GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */
783 #define LL_GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */
784 #define LL_GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */
785 #define LL_GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */
786 #if defined (USART2)
787 #define LL_GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */
788 #define LL_GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */
789 #endif /* USART2 */
790 #define LL_GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */
791 #define LL_GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */
792 #if defined (SAI1)
793 #define LL_GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */
794 #define LL_GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */
795 #endif /* SAI1 */
796 #define LL_GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */
797 #define LL_GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */
798 #define LL_GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */
799 #define LL_GPDMA1_REQUEST_TIM1_CH4 22U /*!< GPDMA1 HW request is TIM1_CH4 */
800 #define LL_GPDMA1_REQUEST_TIM1_UP 23U /*!< GPDMA1 HW request is TIM1_UP */
801 #define LL_GPDMA1_REQUEST_TIM1_TRIG 24U /*!< GPDMA1 HW request is TIM1_TRIG */
802 #define LL_GPDMA1_REQUEST_TIM1_COM 25U /*!< GPDMA1 HW request is TIM1_COM */
803 #define LL_GPDMA1_REQUEST_TIM2_CH1 26U /*!< GPDMA1 HW request is TIM2_CH1 */
804 #define LL_GPDMA1_REQUEST_TIM2_CH2 27U /*!< GPDMA1 HW request is TIM2_CH2 */
805 #define LL_GPDMA1_REQUEST_TIM2_CH3 28U /*!< GPDMA1 HW request is TIM2_CH3 */
806 #define LL_GPDMA1_REQUEST_TIM2_CH4 29U /*!< GPDMA1 HW request is TIM2_CH4 */
807 #define LL_GPDMA1_REQUEST_TIM2_UP 30U /*!< GPDMA1 HW request is TIM2_UP */
808 #if defined (TIM3)
809 #define LL_GPDMA1_REQUEST_TIM3_CH1 31U /*!< GPDMA1 HW request is TIM3_CH1 */
810 #define LL_GPDMA1_REQUEST_TIM3_CH2 32U /*!< GPDMA1 HW request is TIM3_CH2 */
811 #define LL_GPDMA1_REQUEST_TIM3_CH3 33U /*!< GPDMA1 HW request is TIM3_CH3 */
812 #define LL_GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */
813 #define LL_GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */
814 #define LL_GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */
815 #endif /* TIM3 */
816 #define LL_GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */
817 #define LL_GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */
818 #if defined (TIM17)
819 #define LL_GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */
820 #define LL_GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */
821 #endif /* TIM17 */
822 #if defined (AES)
823 #define LL_GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */
824 #define LL_GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */
825 #endif /* AES */
826 #define LL_GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */
827 #if defined (SAES)
828 #define LL_GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */
829 #define LL_GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */
830 #endif /* SAES */
831 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */
832 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */
833 #define LL_GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */
834 #if defined (LPTIM2)
835 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */
836 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */
837 #define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */
838 #endif /* LPTIM2 */
839 /**
840 * @}
841 */
842
843 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
844 * @{
845 */
846 /* GPDMA1 Hardware Triggers */
847 #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
848 #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
849 #define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
850 #define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
851 #define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
852 #define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
853 #define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
854 #define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
855 #define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
856 #define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
857 #define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
858 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
859 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
860 #if defined (LPTIM2)
861 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
862 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
863 #endif /* LPTIM2 */
864 #if defined (COMP1)
865 #define LL_GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
866 #endif /* COMP1 */
867 #if defined (COMP2)
868 #define LL_GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */
869 #endif /* COMP2 */
870 #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
871 #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
872 #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
873 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
874 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
875 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
876 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
877 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
878 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
879 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
880 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
881 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 28U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
882 #define LL_GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */
883 #if defined (TIM3)
884 #define LL_GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
885 #endif /* TIM3 */
886 /**
887 * @}
888 */
889
890 /**
891 * @}
892 */
893
894 /* Exported macro ------------------------------------------------------------*/
895
896 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
897 * @{
898 */
899
900 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
901 * @{
902 */
903 /**
904 * @brief Write a value in DMA register.
905 * @param __INSTANCE__ DMA Instance.
906 * @param __REG__ Register to be written.
907 * @param __VALUE__ Value to be written in the register.
908 * @retval None.
909 */
910 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
911
912 /**
913 * @brief Read a value in DMA register.
914 * @param __INSTANCE__ DMA Instance.
915 * @param __REG__ Register to be read.
916 * @retval Register value.
917 */
918 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
919 /**
920 * @}
921 */
922
923 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
924 * @{
925 */
926 /**
927 * @brief Convert DMAx_Channely into DMAx.
928 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
929 * @retval DMAx.
930 */
931 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
932 (GPDMA1)
933
934 /**
935 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
936 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
937 * @retval LL_DMA_CHANNEL_y.
938 */
939 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
940 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
941 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
942 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
943 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
944 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
945 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
946 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
947 LL_DMA_CHANNEL_7)
948
949 /**
950 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
951 * @param __DMA_INSTANCE__ DMAx.
952 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
953 * @retval DMAx_Channely.
954 */
955 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
956 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
957 ? GPDMA1_Channel0 : \
958 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
959 ? GPDMA1_Channel1 : \
960 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
961 ? GPDMA1_Channel2 : \
962 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
963 ? GPDMA1_Channel3 : \
964 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
965 ? GPDMA1_Channel4 : \
966 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
967 ? GPDMA1_Channel5 : \
968 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
969 ? GPDMA1_Channel6 : GPDMA1_Channel7)
970
971 /**
972 * @}
973 */
974
975 /**
976 * @}
977 */
978
979 /* Exported functions --------------------------------------------------------*/
980
981 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
982 * @{
983 */
984
985 /** @defgroup DMA_LL_EF_Configuration Configuration
986 * @{
987 */
988 /**
989 * @brief Enable channel.
990 * @note This API is used for all available DMA channels.
991 * @rmtoll CCR EN LL_DMA_EnableChannel
992 * @param DMAx DMAx Instance.
993 * @param Channel This parameter can be one of the following values:
994 * @arg @ref LL_DMA_CHANNEL_0
995 * @arg @ref LL_DMA_CHANNEL_1
996 * @arg @ref LL_DMA_CHANNEL_2
997 * @arg @ref LL_DMA_CHANNEL_3
998 * @arg @ref LL_DMA_CHANNEL_4
999 * @arg @ref LL_DMA_CHANNEL_5
1000 * @arg @ref LL_DMA_CHANNEL_6
1001 * @arg @ref LL_DMA_CHANNEL_7
1002 * @retval None.
1003 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1004 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1005 {
1006 uint32_t dma_base_addr = (uint32_t)DMAx;
1007 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1008 }
1009
1010 /**
1011 * @brief Disable channel.
1012 * @note This API is used for all available DMA channels.
1013 * @rmtoll CCR EN LL_DMA_DisableChannel
1014 * @param DMAx DMAx Instance.
1015 * @param Channel This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_CHANNEL_0
1017 * @arg @ref LL_DMA_CHANNEL_1
1018 * @arg @ref LL_DMA_CHANNEL_2
1019 * @arg @ref LL_DMA_CHANNEL_3
1020 * @arg @ref LL_DMA_CHANNEL_4
1021 * @arg @ref LL_DMA_CHANNEL_5
1022 * @arg @ref LL_DMA_CHANNEL_6
1023 * @arg @ref LL_DMA_CHANNEL_7
1024 * @retval None.
1025 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1026 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1027 {
1028 uint32_t dma_base_addr = (uint32_t)DMAx;
1029 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1030 (DMA_CCR_SUSP | DMA_CCR_RESET));
1031 }
1032
1033 /**
1034 * @brief Check if channel is enabled or disabled.
1035 * @note This API is used for all available DMA channels.
1036 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1037 * @param DMAx DMAx Instance
1038 * @param Channel This parameter can be one of the following values:
1039 * @arg @ref LL_DMA_CHANNEL_0
1040 * @arg @ref LL_DMA_CHANNEL_1
1041 * @arg @ref LL_DMA_CHANNEL_2
1042 * @arg @ref LL_DMA_CHANNEL_3
1043 * @arg @ref LL_DMA_CHANNEL_4
1044 * @arg @ref LL_DMA_CHANNEL_5
1045 * @arg @ref LL_DMA_CHANNEL_6
1046 * @arg @ref LL_DMA_CHANNEL_7
1047 * @retval State of bit (1 or 0).
1048 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1049 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1050 {
1051 uint32_t dma_base_addr = (uint32_t)DMAx;
1052 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1053 == (DMA_CCR_EN)) ? 1UL : 0UL);
1054 }
1055
1056 /**
1057 * @brief Reset channel.
1058 * @note This API is used for all available DMA channels.
1059 * @rmtoll CCR RESET LL_DMA_ResetChannel
1060 * @param DMAx DMAx Instance
1061 * @param Channel This parameter can be one of the following values:
1062 * @arg @ref LL_DMA_CHANNEL_0
1063 * @arg @ref LL_DMA_CHANNEL_1
1064 * @arg @ref LL_DMA_CHANNEL_2
1065 * @arg @ref LL_DMA_CHANNEL_3
1066 * @arg @ref LL_DMA_CHANNEL_4
1067 * @arg @ref LL_DMA_CHANNEL_5
1068 * @arg @ref LL_DMA_CHANNEL_6
1069 * @arg @ref LL_DMA_CHANNEL_7
1070 * @retval None.
1071 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1072 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1073 {
1074 uint32_t dma_base_addr = (uint32_t)DMAx;
1075 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1076 }
1077
1078 /**
1079 * @brief Suspend channel.
1080 * @note This API is used for all available DMA channels.
1081 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1082 * @param DMAx DMAx Instance
1083 * @param Channel This parameter can be one of the following values:
1084 * @arg @ref LL_DMA_CHANNEL_0
1085 * @arg @ref LL_DMA_CHANNEL_1
1086 * @arg @ref LL_DMA_CHANNEL_2
1087 * @arg @ref LL_DMA_CHANNEL_3
1088 * @arg @ref LL_DMA_CHANNEL_4
1089 * @arg @ref LL_DMA_CHANNEL_5
1090 * @arg @ref LL_DMA_CHANNEL_6
1091 * @arg @ref LL_DMA_CHANNEL_7
1092 * @retval None.
1093 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1094 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1095 {
1096 uint32_t dma_base_addr = (uint32_t)DMAx;
1097 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1098 }
1099
1100 /**
1101 * @brief Resume channel.
1102 * @note This API is used for all available DMA channels.
1103 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1104 * @param DMAx DMAx Instance
1105 * @param Channel This parameter can be one of the following values:
1106 * @arg @ref LL_DMA_CHANNEL_0
1107 * @arg @ref LL_DMA_CHANNEL_1
1108 * @arg @ref LL_DMA_CHANNEL_2
1109 * @arg @ref LL_DMA_CHANNEL_3
1110 * @arg @ref LL_DMA_CHANNEL_4
1111 * @arg @ref LL_DMA_CHANNEL_5
1112 * @arg @ref LL_DMA_CHANNEL_6
1113 * @arg @ref LL_DMA_CHANNEL_7
1114 * @retval None.
1115 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1116 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1117 {
1118 uint32_t dma_base_addr = (uint32_t)DMAx;
1119 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1120 }
1121
1122 /**
1123 * @brief Check if channel is suspended.
1124 * @note This API is used for all available DMA channels.
1125 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1126 * @param DMAx DMAx Instance
1127 * @param Channel This parameter can be one of the following values:
1128 * @arg @ref LL_DMA_CHANNEL_0
1129 * @arg @ref LL_DMA_CHANNEL_1
1130 * @arg @ref LL_DMA_CHANNEL_2
1131 * @arg @ref LL_DMA_CHANNEL_3
1132 * @arg @ref LL_DMA_CHANNEL_4
1133 * @arg @ref LL_DMA_CHANNEL_5
1134 * @arg @ref LL_DMA_CHANNEL_6
1135 * @arg @ref LL_DMA_CHANNEL_7
1136 * @retval State of bit (1 or 0).
1137 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1138 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1139 {
1140 uint32_t dma_base_addr = (uint32_t)DMAx;
1141 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1142 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1143 }
1144
1145 /**
1146 * @brief Set linked-list base address.
1147 * @note This API is used for all available DMA channels.
1148 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1149 * @param DMAx DMAx Instance
1150 * @param Channel This parameter can be one of the following values:
1151 * @arg @ref LL_DMA_CHANNEL_0
1152 * @arg @ref LL_DMA_CHANNEL_1
1153 * @arg @ref LL_DMA_CHANNEL_2
1154 * @arg @ref LL_DMA_CHANNEL_3
1155 * @arg @ref LL_DMA_CHANNEL_4
1156 * @arg @ref LL_DMA_CHANNEL_5
1157 * @arg @ref LL_DMA_CHANNEL_6
1158 * @arg @ref LL_DMA_CHANNEL_7
1159 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1160 * are always 0)
1161 * @retval None.
1162 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1163 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
1164 uint32_t LinkedListBaseAddr)
1165 {
1166 uint32_t dma_base_addr = (uint32_t)DMAx;
1167 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1168 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1169 }
1170
1171 /**
1172 * @brief Get linked-list base address.
1173 * @note This API is used for all available DMA channels.
1174 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1175 * @param DMAx DMAx Instance
1176 * @param Channel This parameter can be one of the following values:
1177 * @arg @ref LL_DMA_CHANNEL_0
1178 * @arg @ref LL_DMA_CHANNEL_1
1179 * @arg @ref LL_DMA_CHANNEL_2
1180 * @arg @ref LL_DMA_CHANNEL_3
1181 * @arg @ref LL_DMA_CHANNEL_4
1182 * @arg @ref LL_DMA_CHANNEL_5
1183 * @arg @ref LL_DMA_CHANNEL_6
1184 * @arg @ref LL_DMA_CHANNEL_7
1185 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1186 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)1187 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
1188 {
1189 uint32_t dma_base_addr = (uint32_t)DMAx;
1190 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1191 }
1192
1193 /**
1194 * @brief Configure all parameters linked to channel control.
1195 * @note This API is used for all available DMA channels.
1196 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1197 * CCR LAP LL_DMA_ConfigControl\n
1198 * CCR LSM LL_DMA_ConfigControl
1199 * @param DMAx DMAx Instance
1200 * @param Channel This parameter can be one of the following values:
1201 * @arg @ref LL_DMA_CHANNEL_0
1202 * @arg @ref LL_DMA_CHANNEL_1
1203 * @arg @ref LL_DMA_CHANNEL_2
1204 * @arg @ref LL_DMA_CHANNEL_3
1205 * @arg @ref LL_DMA_CHANNEL_4
1206 * @arg @ref LL_DMA_CHANNEL_5
1207 * @arg @ref LL_DMA_CHANNEL_6
1208 * @arg @ref LL_DMA_CHANNEL_7
1209 * @param Configuration This parameter must be a combination of all the following values:
1210 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1211 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1212 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1213 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1214 *@retval None.
1215 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1216 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1217 {
1218 uint32_t dma_base_addr = (uint32_t)DMAx;
1219 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1220 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1221 }
1222
1223 /**
1224 * @brief Set priority level.
1225 * @note This API is used for all available DMA channels.
1226 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1227 * @param DMAx DMAx Instance
1228 * @param Channel This parameter can be one of the following values:
1229 * @arg @ref LL_DMA_CHANNEL_0
1230 * @arg @ref LL_DMA_CHANNEL_1
1231 * @arg @ref LL_DMA_CHANNEL_2
1232 * @arg @ref LL_DMA_CHANNEL_3
1233 * @arg @ref LL_DMA_CHANNEL_4
1234 * @arg @ref LL_DMA_CHANNEL_5
1235 * @arg @ref LL_DMA_CHANNEL_6
1236 * @arg @ref LL_DMA_CHANNEL_7
1237 * @param Priority This parameter can be one of the following values:
1238 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1239 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1240 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1241 * @arg @ref LL_DMA_HIGH_PRIORITY
1242 * @retval None.
1243 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1244 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1245 {
1246 uint32_t dma_base_addr = (uint32_t)DMAx;
1247 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1248 }
1249
1250 /**
1251 * @brief Get Channel priority level.
1252 * @note This API is used for all available DMA channels.
1253 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1254 * @param DMAx DMAx Instance
1255 * @param Channel This parameter can be one of the following values:
1256 * @arg @ref LL_DMA_CHANNEL_0
1257 * @arg @ref LL_DMA_CHANNEL_1
1258 * @arg @ref LL_DMA_CHANNEL_2
1259 * @arg @ref LL_DMA_CHANNEL_3
1260 * @arg @ref LL_DMA_CHANNEL_4
1261 * @arg @ref LL_DMA_CHANNEL_5
1262 * @arg @ref LL_DMA_CHANNEL_6
1263 * @arg @ref LL_DMA_CHANNEL_7
1264 * @retval Returned value can be one of the following values:
1265 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1266 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1267 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1268 * @arg @ref LL_DMA_HIGH_PRIORITY
1269 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)1270 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
1271 {
1272 uint32_t dma_base_addr = (uint32_t)DMAx;
1273 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
1274 }
1275
1276 /**
1277 * @brief Set linked-list allocated port.
1278 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
1279 * @param DMAx DMAx Instance
1280 * @param Channel This parameter can be one of the following values:
1281 * @arg @ref LL_DMA_CHANNEL_0
1282 * @arg @ref LL_DMA_CHANNEL_1
1283 * @arg @ref LL_DMA_CHANNEL_2
1284 * @arg @ref LL_DMA_CHANNEL_3
1285 * @arg @ref LL_DMA_CHANNEL_4
1286 * @arg @ref LL_DMA_CHANNEL_5
1287 * @arg @ref LL_DMA_CHANNEL_6
1288 * @arg @ref LL_DMA_CHANNEL_7
1289 * @param LinkAllocatedPort This parameter can be one of the following values:
1290 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1291 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1292 * @retval None.
1293 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)1294 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
1295 {
1296 uint32_t dma_base_addr = (uint32_t)DMAx;
1297 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1298 DMA_CCR_LAP, LinkAllocatedPort);
1299 }
1300
1301 /**
1302 * @brief Get linked-list allocated port.
1303 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
1304 * @param DMAx DMAx Instance
1305 * @param Channel This parameter can be one of the following values:
1306 * @arg @ref LL_DMA_CHANNEL_0
1307 * @arg @ref LL_DMA_CHANNEL_1
1308 * @arg @ref LL_DMA_CHANNEL_2
1309 * @arg @ref LL_DMA_CHANNEL_3
1310 * @arg @ref LL_DMA_CHANNEL_4
1311 * @arg @ref LL_DMA_CHANNEL_5
1312 * @arg @ref LL_DMA_CHANNEL_6
1313 * @arg @ref LL_DMA_CHANNEL_7
1314 * @retval Returned value can be one of the following values:
1315 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1316 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1317 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1318 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1319 {
1320 uint32_t dma_base_addr = (uint32_t)DMAx;
1321 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
1322 }
1323
1324 /**
1325 * @brief Set link step mode.
1326 * @note This API is used for all available DMA channels.
1327 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
1328 * @param DMAx DMAx Instance
1329 * @param Channel This parameter can be one of the following values:
1330 * @arg @ref LL_DMA_CHANNEL_0
1331 * @arg @ref LL_DMA_CHANNEL_1
1332 * @arg @ref LL_DMA_CHANNEL_2
1333 * @arg @ref LL_DMA_CHANNEL_3
1334 * @arg @ref LL_DMA_CHANNEL_4
1335 * @arg @ref LL_DMA_CHANNEL_5
1336 * @arg @ref LL_DMA_CHANNEL_6
1337 * @arg @ref LL_DMA_CHANNEL_7
1338 * @param LinkStepMode This parameter can be one of the following values:
1339 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1340 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1341 * @retval None.
1342 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)1343 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
1344 {
1345 uint32_t dma_base_addr = (uint32_t)DMAx;
1346 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
1347 }
1348
1349 /**
1350 * @brief Get Link step mode.
1351 * @note This API is used for all available DMA channels.
1352 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
1353 * @param DMAx DMAx Instance
1354 * @param Channel This parameter can be one of the following values:
1355 * @arg @ref LL_DMA_CHANNEL_0
1356 * @arg @ref LL_DMA_CHANNEL_1
1357 * @arg @ref LL_DMA_CHANNEL_2
1358 * @arg @ref LL_DMA_CHANNEL_3
1359 * @arg @ref LL_DMA_CHANNEL_4
1360 * @arg @ref LL_DMA_CHANNEL_5
1361 * @arg @ref LL_DMA_CHANNEL_6
1362 * @arg @ref LL_DMA_CHANNEL_7
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1365 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1366 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)1367 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1368 {
1369 uint32_t dma_base_addr = (uint32_t)DMAx;
1370 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
1371 }
1372
1373 /**
1374 * @brief Configure data transfer.
1375 * @note This API is used for all available DMA channels.
1376 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
1377 * CTR1 DHX LL_DMA_ConfigTransfer\n
1378 * CTR1 DBX LL_DMA_ConfigTransfer\n
1379 * CTR1 DINC LL_DMA_ConfigTransfer\n
1380 * CTR1 SAP LL_DMA_ConfigTransfer\n
1381 * CTR1 SBX LL_DMA_ConfigTransfer\n
1382 * CTR1 PAM LL_DMA_ConfigTransfer\n
1383 * CTR1 SINC LL_DMA_ConfigTransfer
1384 * @param DMAx DMAx Instance
1385 * @param Channel This parameter can be one of the following values:
1386 * @arg @ref LL_DMA_CHANNEL_0
1387 * @arg @ref LL_DMA_CHANNEL_1
1388 * @arg @ref LL_DMA_CHANNEL_2
1389 * @arg @ref LL_DMA_CHANNEL_3
1390 * @arg @ref LL_DMA_CHANNEL_4
1391 * @arg @ref LL_DMA_CHANNEL_5
1392 * @arg @ref LL_DMA_CHANNEL_6
1393 * @arg @ref LL_DMA_CHANNEL_7
1394 * @param Configuration This parameter must be a combination of all the following values:
1395 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
1396 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1397 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
1398 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
1399 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
1400 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
1401 * @ref LL_DMA_DEST_DATAWIDTH_WORD
1402 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
1403 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
1404 * @ref LL_DMA_DATA_PACK_UNPACK
1405 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
1406 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
1407 * @ref LL_DMA_SRC_DATAWIDTH_WORD
1408 *@retval None.
1409 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1410 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1411 {
1412 uint32_t dma_base_addr = (uint32_t)DMAx;
1413 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1414 DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
1415 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
1416 }
1417
1418 /**
1419 * @brief Configure source and destination burst length.
1420 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
1421 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
1422 * @param DMAx DMAx Instance
1423 * @param Channel This parameter can be one of the following values:
1424 * @arg @ref LL_DMA_CHANNEL_0
1425 * @arg @ref LL_DMA_CHANNEL_1
1426 * @arg @ref LL_DMA_CHANNEL_2
1427 * @arg @ref LL_DMA_CHANNEL_3
1428 * @arg @ref LL_DMA_CHANNEL_4
1429 * @arg @ref LL_DMA_CHANNEL_5
1430 * @arg @ref LL_DMA_CHANNEL_6
1431 * @arg @ref LL_DMA_CHANNEL_7
1432 * @param SrcBurstLength Between 1 to 64
1433 * @param DestBurstLength Between 1 to 64
1434 * @retval None.
1435 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)1436 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
1437 uint32_t DestBurstLength)
1438 {
1439 uint32_t dma_base_addr = (uint32_t)DMAx;
1440 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1441 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
1442 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
1443 }
1444
1445 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1446 /**
1447 * @brief Configure all secure parameters linked to DMA channel.
1448 * @note This API is used for all available DMA channels.
1449 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
1450 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
1451 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
1452 * @param DMAx DMAx Instance
1453 * @param Channel This parameter can be one of the following values:
1454 * @arg @ref LL_DMA_CHANNEL_0
1455 * @arg @ref LL_DMA_CHANNEL_1
1456 * @arg @ref LL_DMA_CHANNEL_2
1457 * @arg @ref LL_DMA_CHANNEL_3
1458 * @arg @ref LL_DMA_CHANNEL_4
1459 * @arg @ref LL_DMA_CHANNEL_5
1460 * @arg @ref LL_DMA_CHANNEL_6
1461 * @arg @ref LL_DMA_CHANNEL_7
1462 * @param Configuration This parameter must be a combination of all the following values:
1463 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
1464 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
1465 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
1466 * @retval None.
1467 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1468 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1469 {
1470 uint32_t dma_base_addr = (uint32_t)DMAx;
1471 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
1472 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1473 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
1474 }
1475
1476 /**
1477 * @brief Enable security attribute of the DMA transfer to the destination.
1478 * @note This API is used for all available DMA channels.
1479 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
1480 * @param DMAx DMAx Instance
1481 * @param Channel This parameter can be one of the following values:
1482 * @arg @ref LL_DMA_CHANNEL_0
1483 * @arg @ref LL_DMA_CHANNEL_1
1484 * @arg @ref LL_DMA_CHANNEL_2
1485 * @arg @ref LL_DMA_CHANNEL_3
1486 * @arg @ref LL_DMA_CHANNEL_4
1487 * @arg @ref LL_DMA_CHANNEL_5
1488 * @arg @ref LL_DMA_CHANNEL_6
1489 * @arg @ref LL_DMA_CHANNEL_7
1490 * @retval None.
1491 */
LL_DMA_EnableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1492 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1493 {
1494 uint32_t dma_base_addr = (uint32_t)DMAx;
1495 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
1496 }
1497
1498 /**
1499 * @brief Disable security attribute of the DMA transfer to the destination.
1500 * @note This API is used for all available DMA channels.
1501 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
1502 * @param DMAx DMAx Instance
1503 * @param Channel This parameter can be one of the following values:
1504 * @arg @ref LL_DMA_CHANNEL_0
1505 * @arg @ref LL_DMA_CHANNEL_1
1506 * @arg @ref LL_DMA_CHANNEL_2
1507 * @arg @ref LL_DMA_CHANNEL_3
1508 * @arg @ref LL_DMA_CHANNEL_4
1509 * @arg @ref LL_DMA_CHANNEL_5
1510 * @arg @ref LL_DMA_CHANNEL_6
1511 * @arg @ref LL_DMA_CHANNEL_7
1512 * @retval None.
1513 */
LL_DMA_DisableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1514 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1515 {
1516 uint32_t dma_base_addr = (uint32_t)DMAx;
1517 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
1518 }
1519 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1520
1521 #if defined (DMA_SECCFGR_SEC0)
1522 /**
1523 * @brief Check security attribute of the DMA transfer to the destination.
1524 * @note This API is used for all available DMA channels.
1525 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
1526 * @param DMAx DMAx Instance
1527 * @param Channel This parameter can be one of the following values:
1528 * @arg @ref LL_DMA_CHANNEL_0
1529 * @arg @ref LL_DMA_CHANNEL_1
1530 * @arg @ref LL_DMA_CHANNEL_2
1531 * @arg @ref LL_DMA_CHANNEL_3
1532 * @arg @ref LL_DMA_CHANNEL_4
1533 * @arg @ref LL_DMA_CHANNEL_5
1534 * @arg @ref LL_DMA_CHANNEL_6
1535 * @arg @ref LL_DMA_CHANNEL_7
1536 * @retval State of bit (1 or 0).
1537 */
LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1538 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1539 {
1540 uint32_t dma_base_addr = (uint32_t)DMAx;
1541 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
1542 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
1543 }
1544 #endif /* DMA_SECCFGR_SEC0 */
1545
1546 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1547 /**
1548 * @brief Enable security attribute of the DMA transfer from the source.
1549 * @note This API is used for all available DMA channels.
1550 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
1551 * @param DMAx DMAx Instance
1552 * @param Channel This parameter can be one of the following values:
1553 * @arg @ref LL_DMA_CHANNEL_0
1554 * @arg @ref LL_DMA_CHANNEL_1
1555 * @arg @ref LL_DMA_CHANNEL_2
1556 * @arg @ref LL_DMA_CHANNEL_3
1557 * @arg @ref LL_DMA_CHANNEL_4
1558 * @arg @ref LL_DMA_CHANNEL_5
1559 * @arg @ref LL_DMA_CHANNEL_6
1560 * @arg @ref LL_DMA_CHANNEL_7
1561 * @retval None.
1562 */
LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1563 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1564 {
1565 uint32_t dma_base_addr = (uint32_t)DMAx;
1566 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
1567 }
1568
1569 /**
1570 * @brief Disable security attribute of the DMA transfer from the source.
1571 * @note This API is used for all available DMA channels.
1572 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
1573 * @param DMAx DMAx Instance
1574 * @param Channel This parameter can be one of the following values:
1575 * @arg @ref LL_DMA_CHANNEL_0
1576 * @arg @ref LL_DMA_CHANNEL_1
1577 * @arg @ref LL_DMA_CHANNEL_2
1578 * @arg @ref LL_DMA_CHANNEL_3
1579 * @arg @ref LL_DMA_CHANNEL_4
1580 * @arg @ref LL_DMA_CHANNEL_5
1581 * @arg @ref LL_DMA_CHANNEL_6
1582 * @arg @ref LL_DMA_CHANNEL_7
1583 * @retval None.
1584 */
LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1585 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1586 {
1587 uint32_t dma_base_addr = (uint32_t)DMAx;
1588 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
1589 }
1590 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1591
1592 #if defined (DMA_SECCFGR_SEC0)
1593 /**
1594 * @brief Check security attribute of the DMA transfer from the source.
1595 * @note This API is used for all available DMA channels.
1596 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
1597 * @param DMAx DMAx Instance
1598 * @param Channel This parameter can be one of the following values:
1599 * @arg @ref LL_DMA_CHANNEL_0
1600 * @arg @ref LL_DMA_CHANNEL_1
1601 * @arg @ref LL_DMA_CHANNEL_2
1602 * @arg @ref LL_DMA_CHANNEL_3
1603 * @arg @ref LL_DMA_CHANNEL_4
1604 * @arg @ref LL_DMA_CHANNEL_5
1605 * @arg @ref LL_DMA_CHANNEL_6
1606 * @arg @ref LL_DMA_CHANNEL_7
1607 * @retval State of bit (1 or 0).
1608 */
LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1609 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1610 {
1611 uint32_t dma_base_addr = (uint32_t)DMAx;
1612 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
1613 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
1614 }
1615 #endif /* DMA_SECCFGR_SEC0 */
1616
1617 /**
1618 * @brief Set destination allocated port.
1619 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
1620 * @param DMAx DMAx Instance
1621 * @param Channel This parameter can be one of the following values:
1622 * @arg @ref LL_DMA_CHANNEL_0
1623 * @arg @ref LL_DMA_CHANNEL_1
1624 * @arg @ref LL_DMA_CHANNEL_2
1625 * @arg @ref LL_DMA_CHANNEL_3
1626 * @arg @ref LL_DMA_CHANNEL_4
1627 * @arg @ref LL_DMA_CHANNEL_5
1628 * @arg @ref LL_DMA_CHANNEL_6
1629 * @arg @ref LL_DMA_CHANNEL_7
1630 * @param DestAllocatedPort This parameter can be one of the following values:
1631 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
1632 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
1633 * @retval None.
1634 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)1635 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
1636 {
1637 uint32_t dma_base_addr = (uint32_t)DMAx;
1638 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
1639 DestAllocatedPort);
1640 }
1641
1642 /**
1643 * @brief Get destination allocated port.
1644 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
1645 * @param DMAx DMAx Instance
1646 * @param Channel This parameter can be one of the following values:
1647 * @arg @ref LL_DMA_CHANNEL_0
1648 * @arg @ref LL_DMA_CHANNEL_1
1649 * @arg @ref LL_DMA_CHANNEL_2
1650 * @arg @ref LL_DMA_CHANNEL_3
1651 * @arg @ref LL_DMA_CHANNEL_4
1652 * @arg @ref LL_DMA_CHANNEL_5
1653 * @arg @ref LL_DMA_CHANNEL_6
1654 * @arg @ref LL_DMA_CHANNEL_7
1655 * @retval Returned value can be one of the following values:
1656 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
1657 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
1658 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1659 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1660 {
1661 uint32_t dma_base_addr = (uint32_t)DMAx;
1662 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
1663 }
1664
1665 /**
1666 * @brief Set destination half-word exchange.
1667 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
1668 * @param DMAx DMAx Instance
1669 * @param Channel This parameter can be one of the following values:
1670 * @arg @ref LL_DMA_CHANNEL_0
1671 * @arg @ref LL_DMA_CHANNEL_1
1672 * @arg @ref LL_DMA_CHANNEL_2
1673 * @arg @ref LL_DMA_CHANNEL_3
1674 * @arg @ref LL_DMA_CHANNEL_4
1675 * @arg @ref LL_DMA_CHANNEL_5
1676 * @arg @ref LL_DMA_CHANNEL_6
1677 * @arg @ref LL_DMA_CHANNEL_7
1678 * @param DestHWordExchange This parameter can be one of the following values:
1679 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
1680 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1681 * @retval None.
1682 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)1683 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
1684 {
1685 uint32_t dma_base_addr = (uint32_t)DMAx;
1686 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
1687 DestHWordExchange);
1688 }
1689
1690 /**
1691 * @brief Get destination half-word exchange.
1692 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
1693 * @param DMAx DMAx Instance
1694 * @param Channel This parameter can be one of the following values:
1695 * @arg @ref LL_DMA_CHANNEL_0
1696 * @arg @ref LL_DMA_CHANNEL_1
1697 * @arg @ref LL_DMA_CHANNEL_2
1698 * @arg @ref LL_DMA_CHANNEL_3
1699 * @arg @ref LL_DMA_CHANNEL_4
1700 * @arg @ref LL_DMA_CHANNEL_5
1701 * @arg @ref LL_DMA_CHANNEL_6
1702 * @arg @ref LL_DMA_CHANNEL_7
1703 * @retval Returned value can be one of the following values:
1704 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
1705 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1706 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1707 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1708 {
1709 uint32_t dma_base_addr = (uint32_t)DMAx;
1710 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
1711 }
1712
1713 /**
1714 * @brief Set destination byte exchange.
1715 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
1716 * @param DMAx DMAx Instance
1717 * @param Channel This parameter can be one of the following values:
1718 * @arg @ref LL_DMA_CHANNEL_0
1719 * @arg @ref LL_DMA_CHANNEL_1
1720 * @arg @ref LL_DMA_CHANNEL_2
1721 * @arg @ref LL_DMA_CHANNEL_3
1722 * @arg @ref LL_DMA_CHANNEL_4
1723 * @arg @ref LL_DMA_CHANNEL_5
1724 * @arg @ref LL_DMA_CHANNEL_6
1725 * @arg @ref LL_DMA_CHANNEL_7
1726 * @param DestByteExchange This parameter can be one of the following values:
1727 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
1728 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
1729 * @retval None.
1730 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)1731 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
1732 {
1733 uint32_t dma_base_addr = (uint32_t)DMAx;
1734 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
1735 DestByteExchange);
1736 }
1737
1738 /**
1739 * @brief Get destination byte exchange.
1740 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
1741 * @param DMAx DMAx Instance
1742 * @param Channel This parameter can be one of the following values:
1743 * @arg @ref LL_DMA_CHANNEL_0
1744 * @arg @ref LL_DMA_CHANNEL_1
1745 * @arg @ref LL_DMA_CHANNEL_2
1746 * @arg @ref LL_DMA_CHANNEL_3
1747 * @arg @ref LL_DMA_CHANNEL_4
1748 * @arg @ref LL_DMA_CHANNEL_5
1749 * @arg @ref LL_DMA_CHANNEL_6
1750 * @arg @ref LL_DMA_CHANNEL_7
1751 * @retval Returned value can be one of the following values:
1752 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
1753 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
1754 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1755 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1756 {
1757 uint32_t dma_base_addr = (uint32_t)DMAx;
1758 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
1759 }
1760
1761 /**
1762 * @brief Set source byte exchange.
1763 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
1764 * @param DMAx DMAx Instance
1765 * @param Channel This parameter can be one of the following values:
1766 * @arg @ref LL_DMA_CHANNEL_0
1767 * @arg @ref LL_DMA_CHANNEL_1
1768 * @arg @ref LL_DMA_CHANNEL_2
1769 * @arg @ref LL_DMA_CHANNEL_3
1770 * @arg @ref LL_DMA_CHANNEL_4
1771 * @arg @ref LL_DMA_CHANNEL_5
1772 * @arg @ref LL_DMA_CHANNEL_6
1773 * @arg @ref LL_DMA_CHANNEL_7
1774 * @param SrcByteExchange This parameter can be one of the following values:
1775 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
1776 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
1777 * @retval None.
1778 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)1779 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
1780 {
1781 uint32_t dma_base_addr = (uint32_t)DMAx;
1782 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
1783 SrcByteExchange);
1784 }
1785
1786 /**
1787 * @brief Get source byte exchange.
1788 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
1789 * @param DMAx DMAx Instance
1790 * @param Channel This parameter can be one of the following values:
1791 * @arg @ref LL_DMA_CHANNEL_0
1792 * @arg @ref LL_DMA_CHANNEL_1
1793 * @arg @ref LL_DMA_CHANNEL_2
1794 * @arg @ref LL_DMA_CHANNEL_3
1795 * @arg @ref LL_DMA_CHANNEL_4
1796 * @arg @ref LL_DMA_CHANNEL_5
1797 * @arg @ref LL_DMA_CHANNEL_6
1798 * @arg @ref LL_DMA_CHANNEL_7
1799 * @retval Returned value can be one of the following values:
1800 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
1801 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
1802 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1803 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1804 {
1805 uint32_t dma_base_addr = (uint32_t)DMAx;
1806 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
1807 }
1808
1809 /**
1810 * @brief Set destination burst length.
1811 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
1812 * @param DMAx DMAx Instance
1813 * @param Channel This parameter can be one of the following values:
1814 * @arg @ref LL_DMA_CHANNEL_0
1815 * @arg @ref LL_DMA_CHANNEL_1
1816 * @arg @ref LL_DMA_CHANNEL_2
1817 * @arg @ref LL_DMA_CHANNEL_3
1818 * @arg @ref LL_DMA_CHANNEL_4
1819 * @arg @ref LL_DMA_CHANNEL_5
1820 * @arg @ref LL_DMA_CHANNEL_6
1821 * @arg @ref LL_DMA_CHANNEL_7
1822 * @param DestBurstLength Between 1 to 64
1823 * @retval None.
1824 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)1825 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
1826 {
1827 uint32_t dma_base_addr = (uint32_t)DMAx;
1828 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
1829 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
1830 }
1831
1832 /**
1833 * @brief Get destination burst length.
1834 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
1835 * @param DMAx DMAx Instance
1836 * @param Channel This parameter can be one of the following values:
1837 * @arg @ref LL_DMA_CHANNEL_0
1838 * @arg @ref LL_DMA_CHANNEL_1
1839 * @arg @ref LL_DMA_CHANNEL_2
1840 * @arg @ref LL_DMA_CHANNEL_3
1841 * @arg @ref LL_DMA_CHANNEL_4
1842 * @arg @ref LL_DMA_CHANNEL_5
1843 * @arg @ref LL_DMA_CHANNEL_6
1844 * @arg @ref LL_DMA_CHANNEL_7
1845 * @retval Between 1 to 64.
1846 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)1847 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
1848 {
1849 uint32_t dma_base_addr = (uint32_t)DMAx;
1850 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1851 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
1852 }
1853
1854 /**
1855 * @brief Set destination increment mode.
1856 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
1857 * @param DMAx DMAx Instance
1858 * @param Channel This parameter can be one of the following values:
1859 * @arg @ref LL_DMA_CHANNEL_0
1860 * @arg @ref LL_DMA_CHANNEL_1
1861 * @arg @ref LL_DMA_CHANNEL_2
1862 * @arg @ref LL_DMA_CHANNEL_3
1863 * @arg @ref LL_DMA_CHANNEL_4
1864 * @arg @ref LL_DMA_CHANNEL_5
1865 * @arg @ref LL_DMA_CHANNEL_6
1866 * @arg @ref LL_DMA_CHANNEL_7
1867 * @param DestInc This parameter can be one of the following values:
1868 * @arg @ref LL_DMA_DEST_FIXED
1869 * @arg @ref LL_DMA_DEST_INCREMENT
1870 * @retval None.
1871 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)1872 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
1873 {
1874 uint32_t dma_base_addr = (uint32_t)DMAx;
1875 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
1876 }
1877 /**
1878 * @brief Get destination increment mode.
1879 * @note This API is used for all available DMA channels.
1880 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
1881 * @param DMAx DMAx Instance
1882 * @param Channel This parameter can be one of the following values:
1883 * @arg @ref LL_DMA_CHANNEL_0
1884 * @arg @ref LL_DMA_CHANNEL_1
1885 * @arg @ref LL_DMA_CHANNEL_2
1886 * @arg @ref LL_DMA_CHANNEL_3
1887 * @arg @ref LL_DMA_CHANNEL_4
1888 * @arg @ref LL_DMA_CHANNEL_5
1889 * @arg @ref LL_DMA_CHANNEL_6
1890 * @arg @ref LL_DMA_CHANNEL_7
1891 * @retval Returned value can be one of the following values:
1892 * @arg @ref LL_DMA_DEST_FIXED
1893 * @arg @ref LL_DMA_DEST_INCREMENT
1894 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)1895 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1896 {
1897 uint32_t dma_base_addr = (uint32_t)DMAx;
1898 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
1899 }
1900
1901 /**
1902 * @brief Set destination data width.
1903 * @note This API is used for all available DMA channels.
1904 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
1905 * @param DMAx DMAx Instance
1906 * @param Channel This parameter can be one of the following values:
1907 * @arg @ref LL_DMA_CHANNEL_0
1908 * @arg @ref LL_DMA_CHANNEL_1
1909 * @arg @ref LL_DMA_CHANNEL_2
1910 * @arg @ref LL_DMA_CHANNEL_3
1911 * @arg @ref LL_DMA_CHANNEL_4
1912 * @arg @ref LL_DMA_CHANNEL_5
1913 * @arg @ref LL_DMA_CHANNEL_6
1914 * @arg @ref LL_DMA_CHANNEL_7
1915 * @param DestDataWidth This parameter can be one of the following values:
1916 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
1917 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
1918 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
1919 * @retval None.
1920 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)1921 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
1922 {
1923 uint32_t dma_base_addr = (uint32_t)DMAx;
1924 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
1925 DestDataWidth);
1926 }
1927
1928 /**
1929 * @brief Get destination data width.
1930 * @note This API is used for all available DMA channels.
1931 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
1932 * @param DMAx DMAx Instance
1933 * @param Channel This parameter can be one of the following values:
1934 * @arg @ref LL_DMA_CHANNEL_0
1935 * @arg @ref LL_DMA_CHANNEL_1
1936 * @arg @ref LL_DMA_CHANNEL_2
1937 * @arg @ref LL_DMA_CHANNEL_3
1938 * @arg @ref LL_DMA_CHANNEL_4
1939 * @arg @ref LL_DMA_CHANNEL_5
1940 * @arg @ref LL_DMA_CHANNEL_6
1941 * @arg @ref LL_DMA_CHANNEL_7
1942 * @retval Returned value can be one of the following values:
1943 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
1944 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
1945 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
1946 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)1947 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
1948 {
1949 uint32_t dma_base_addr = (uint32_t)DMAx;
1950 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
1951 }
1952
1953 /**
1954 * @brief Set source allocated port.
1955 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
1956 * @param DMAx DMAx Instance
1957 * @param Channel This parameter can be one of the following values:
1958 * @arg @ref LL_DMA_CHANNEL_0
1959 * @arg @ref LL_DMA_CHANNEL_1
1960 * @arg @ref LL_DMA_CHANNEL_2
1961 * @arg @ref LL_DMA_CHANNEL_3
1962 * @arg @ref LL_DMA_CHANNEL_4
1963 * @arg @ref LL_DMA_CHANNEL_5
1964 * @arg @ref LL_DMA_CHANNEL_6
1965 * @arg @ref LL_DMA_CHANNEL_7
1966 * @param SrcAllocatedPort This parameter can be one of the following values:
1967 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
1968 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
1969 * @retval None.
1970 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)1971 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
1972 {
1973 uint32_t dma_base_addr = (uint32_t)DMAx;
1974 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
1975 SrcAllocatedPort);
1976 }
1977
1978 /**
1979 * @brief Get source allocated port.
1980 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
1981 * @param DMAx DMAx Instance
1982 * @param Channel This parameter can be one of the following values:
1983 * @arg @ref LL_DMA_CHANNEL_0
1984 * @arg @ref LL_DMA_CHANNEL_1
1985 * @arg @ref LL_DMA_CHANNEL_2
1986 * @arg @ref LL_DMA_CHANNEL_3
1987 * @arg @ref LL_DMA_CHANNEL_4
1988 * @arg @ref LL_DMA_CHANNEL_5
1989 * @arg @ref LL_DMA_CHANNEL_6
1990 * @arg @ref LL_DMA_CHANNEL_7
1991 * @retval Returned value can be one of the following values:
1992 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
1993 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
1994 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1995 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1996 {
1997 uint32_t dma_base_addr = (uint32_t)DMAx;
1998 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
1999 }
2000
2001 /**
2002 * @brief Set data alignment mode.
2003 * @note This API is used for all available DMA channels.
2004 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2005 * @param DMAx DMAx Instance
2006 * @param Channel This parameter can be one of the following values:
2007 * @arg @ref LL_DMA_CHANNEL_0
2008 * @arg @ref LL_DMA_CHANNEL_1
2009 * @arg @ref LL_DMA_CHANNEL_2
2010 * @arg @ref LL_DMA_CHANNEL_3
2011 * @arg @ref LL_DMA_CHANNEL_4
2012 * @arg @ref LL_DMA_CHANNEL_5
2013 * @arg @ref LL_DMA_CHANNEL_6
2014 * @arg @ref LL_DMA_CHANNEL_7
2015 * @param DataAlignment This parameter can be one of the following values:
2016 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2017 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2018 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2019 * @retval None.
2020 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)2021 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
2022 {
2023 uint32_t dma_base_addr = (uint32_t)DMAx;
2024 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
2025 DataAlignment);
2026 }
2027
2028 /**
2029 * @brief Get data alignment mode.
2030 * @note This API is used for all available DMA channels.
2031 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
2032 * @param DMAx DMAx Instance
2033 * @param Channel This parameter can be one of the following values:
2034 * @arg @ref LL_DMA_CHANNEL_0
2035 * @arg @ref LL_DMA_CHANNEL_1
2036 * @arg @ref LL_DMA_CHANNEL_2
2037 * @arg @ref LL_DMA_CHANNEL_3
2038 * @arg @ref LL_DMA_CHANNEL_4
2039 * @arg @ref LL_DMA_CHANNEL_5
2040 * @arg @ref LL_DMA_CHANNEL_6
2041 * @arg @ref LL_DMA_CHANNEL_7
2042 * @retval Returned value can be one of the following values:
2043 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2044 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2045 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2046 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)2047 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
2048 {
2049 uint32_t dma_base_addr = (uint32_t)DMAx;
2050 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
2051 }
2052
2053 /**
2054 * @brief Set source burst length.
2055 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
2056 * @param DMAx DMAx Instance
2057 * @param Channel This parameter can be one of the following values:
2058 * @arg @ref LL_DMA_CHANNEL_0
2059 * @arg @ref LL_DMA_CHANNEL_1
2060 * @arg @ref LL_DMA_CHANNEL_2
2061 * @arg @ref LL_DMA_CHANNEL_3
2062 * @arg @ref LL_DMA_CHANNEL_4
2063 * @arg @ref LL_DMA_CHANNEL_5
2064 * @arg @ref LL_DMA_CHANNEL_6
2065 * @arg @ref LL_DMA_CHANNEL_7
2066 * @param SrcBurstLength Between 1 to 64
2067 * @retval None.
2068 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)2069 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
2070 {
2071 uint32_t dma_base_addr = (uint32_t)DMAx;
2072 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
2073 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
2074 }
2075
2076 /**
2077 * @brief Get source burst length.
2078 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
2079 * @param DMAx DMAx Instance
2080 * @param Channel This parameter can be one of the following values:
2081 * @arg @ref LL_DMA_CHANNEL_0
2082 * @arg @ref LL_DMA_CHANNEL_1
2083 * @arg @ref LL_DMA_CHANNEL_2
2084 * @arg @ref LL_DMA_CHANNEL_3
2085 * @arg @ref LL_DMA_CHANNEL_4
2086 * @arg @ref LL_DMA_CHANNEL_5
2087 * @arg @ref LL_DMA_CHANNEL_6
2088 * @arg @ref LL_DMA_CHANNEL_7
2089 * @retval Between 1 to 64
2090 * @retval None.
2091 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2092 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2093 {
2094 uint32_t dma_base_addr = (uint32_t)DMAx;
2095 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2096 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
2097 }
2098
2099 /**
2100 * @brief Set source increment mode.
2101 * @note This API is used for all available DMA channels.
2102 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
2103 * @param DMAx DMAx Instance
2104 * @param Channel This parameter can be one of the following values:
2105 * @arg @ref LL_DMA_CHANNEL_0
2106 * @arg @ref LL_DMA_CHANNEL_1
2107 * @arg @ref LL_DMA_CHANNEL_2
2108 * @arg @ref LL_DMA_CHANNEL_3
2109 * @arg @ref LL_DMA_CHANNEL_4
2110 * @arg @ref LL_DMA_CHANNEL_5
2111 * @arg @ref LL_DMA_CHANNEL_6
2112 * @arg @ref LL_DMA_CHANNEL_7
2113 * @param SrcInc This parameter can be one of the following values:
2114 * @arg @ref LL_DMA_SRC_FIXED
2115 * @arg @ref LL_DMA_SRC_INCREMENT
2116 * @retval None.
2117 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)2118 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
2119 {
2120 uint32_t dma_base_addr = (uint32_t)DMAx;
2121 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
2122 }
2123
2124 /**
2125 * @brief Get source increment mode.
2126 * @note This API is used for all available DMA channels.
2127 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
2128 * @param DMAx DMAx Instance
2129 * @param Channel This parameter can be one of the following values:
2130 * @arg @ref LL_DMA_CHANNEL_0
2131 * @arg @ref LL_DMA_CHANNEL_1
2132 * @arg @ref LL_DMA_CHANNEL_2
2133 * @arg @ref LL_DMA_CHANNEL_3
2134 * @arg @ref LL_DMA_CHANNEL_4
2135 * @arg @ref LL_DMA_CHANNEL_5
2136 * @arg @ref LL_DMA_CHANNEL_6
2137 * @arg @ref LL_DMA_CHANNEL_7
2138 * @retval Returned value can be one of the following values:
2139 * @arg @ref LL_DMA_SRC_FIXED
2140 * @arg @ref LL_DMA_SRC_INCREMENT
2141 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2142 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2143 {
2144 uint32_t dma_base_addr = (uint32_t)DMAx;
2145 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
2146 }
2147
2148 /**
2149 * @brief Set source data width.
2150 * @note This API is used for all available DMA channels.
2151 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
2152 * @param DMAx DMAx Instance
2153 * @param Channel This parameter can be one of the following values:
2154 * @arg @ref LL_DMA_CHANNEL_0
2155 * @arg @ref LL_DMA_CHANNEL_1
2156 * @arg @ref LL_DMA_CHANNEL_2
2157 * @arg @ref LL_DMA_CHANNEL_3
2158 * @arg @ref LL_DMA_CHANNEL_4
2159 * @arg @ref LL_DMA_CHANNEL_5
2160 * @arg @ref LL_DMA_CHANNEL_6
2161 * @arg @ref LL_DMA_CHANNEL_7
2162 * @param SrcDataWidth This parameter can be one of the following values:
2163 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2164 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2165 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2166 * @retval None.
2167 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)2168 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
2169 {
2170 uint32_t dma_base_addr = (uint32_t)DMAx;
2171 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
2172 SrcDataWidth);
2173 }
2174
2175 /**
2176 * @brief Get Source Data width.
2177 * @note This API is used for all available DMA channels.
2178 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
2179 * @param DMAx DMAx Instance
2180 * @param Channel This parameter can be one of the following values:
2181 * @arg @ref LL_DMA_CHANNEL_0
2182 * @arg @ref LL_DMA_CHANNEL_1
2183 * @arg @ref LL_DMA_CHANNEL_2
2184 * @arg @ref LL_DMA_CHANNEL_3
2185 * @arg @ref LL_DMA_CHANNEL_4
2186 * @arg @ref LL_DMA_CHANNEL_5
2187 * @arg @ref LL_DMA_CHANNEL_6
2188 * @arg @ref LL_DMA_CHANNEL_7
2189 * @retval Returned value can be one of the following values:
2190 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2191 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2192 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2193 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2194 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2195 {
2196 uint32_t dma_base_addr = (uint32_t)DMAx;
2197 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
2198 }
2199
2200 /**
2201 * @brief Configure channel transfer.
2202 * @note This API is used for all available DMA channels.
2203 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
2204 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
2205 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
2206 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
2207 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
2208 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer
2209 * @param DMAx DMAx Instance
2210 * @param Channel This parameter can be one of the following values:
2211 * @arg @ref LL_DMA_CHANNEL_0
2212 * @arg @ref LL_DMA_CHANNEL_1
2213 * @arg @ref LL_DMA_CHANNEL_2
2214 * @arg @ref LL_DMA_CHANNEL_3
2215 * @arg @ref LL_DMA_CHANNEL_4
2216 * @arg @ref LL_DMA_CHANNEL_5
2217 * @arg @ref LL_DMA_CHANNEL_6
2218 * @arg @ref LL_DMA_CHANNEL_7
2219 * @param Configuration This parameter must be a combination of all the following values:
2220 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
2221 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2222 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
2223 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
2224 * @ref LL_DMA_TRIG_POLARITY_FALLING
2225 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
2226 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2227 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
2228 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2229 *@retval None.
2230 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2231 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2232 {
2233 uint32_t dma_base_addr = (uint32_t)DMAx;
2234 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2235 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
2236 Configuration);
2237 }
2238
2239 /**
2240 * @brief Set transfer event mode.
2241 * @note This API is used for all available DMA channels.
2242 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
2243 * @param DMAx DMAx Instance
2244 * @param Channel This parameter can be one of the following values:
2245 * @arg @ref LL_DMA_CHANNEL_0
2246 * @arg @ref LL_DMA_CHANNEL_1
2247 * @arg @ref LL_DMA_CHANNEL_2
2248 * @arg @ref LL_DMA_CHANNEL_3
2249 * @arg @ref LL_DMA_CHANNEL_4
2250 * @arg @ref LL_DMA_CHANNEL_5
2251 * @arg @ref LL_DMA_CHANNEL_6
2252 * @arg @ref LL_DMA_CHANNEL_7
2253 * @param TransferEventMode This parameter can be one of the following values:
2254 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2255 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2256 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2257 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2258 * @retval None.
2259 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)2260 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
2261 {
2262 uint32_t dma_base_addr = (uint32_t)DMAx;
2263 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
2264 TransferEventMode);
2265 }
2266
2267 /**
2268 * @brief Get transfer event mode.
2269 * @note This API is used for all available DMA channels.
2270 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
2271 * @param DMAx DMAx Instance
2272 * @param Channel This parameter can be one of the following values:
2273 * @arg @ref LL_DMA_CHANNEL_0
2274 * @arg @ref LL_DMA_CHANNEL_1
2275 * @arg @ref LL_DMA_CHANNEL_2
2276 * @arg @ref LL_DMA_CHANNEL_3
2277 * @arg @ref LL_DMA_CHANNEL_4
2278 * @arg @ref LL_DMA_CHANNEL_5
2279 * @arg @ref LL_DMA_CHANNEL_6
2280 * @arg @ref LL_DMA_CHANNEL_7
2281 * @retval Returned value can be one of the following values:
2282 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2283 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2284 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2285 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2286 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)2287 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2288 {
2289 uint32_t dma_base_addr = (uint32_t)DMAx;
2290 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
2291 }
2292
2293 /**
2294 * @brief Set trigger polarity.
2295 * @note This API is used for all available DMA channels.
2296 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
2297 * @param DMAx DMAx Instance
2298 * @param Channel This parameter can be one of the following values:
2299 * @arg @ref LL_DMA_CHANNEL_0
2300 * @arg @ref LL_DMA_CHANNEL_1
2301 * @arg @ref LL_DMA_CHANNEL_2
2302 * @arg @ref LL_DMA_CHANNEL_3
2303 * @arg @ref LL_DMA_CHANNEL_4
2304 * @arg @ref LL_DMA_CHANNEL_5
2305 * @arg @ref LL_DMA_CHANNEL_6
2306 * @arg @ref LL_DMA_CHANNEL_7
2307 * @param TriggerPolarity This parameter can be one of the following values:
2308 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2309 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2310 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2311 * @retval None.
2312 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)2313 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
2314 {
2315 uint32_t dma_base_addr = (uint32_t)DMAx;
2316 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
2317 TriggerPolarity);
2318 }
2319
2320 /**
2321 * @brief Get trigger polarity.
2322 * @note This API is used for all available DMA channels.
2323 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
2324 * @param DMAx DMAx Instance
2325 * @param Channel This parameter can be one of the following values:
2326 * @arg @ref LL_DMA_CHANNEL_0
2327 * @arg @ref LL_DMA_CHANNEL_1
2328 * @arg @ref LL_DMA_CHANNEL_2
2329 * @arg @ref LL_DMA_CHANNEL_3
2330 * @arg @ref LL_DMA_CHANNEL_4
2331 * @arg @ref LL_DMA_CHANNEL_5
2332 * @arg @ref LL_DMA_CHANNEL_6
2333 * @arg @ref LL_DMA_CHANNEL_7
2334 * @retval Returned value can be one of the following values:
2335 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2336 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2337 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2338 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)2339 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
2340 {
2341 uint32_t dma_base_addr = (uint32_t)DMAx;
2342 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
2343 }
2344
2345 /**
2346 * @brief Set trigger Mode.
2347 * @note This API is used for all available DMA channels.
2348 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
2349 * @param DMAx DMAx Instance
2350 * @param Channel This parameter can be one of the following values:
2351 * @arg @ref LL_DMA_CHANNEL_0
2352 * @arg @ref LL_DMA_CHANNEL_1
2353 * @arg @ref LL_DMA_CHANNEL_2
2354 * @arg @ref LL_DMA_CHANNEL_3
2355 * @arg @ref LL_DMA_CHANNEL_4
2356 * @arg @ref LL_DMA_CHANNEL_5
2357 * @arg @ref LL_DMA_CHANNEL_6
2358 * @arg @ref LL_DMA_CHANNEL_7
2359 * @param TriggerMode This parameter can be one of the following values:
2360 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
2361 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
2362 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2363 * @retval None.
2364 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)2365 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
2366 {
2367 uint32_t dma_base_addr = (uint32_t)DMAx;
2368 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
2369 TriggerMode);
2370 }
2371
2372 /**
2373 * @brief Get trigger Mode.
2374 * @note This API is used for all available DMA channels.
2375 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
2376 * @param DMAx DMAx Instance
2377 * @param Channel This parameter can be one of the following values:
2378 * @arg @ref LL_DMA_CHANNEL_0
2379 * @arg @ref LL_DMA_CHANNEL_1
2380 * @arg @ref LL_DMA_CHANNEL_2
2381 * @arg @ref LL_DMA_CHANNEL_3
2382 * @arg @ref LL_DMA_CHANNEL_4
2383 * @arg @ref LL_DMA_CHANNEL_5
2384 * @arg @ref LL_DMA_CHANNEL_6
2385 * @arg @ref LL_DMA_CHANNEL_7
2386 * @retval Returned value can be one of the following values:
2387 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
2388 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
2389 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2390 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)2391 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2392 {
2393 uint32_t dma_base_addr = (uint32_t)DMAx;
2394 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
2395 }
2396
2397 /**
2398 * @brief Set destination hardware and software transfer request.
2399 * @note This API is used for all available DMA channels.
2400 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
2401 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
2402 * @param DMAx DMAx Instance
2403 * @param Channel This parameter can be one of the following values:
2404 * @arg @ref LL_DMA_CHANNEL_0
2405 * @arg @ref LL_DMA_CHANNEL_1
2406 * @arg @ref LL_DMA_CHANNEL_2
2407 * @arg @ref LL_DMA_CHANNEL_3
2408 * @arg @ref LL_DMA_CHANNEL_4
2409 * @arg @ref LL_DMA_CHANNEL_5
2410 * @arg @ref LL_DMA_CHANNEL_6
2411 * @arg @ref LL_DMA_CHANNEL_7
2412 * @param Direction This parameter can be one of the following values:
2413 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
2414 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
2415 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2416 * @retval None.
2417 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)2418 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
2419 {
2420 uint32_t dma_base_addr = (uint32_t)DMAx;
2421 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2422 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
2423 }
2424
2425 /**
2426 * @brief Get destination hardware and software transfer request.
2427 * @note This API is used for all available DMA channels.
2428 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
2429 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
2430 * @param DMAx DMAx Instance
2431 * @param Channel This parameter can be one of the following values:
2432 * @arg @ref LL_DMA_CHANNEL_0
2433 * @arg @ref LL_DMA_CHANNEL_1
2434 * @arg @ref LL_DMA_CHANNEL_2
2435 * @arg @ref LL_DMA_CHANNEL_3
2436 * @arg @ref LL_DMA_CHANNEL_4
2437 * @arg @ref LL_DMA_CHANNEL_5
2438 * @arg @ref LL_DMA_CHANNEL_6
2439 * @arg @ref LL_DMA_CHANNEL_7
2440 * @retval Returned value can be one of the following values:
2441 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
2442 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
2443 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2444 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)2445 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
2446 {
2447 uint32_t dma_base_addr = (uint32_t)DMAx;
2448 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2449 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
2450 }
2451
2452 /**
2453 * @brief Set block hardware request.
2454 * @note This API is used for all available DMA channels.
2455 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
2456 * @param DMAx DMAx Instance
2457 * @param Channel This parameter can be one of the following values:
2458 * @arg @ref LL_DMA_CHANNEL_0
2459 * @arg @ref LL_DMA_CHANNEL_1
2460 * @arg @ref LL_DMA_CHANNEL_2
2461 * @arg @ref LL_DMA_CHANNEL_3
2462 * @arg @ref LL_DMA_CHANNEL_4
2463 * @arg @ref LL_DMA_CHANNEL_5
2464 * @arg @ref LL_DMA_CHANNEL_6
2465 * @arg @ref LL_DMA_CHANNEL_7
2466 * @param BlkHWRequest This parameter can be one of the following values:
2467 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
2468 * @arg @ref LL_DMA_HWREQUEST_BLK
2469 * @retval None.
2470 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)2471 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
2472 {
2473 uint32_t dma_base_addr = (uint32_t)DMAx;
2474 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
2475 BlkHWRequest);
2476 }
2477
2478 /**
2479 * @brief Get block hardware request.
2480 * @note This API is used for all available DMA channels.
2481 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
2482 * @param DMAx DMAx Instance
2483 * @param Channel This parameter can be one of the following values:
2484 * @arg @ref LL_DMA_CHANNEL_0
2485 * @arg @ref LL_DMA_CHANNEL_1
2486 * @arg @ref LL_DMA_CHANNEL_2
2487 * @arg @ref LL_DMA_CHANNEL_3
2488 * @arg @ref LL_DMA_CHANNEL_4
2489 * @arg @ref LL_DMA_CHANNEL_5
2490 * @arg @ref LL_DMA_CHANNEL_6
2491 * @arg @ref LL_DMA_CHANNEL_7
2492 * @retval Returned value can be one of the following values:
2493 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
2494 * @arg @ref LL_DMA_HWREQUEST_BLK
2495 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)2496 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
2497 {
2498 uint32_t dma_base_addr = (uint32_t)DMAx;
2499 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
2500 }
2501
2502 /**
2503 * @brief Set hardware request.
2504 * @note This API is used for all available DMA channels.
2505 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
2506 * @param DMAx DMAx Instance
2507 * @param Channel This parameter can be one of the following values:
2508 * @arg @ref LL_DMA_CHANNEL_0
2509 * @arg @ref LL_DMA_CHANNEL_1
2510 * @arg @ref LL_DMA_CHANNEL_2
2511 * @arg @ref LL_DMA_CHANNEL_3
2512 * @arg @ref LL_DMA_CHANNEL_4
2513 * @arg @ref LL_DMA_CHANNEL_5
2514 * @arg @ref LL_DMA_CHANNEL_6
2515 * @arg @ref LL_DMA_CHANNEL_7
2516 * @param Request This parameter can be one of the following values:
2517 * @arg @ref LL_GPDMA1_REQUEST_ADC4
2518 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*)
2519 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*)
2520 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
2521 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
2522 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*)
2523 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*)
2524 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*)
2525 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
2526 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
2527 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
2528 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
2529 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
2530 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
2531 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
2532 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
2533 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
2534 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
2535 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
2536 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
2537 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
2538 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
2539 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
2540 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
2541 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
2542 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
2543 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
2544 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
2545 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
2546 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
2547 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
2548 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*)
2549 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*)
2550 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*)
2551 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*)
2552 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*)
2553 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*)
2554 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
2555 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
2556 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
2557 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
2558 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
2559 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
2560 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
2561 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
2562 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
2563 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
2564 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
2565 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
2566 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*)
2567 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*)
2568 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*)
2569 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*)
2570 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*)
2571 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*)
2572 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*)
2573 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*)
2574 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
2575 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
2576 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*)
2577 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
2578 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
2579 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
2580 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
2581 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
2582 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*)
2583 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*)
2584 * @note (*) Availability depends on devices.
2585 * @retval None.
2586 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)2587 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
2588 {
2589 uint32_t dma_base_addr = (uint32_t)DMAx;
2590 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
2591 }
2592
2593 /**
2594 * @brief Get hardware request.
2595 * @note This API is used for all available DMA channels.
2596 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
2597 * @param DMAx DMAx Instance
2598 * @param Channel This parameter can be one of the following values:
2599 * @arg @ref LL_DMA_CHANNEL_0
2600 * @arg @ref LL_DMA_CHANNEL_1
2601 * @arg @ref LL_DMA_CHANNEL_2
2602 * @arg @ref LL_DMA_CHANNEL_3
2603 * @arg @ref LL_DMA_CHANNEL_4
2604 * @arg @ref LL_DMA_CHANNEL_5
2605 * @arg @ref LL_DMA_CHANNEL_6
2606 * @arg @ref LL_DMA_CHANNEL_7
2607 * @retval Returned value can be one of the following values:
2608 * @arg @ref LL_GPDMA1_REQUEST_ADC4
2609 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*)
2610 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*)
2611 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
2612 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
2613 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*)
2614 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*)
2615 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*)
2616 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
2617 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
2618 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
2619 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
2620 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
2621 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
2622 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
2623 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
2624 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
2625 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
2626 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
2627 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
2628 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
2629 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
2630 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
2631 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
2632 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
2633 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
2634 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
2635 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
2636 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
2637 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
2638 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
2639 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*)
2640 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*)
2641 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*)
2642 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*)
2643 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*)
2644 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*)
2645 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
2646 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
2647 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
2648 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
2649 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
2650 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
2651 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
2652 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
2653 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
2654 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
2655 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
2656 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
2657 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*)
2658 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*)
2659 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*)
2660 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*)
2661 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*)
2662 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*)
2663 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*)
2664 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*)
2665 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
2666 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
2667 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*)
2668 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
2669 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
2670 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
2671 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
2672 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
2673 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*)
2674 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*)
2675 * @note (*) Availability depends on devices.
2676 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)2677 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
2678 {
2679 uint32_t dma_base_addr = (uint32_t)DMAx;
2680 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
2681 }
2682
2683 /**
2684 * @brief Set hardware trigger.
2685 * @note This API is used for all available DMA channels.
2686 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
2687 * @param DMAx DMAx Instance
2688 * @param Channel This parameter can be one of the following values:
2689 * @arg @ref LL_DMA_CHANNEL_0
2690 * @arg @ref LL_DMA_CHANNEL_1
2691 * @arg @ref LL_DMA_CHANNEL_2
2692 * @arg @ref LL_DMA_CHANNEL_3
2693 * @arg @ref LL_DMA_CHANNEL_4
2694 * @arg @ref LL_DMA_CHANNEL_5
2695 * @arg @ref LL_DMA_CHANNEL_6
2696 * @arg @ref LL_DMA_CHANNEL_7
2697 * @param Trigger This parameter can be one of the following values:
2698 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
2699 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
2700 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
2701 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
2702 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
2703 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
2704 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
2705 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
2706 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
2707 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
2708 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
2709 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
2710 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
2711 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*)
2712 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*)
2713 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
2714 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
2715 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
2716 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
2717 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
2718 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
2719 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
2720 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
2721 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
2722 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
2723 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
2724 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
2725 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
2726 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
2727 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
2728 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
2729 * @retval None.
2730 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)2731 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
2732 {
2733 uint32_t dma_base_addr = (uint32_t)DMAx;
2734 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
2735 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
2736 }
2737
2738 /**
2739 * @brief Get hardware triggers.
2740 * @note This API is used for all available DMA channels.
2741 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
2742 * @param DMAx DMAx Instance
2743 * @param Channel This parameter can be one of the following values:
2744 * @arg @ref LL_DMA_CHANNEL_0
2745 * @arg @ref LL_DMA_CHANNEL_1
2746 * @arg @ref LL_DMA_CHANNEL_2
2747 * @arg @ref LL_DMA_CHANNEL_3
2748 * @arg @ref LL_DMA_CHANNEL_4
2749 * @arg @ref LL_DMA_CHANNEL_5
2750 * @arg @ref LL_DMA_CHANNEL_6
2751 * @arg @ref LL_DMA_CHANNEL_7
2752 * @retval Returned value can be one of the following values:
2753 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
2754 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
2755 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
2756 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
2757 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
2758 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
2759 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
2760 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
2761 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
2762 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
2763 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
2764 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
2765 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
2766 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*)
2767 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*)
2768 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
2769 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
2770 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
2771 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
2772 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
2773 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
2774 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
2775 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
2776 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
2777 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
2778 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
2779 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
2780 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
2781 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
2782 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
2783 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
2784 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)2785 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
2786 {
2787 uint32_t dma_base_addr = (uint32_t)DMAx;
2788 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2789 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
2790 }
2791
2792 /**
2793 * @brief Set block data length in bytes to transfer.
2794 * @note This API is used for all available DMA channels.
2795 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
2796 * @param DMAx DMAx Instance
2797 * @param Channel This parameter can be one of the following values:
2798 * @arg @ref LL_DMA_CHANNEL_0
2799 * @arg @ref LL_DMA_CHANNEL_1
2800 * @arg @ref LL_DMA_CHANNEL_2
2801 * @arg @ref LL_DMA_CHANNEL_3
2802 * @arg @ref LL_DMA_CHANNEL_4
2803 * @arg @ref LL_DMA_CHANNEL_5
2804 * @arg @ref LL_DMA_CHANNEL_6
2805 * @arg @ref LL_DMA_CHANNEL_7
2806 * @param BlkDataLength Between 0 to 0x0000FFFF
2807 * @retval None.
2808 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)2809 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
2810 {
2811 uint32_t dma_base_addr = (uint32_t)DMAx;
2812 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
2813 BlkDataLength);
2814 }
2815
2816 /**
2817 * @brief Get block data length in bytes to transfer.
2818 * @note This API is used for all available DMA channels.
2819 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
2820 * @param DMAx DMAx Instance
2821 * @param Channel This parameter can be one of the following values:
2822 * @arg @ref LL_DMA_CHANNEL_0
2823 * @arg @ref LL_DMA_CHANNEL_1
2824 * @arg @ref LL_DMA_CHANNEL_2
2825 * @arg @ref LL_DMA_CHANNEL_3
2826 * @arg @ref LL_DMA_CHANNEL_4
2827 * @arg @ref LL_DMA_CHANNEL_5
2828 * @arg @ref LL_DMA_CHANNEL_6
2829 * @arg @ref LL_DMA_CHANNEL_7
2830 * @retval Between 0 to 0x0000FFFF
2831 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)2832 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2833 {
2834 uint32_t dma_base_addr = (uint32_t)DMAx;
2835 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
2836 }
2837
2838 /**
2839 * @brief Configure the source and destination addresses.
2840 * @note This API is used for all available DMA channels.
2841 * @note This API must not be called when the DMA Channel is enabled.
2842 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
2843 * CDAR DA LL_DMA_ConfigAddresses
2844 * @param DMAx DMAx Instance
2845 * @param Channel This parameter can be one of the following values:
2846 * @arg @ref LL_DMA_CHANNEL_0
2847 * @arg @ref LL_DMA_CHANNEL_1
2848 * @arg @ref LL_DMA_CHANNEL_2
2849 * @arg @ref LL_DMA_CHANNEL_3
2850 * @arg @ref LL_DMA_CHANNEL_4
2851 * @arg @ref LL_DMA_CHANNEL_5
2852 * @arg @ref LL_DMA_CHANNEL_6
2853 * @arg @ref LL_DMA_CHANNEL_7
2854 * @param SrcAddress Between 0 to 0xFFFFFFFF
2855 * @param DestAddress Between 0 to 0xFFFFFFFF
2856 * @retval None.
2857 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)2858 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
2859 DestAddress)
2860 {
2861 uint32_t dma_base_addr = (uint32_t)DMAx;
2862 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2863 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
2864 }
2865
2866 /**
2867 * @brief Set source address.
2868 * @note This API is used for all available DMA channels.
2869 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
2870 * @param DMAx DMAx Instance
2871 * @param Channel This parameter can be one of the following values:
2872 * @arg @ref LL_DMA_CHANNEL_0
2873 * @arg @ref LL_DMA_CHANNEL_1
2874 * @arg @ref LL_DMA_CHANNEL_2
2875 * @arg @ref LL_DMA_CHANNEL_3
2876 * @arg @ref LL_DMA_CHANNEL_4
2877 * @arg @ref LL_DMA_CHANNEL_5
2878 * @arg @ref LL_DMA_CHANNEL_6
2879 * @arg @ref LL_DMA_CHANNEL_7
2880 * @param SrcAddress Between 0 to 0xFFFFFFFF
2881 * @retval None.
2882 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)2883 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
2884 {
2885 uint32_t dma_base_addr = (uint32_t)DMAx;
2886 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2887 }
2888
2889 /**
2890 * @brief Get source address.
2891 * @note This API is used for all available DMA channels.
2892 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
2893 * @param DMAx DMAx Instance
2894 * @param Channel This parameter can be one of the following values:
2895 * @arg @ref LL_DMA_CHANNEL_0
2896 * @arg @ref LL_DMA_CHANNEL_1
2897 * @arg @ref LL_DMA_CHANNEL_2
2898 * @arg @ref LL_DMA_CHANNEL_3
2899 * @arg @ref LL_DMA_CHANNEL_4
2900 * @arg @ref LL_DMA_CHANNEL_5
2901 * @arg @ref LL_DMA_CHANNEL_6
2902 * @arg @ref LL_DMA_CHANNEL_7
2903 * @retval Between 0 to 0xFFFFFFFF
2904 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)2905 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
2906 {
2907 uint32_t dma_base_addr = (uint32_t)DMAx;
2908 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
2909 }
2910
2911 /**
2912 * @brief Set destination address.
2913 * @note This API is used for all available DMA channels.
2914 * @rmtoll CDAR DA LL_DMA_SetDestAddress
2915 * @param DMAx DMAx Instance
2916 * @param Channel This parameter can be one of the following values:
2917 * @arg @ref LL_DMA_CHANNEL_0
2918 * @arg @ref LL_DMA_CHANNEL_1
2919 * @arg @ref LL_DMA_CHANNEL_2
2920 * @arg @ref LL_DMA_CHANNEL_3
2921 * @arg @ref LL_DMA_CHANNEL_4
2922 * @arg @ref LL_DMA_CHANNEL_5
2923 * @arg @ref LL_DMA_CHANNEL_6
2924 * @arg @ref LL_DMA_CHANNEL_7
2925 * @param DestAddress Between 0 to 0xFFFFFFFF
2926 * @retval None.
2927 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)2928 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
2929 {
2930 uint32_t dma_base_addr = (uint32_t)DMAx;
2931 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
2932 }
2933
2934 /**
2935 * @brief Get destination address.
2936 * @note This API is used for all available DMA channels.
2937 * @rmtoll CDAR DA LL_DMA_GetDestAddress
2938 * @param DMAx DMAx Instance
2939 * @param Channel This parameter can be one of the following values:
2940 * @arg @ref LL_DMA_CHANNEL_0
2941 * @arg @ref LL_DMA_CHANNEL_1
2942 * @arg @ref LL_DMA_CHANNEL_2
2943 * @arg @ref LL_DMA_CHANNEL_3
2944 * @arg @ref LL_DMA_CHANNEL_4
2945 * @arg @ref LL_DMA_CHANNEL_5
2946 * @arg @ref LL_DMA_CHANNEL_6
2947 * @arg @ref LL_DMA_CHANNEL_7
2948 * @retval Between 0 to 0xFFFFFFFF
2949 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)2950 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
2951 {
2952 uint32_t dma_base_addr = (uint32_t)DMAx;
2953 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
2954 }
2955
2956
2957 /**
2958 * @brief Configure registers update and node address offset during the link transfer.
2959 * @note This API is used for all available DMA channels.
2960 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
2961 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
2962 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
2963 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
2964 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
2965 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
2966 * @param DMAx DMAx Instance
2967 * @param Channel This parameter can be one of the following values:
2968 * @arg @ref LL_DMA_CHANNEL_0
2969 * @arg @ref LL_DMA_CHANNEL_1
2970 * @arg @ref LL_DMA_CHANNEL_2
2971 * @arg @ref LL_DMA_CHANNEL_3
2972 * @arg @ref LL_DMA_CHANNEL_4
2973 * @arg @ref LL_DMA_CHANNEL_5
2974 * @arg @ref LL_DMA_CHANNEL_6
2975 * @arg @ref LL_DMA_CHANNEL_7
2976 * @param RegistersUpdate This parameter must be a combination of all the following values:
2977 * @arg @ref LL_DMA_UPDATE_CTR1
2978 * @arg @ref LL_DMA_UPDATE_CTR2
2979 * @arg @ref LL_DMA_UPDATE_CBR1
2980 * @arg @ref LL_DMA_UPDATE_CSAR
2981 * @arg @ref LL_DMA_UPDATE_CDAR
2982 * @arg @ref LL_DMA_UPDATE_CLLR
2983 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
2984 * @retval None.
2985 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)2986 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
2987 uint32_t LinkedListAddrOffset)
2988 {
2989 uint32_t dma_base_addr = (uint32_t)DMAx;
2990 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
2991 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
2992 DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
2993 }
2994
2995 /**
2996 * @brief Enable CTR1 update during the link transfer.
2997 * @note This API is used for all available DMA channels.
2998 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
2999 * @param DMAx DMAx Instance
3000 * @param Channel This parameter can be one of the following values:
3001 * @arg @ref LL_DMA_CHANNEL_0
3002 * @arg @ref LL_DMA_CHANNEL_1
3003 * @arg @ref LL_DMA_CHANNEL_2
3004 * @arg @ref LL_DMA_CHANNEL_3
3005 * @arg @ref LL_DMA_CHANNEL_4
3006 * @arg @ref LL_DMA_CHANNEL_5
3007 * @arg @ref LL_DMA_CHANNEL_6
3008 * @arg @ref LL_DMA_CHANNEL_7
3009 * @retval None.
3010 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3011 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3012 {
3013 uint32_t dma_base_addr = (uint32_t)DMAx;
3014 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
3015 }
3016
3017 /**
3018 * @brief Disable CTR1 update during the link transfer.
3019 * @note This API is used for all available DMA channels.
3020 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
3021 * @param DMAx DMAx Instance
3022 * @param Channel This parameter can be one of the following values:
3023 * @arg @ref LL_DMA_CHANNEL_0
3024 * @arg @ref LL_DMA_CHANNEL_1
3025 * @arg @ref LL_DMA_CHANNEL_2
3026 * @arg @ref LL_DMA_CHANNEL_3
3027 * @arg @ref LL_DMA_CHANNEL_4
3028 * @arg @ref LL_DMA_CHANNEL_5
3029 * @arg @ref LL_DMA_CHANNEL_6
3030 * @arg @ref LL_DMA_CHANNEL_7
3031 * @retval None.
3032 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3033 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3034 {
3035 uint32_t dma_base_addr = (uint32_t)DMAx;
3036 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
3037 }
3038
3039 /**
3040 * @brief Check if CTR1 update during the link transfer is enabled.
3041 * @note This API is used for all available DMA channels.
3042 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
3043 * @param DMAx DMAx Instance
3044 * @param Channel This parameter can be one of the following values:
3045 * @arg @ref LL_DMA_CHANNEL_0
3046 * @arg @ref LL_DMA_CHANNEL_1
3047 * @arg @ref LL_DMA_CHANNEL_2
3048 * @arg @ref LL_DMA_CHANNEL_3
3049 * @arg @ref LL_DMA_CHANNEL_4
3050 * @arg @ref LL_DMA_CHANNEL_5
3051 * @arg @ref LL_DMA_CHANNEL_6
3052 * @arg @ref LL_DMA_CHANNEL_7
3053 * @retval State of bit (1 or 0).
3054 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3055 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3056 {
3057 uint32_t dma_base_addr = (uint32_t)DMAx;
3058 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
3059 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
3060 }
3061
3062 /**
3063 * @brief Enable CTR2 update during the link transfer.
3064 * @note This API is used for all available DMA channels.
3065 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
3066 * @param DMAx DMAx Instance
3067 * @param Channel This parameter can be one of the following values:
3068 * @arg @ref LL_DMA_CHANNEL_0
3069 * @arg @ref LL_DMA_CHANNEL_1
3070 * @arg @ref LL_DMA_CHANNEL_2
3071 * @arg @ref LL_DMA_CHANNEL_3
3072 * @arg @ref LL_DMA_CHANNEL_4
3073 * @arg @ref LL_DMA_CHANNEL_5
3074 * @arg @ref LL_DMA_CHANNEL_6
3075 * @arg @ref LL_DMA_CHANNEL_7
3076 * @retval None.
3077 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3078 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3079 {
3080 uint32_t dma_base_addr = (uint32_t)DMAx;
3081 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
3082 }
3083
3084 /**
3085 * @brief Disable CTR2 update during the link transfer.
3086 * @note This API is used for all available DMA channels.
3087 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
3088 * @param DMAx DMAx Instance
3089 * @param Channel This parameter can be one of the following values:
3090 * @arg @ref LL_DMA_CHANNEL_0
3091 * @arg @ref LL_DMA_CHANNEL_1
3092 * @arg @ref LL_DMA_CHANNEL_2
3093 * @arg @ref LL_DMA_CHANNEL_3
3094 * @arg @ref LL_DMA_CHANNEL_4
3095 * @arg @ref LL_DMA_CHANNEL_5
3096 * @arg @ref LL_DMA_CHANNEL_6
3097 * @arg @ref LL_DMA_CHANNEL_7
3098 * @retval None.
3099 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3100 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3101 {
3102 uint32_t dma_base_addr = (uint32_t)DMAx;
3103 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
3104 }
3105
3106 /**
3107 * @brief Check if CTR2 update during the link transfer is enabled.
3108 * @note This API is used for all available DMA channels.
3109 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
3110 * @param DMAx DMAx Instance
3111 * @param Channel This parameter can be one of the following values:
3112 * @arg @ref LL_DMA_CHANNEL_0
3113 * @arg @ref LL_DMA_CHANNEL_1
3114 * @arg @ref LL_DMA_CHANNEL_2
3115 * @arg @ref LL_DMA_CHANNEL_3
3116 * @arg @ref LL_DMA_CHANNEL_4
3117 * @arg @ref LL_DMA_CHANNEL_5
3118 * @arg @ref LL_DMA_CHANNEL_6
3119 * @arg @ref LL_DMA_CHANNEL_7
3120 * @retval State of bit (1 or 0).
3121 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3122 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3123 {
3124 uint32_t dma_base_addr = (uint32_t)DMAx;
3125 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
3126 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
3127 }
3128
3129 /**
3130 * @brief Enable CBR1 update during the link transfer.
3131 * @note This API is used for all available DMA channels.
3132 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
3133 * @param DMAx DMAx Instance
3134 * @param Channel This parameter can be one of the following values:
3135 * @arg @ref LL_DMA_CHANNEL_0
3136 * @arg @ref LL_DMA_CHANNEL_1
3137 * @arg @ref LL_DMA_CHANNEL_2
3138 * @arg @ref LL_DMA_CHANNEL_3
3139 * @arg @ref LL_DMA_CHANNEL_4
3140 * @arg @ref LL_DMA_CHANNEL_5
3141 * @arg @ref LL_DMA_CHANNEL_6
3142 * @arg @ref LL_DMA_CHANNEL_7
3143 * @retval None.
3144 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3145 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3146 {
3147 uint32_t dma_base_addr = (uint32_t)DMAx;
3148 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
3149 }
3150
3151 /**
3152 * @brief Disable CBR1 update during the link transfer.
3153 * @note This API is used for all available DMA channels.
3154 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
3155 * @param DMAx DMAx Instance
3156 * @param Channel This parameter can be one of the following values:
3157 * @arg @ref LL_DMA_CHANNEL_0
3158 * @arg @ref LL_DMA_CHANNEL_1
3159 * @arg @ref LL_DMA_CHANNEL_2
3160 * @arg @ref LL_DMA_CHANNEL_3
3161 * @arg @ref LL_DMA_CHANNEL_4
3162 * @arg @ref LL_DMA_CHANNEL_5
3163 * @arg @ref LL_DMA_CHANNEL_6
3164 * @arg @ref LL_DMA_CHANNEL_7
3165 * @retval None.
3166 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3167 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3168 {
3169 uint32_t dma_base_addr = (uint32_t)DMAx;
3170 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
3171 }
3172
3173 /**
3174 * @brief Check if CBR1 update during the link transfer is enabled.
3175 * @note This API is used for all available DMA channels.
3176 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
3177 * @param DMAx DMAx Instance
3178 * @param Channel This parameter can be one of the following values:
3179 * @arg @ref LL_DMA_CHANNEL_0
3180 * @arg @ref LL_DMA_CHANNEL_1
3181 * @arg @ref LL_DMA_CHANNEL_2
3182 * @arg @ref LL_DMA_CHANNEL_3
3183 * @arg @ref LL_DMA_CHANNEL_4
3184 * @arg @ref LL_DMA_CHANNEL_5
3185 * @arg @ref LL_DMA_CHANNEL_6
3186 * @arg @ref LL_DMA_CHANNEL_7
3187 * @retval State of bit (1 or 0).
3188 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3189 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3190 {
3191 uint32_t dma_base_addr = (uint32_t)DMAx;
3192 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
3193 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
3194 }
3195
3196 /**
3197 * @brief Enable CSAR update during the link transfer.
3198 * @note This API is used for all available DMA channels.
3199 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
3200 * @param DMAx DMAx Instance
3201 * @param Channel This parameter can be one of the following values:
3202 * @arg @ref LL_DMA_CHANNEL_0
3203 * @arg @ref LL_DMA_CHANNEL_1
3204 * @arg @ref LL_DMA_CHANNEL_2
3205 * @arg @ref LL_DMA_CHANNEL_3
3206 * @arg @ref LL_DMA_CHANNEL_4
3207 * @arg @ref LL_DMA_CHANNEL_5
3208 * @arg @ref LL_DMA_CHANNEL_6
3209 * @arg @ref LL_DMA_CHANNEL_7
3210 * @retval None.
3211 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3212 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3213 {
3214 uint32_t dma_base_addr = (uint32_t)DMAx;
3215 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
3216 }
3217
3218 /**
3219 * @brief Disable CSAR update during the link transfer.
3220 * @note This API is used for all available DMA channels.
3221 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
3222 * @param DMAx DMAx Instance
3223 * @param Channel This parameter can be one of the following values:
3224 * @arg @ref LL_DMA_CHANNEL_0
3225 * @arg @ref LL_DMA_CHANNEL_1
3226 * @arg @ref LL_DMA_CHANNEL_2
3227 * @arg @ref LL_DMA_CHANNEL_3
3228 * @arg @ref LL_DMA_CHANNEL_4
3229 * @arg @ref LL_DMA_CHANNEL_5
3230 * @arg @ref LL_DMA_CHANNEL_6
3231 * @arg @ref LL_DMA_CHANNEL_7
3232 * @retval None.
3233 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3234 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3235 {
3236 uint32_t dma_base_addr = (uint32_t)DMAx;
3237 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
3238 }
3239
3240 /**
3241 * @brief Check if CSAR update during the link transfer is enabled.
3242 * @note This API is used for all available DMA channels.
3243 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
3244 * @param DMAx DMAx Instance
3245 * @param Channel This parameter can be one of the following values:
3246 * @arg @ref LL_DMA_CHANNEL_0
3247 * @arg @ref LL_DMA_CHANNEL_1
3248 * @arg @ref LL_DMA_CHANNEL_2
3249 * @arg @ref LL_DMA_CHANNEL_3
3250 * @arg @ref LL_DMA_CHANNEL_4
3251 * @arg @ref LL_DMA_CHANNEL_5
3252 * @arg @ref LL_DMA_CHANNEL_6
3253 * @arg @ref LL_DMA_CHANNEL_7
3254 * @retval State of bit (1 or 0).
3255 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3256 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3257 {
3258 uint32_t dma_base_addr = (uint32_t)DMAx;
3259 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
3260 == (DMA_CLLR_USA)) ? 1UL : 0UL);
3261 }
3262
3263 /**
3264 * @brief Enable CDAR update during the link transfer.
3265 * @note This API is used for all available DMA channels.
3266 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
3267 * @param DMAx DMAx Instance
3268 * @param Channel This parameter can be one of the following values:
3269 * @arg @ref LL_DMA_CHANNEL_0
3270 * @arg @ref LL_DMA_CHANNEL_1
3271 * @arg @ref LL_DMA_CHANNEL_2
3272 * @arg @ref LL_DMA_CHANNEL_3
3273 * @arg @ref LL_DMA_CHANNEL_4
3274 * @arg @ref LL_DMA_CHANNEL_5
3275 * @arg @ref LL_DMA_CHANNEL_6
3276 * @arg @ref LL_DMA_CHANNEL_7
3277 * @retval None.
3278 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3279 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3280 {
3281 uint32_t dma_base_addr = (uint32_t)DMAx;
3282 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
3283 }
3284
3285 /**
3286 * @brief Disable CDAR update during the link transfer.
3287 * @note This API is used for all available DMA channels.
3288 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
3289 * @param DMAx DMAx Instance
3290 * @param Channel This parameter can be one of the following values:
3291 * @arg @ref LL_DMA_CHANNEL_0
3292 * @arg @ref LL_DMA_CHANNEL_1
3293 * @arg @ref LL_DMA_CHANNEL_2
3294 * @arg @ref LL_DMA_CHANNEL_3
3295 * @arg @ref LL_DMA_CHANNEL_4
3296 * @arg @ref LL_DMA_CHANNEL_5
3297 * @arg @ref LL_DMA_CHANNEL_6
3298 * @arg @ref LL_DMA_CHANNEL_7
3299 * @retval None.
3300 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3301 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3302 {
3303 uint32_t dma_base_addr = (uint32_t)DMAx;
3304 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
3305 }
3306
3307 /**
3308 * @brief Check if CDAR update during the link transfer is enabled.
3309 * @note This API is used for all available DMA channels.
3310 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
3311 * @param DMAx DMAx Instance
3312 * @param Channel This parameter can be one of the following values:
3313 * @arg @ref LL_DMA_CHANNEL_0
3314 * @arg @ref LL_DMA_CHANNEL_1
3315 * @arg @ref LL_DMA_CHANNEL_2
3316 * @arg @ref LL_DMA_CHANNEL_3
3317 * @arg @ref LL_DMA_CHANNEL_4
3318 * @arg @ref LL_DMA_CHANNEL_5
3319 * @arg @ref LL_DMA_CHANNEL_6
3320 * @arg @ref LL_DMA_CHANNEL_7
3321 * @retval State of bit (1 or 0).
3322 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3323 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3324 {
3325 uint32_t dma_base_addr = (uint32_t)DMAx;
3326 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
3327 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
3328 }
3329
3330
3331 /**
3332 * @brief Enable CLLR update during the link transfer.
3333 * @note This API is used for all available DMA channels.
3334 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
3335 * @param DMAx DMAx Instance
3336 * @param Channel This parameter can be one of the following values:
3337 * @arg @ref LL_DMA_CHANNEL_0
3338 * @arg @ref LL_DMA_CHANNEL_1
3339 * @arg @ref LL_DMA_CHANNEL_2
3340 * @arg @ref LL_DMA_CHANNEL_3
3341 * @arg @ref LL_DMA_CHANNEL_4
3342 * @arg @ref LL_DMA_CHANNEL_5
3343 * @arg @ref LL_DMA_CHANNEL_6
3344 * @arg @ref LL_DMA_CHANNEL_7
3345 * @retval None.
3346 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3347 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3348 {
3349 uint32_t dma_base_addr = (uint32_t)DMAx;
3350 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
3351 }
3352
3353 /**
3354 * @brief Disable CLLR update during the link transfer.
3355 * @note This API is used for all available DMA channels.
3356 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
3357 * @param DMAx DMAx Instance
3358 * @param Channel This parameter can be one of the following values:
3359 * @arg @ref LL_DMA_CHANNEL_0
3360 * @arg @ref LL_DMA_CHANNEL_1
3361 * @arg @ref LL_DMA_CHANNEL_2
3362 * @arg @ref LL_DMA_CHANNEL_3
3363 * @arg @ref LL_DMA_CHANNEL_4
3364 * @arg @ref LL_DMA_CHANNEL_5
3365 * @arg @ref LL_DMA_CHANNEL_6
3366 * @arg @ref LL_DMA_CHANNEL_7
3367 * @retval None.
3368 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3369 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3370 {
3371 uint32_t dma_base_addr = (uint32_t)DMAx;
3372 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
3373 }
3374
3375 /**
3376 * @brief Check if CLLR update during the link transfer is enabled.
3377 * @note This API is used for all available DMA channels.
3378 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
3379 * @param DMAx DMAx Instance
3380 * @param Channel This parameter can be one of the following values:
3381 * @arg @ref LL_DMA_CHANNEL_0
3382 * @arg @ref LL_DMA_CHANNEL_1
3383 * @arg @ref LL_DMA_CHANNEL_2
3384 * @arg @ref LL_DMA_CHANNEL_3
3385 * @arg @ref LL_DMA_CHANNEL_4
3386 * @arg @ref LL_DMA_CHANNEL_5
3387 * @arg @ref LL_DMA_CHANNEL_6
3388 * @arg @ref LL_DMA_CHANNEL_7
3389 * @retval State of bit (1 or 0).
3390 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3391 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3392 {
3393 uint32_t dma_base_addr = (uint32_t)DMAx;
3394 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
3395 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
3396 }
3397
3398 /**
3399 * @brief Set linked list address offset.
3400 * @note This API is used for all available DMA channels.
3401 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
3402 * @param DMAx DMAx Instance
3403 * @param Channel This parameter can be one of the following values:
3404 * @arg @ref LL_DMA_CHANNEL_0
3405 * @arg @ref LL_DMA_CHANNEL_1
3406 * @arg @ref LL_DMA_CHANNEL_2
3407 * @arg @ref LL_DMA_CHANNEL_3
3408 * @arg @ref LL_DMA_CHANNEL_4
3409 * @arg @ref LL_DMA_CHANNEL_5
3410 * @arg @ref LL_DMA_CHANNEL_6
3411 * @arg @ref LL_DMA_CHANNEL_7
3412 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
3413 * @retval None.
3414 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)3415 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
3416 uint32_t LinkedListAddrOffset)
3417 {
3418 uint32_t dma_base_addr = (uint32_t)DMAx;
3419 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
3420 (LinkedListAddrOffset & DMA_CLLR_LA));
3421 }
3422
3423 /**
3424 * @brief Get linked list address offset.
3425 * @note This API is used for all available DMA channels.
3426 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
3427 * @param DMAx DMAx Instance
3428 * @param Channel This parameter can be one of the following values:
3429 * @arg @ref LL_DMA_CHANNEL_0
3430 * @arg @ref LL_DMA_CHANNEL_1
3431 * @arg @ref LL_DMA_CHANNEL_2
3432 * @arg @ref LL_DMA_CHANNEL_3
3433 * @arg @ref LL_DMA_CHANNEL_4
3434 * @arg @ref LL_DMA_CHANNEL_5
3435 * @arg @ref LL_DMA_CHANNEL_6
3436 * @arg @ref LL_DMA_CHANNEL_7
3437 * @retval Between 0 to 0x0000FFFC.
3438 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)3439 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
3440 {
3441 uint32_t dma_base_addr = (uint32_t)DMAx;
3442 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
3443 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
3444 }
3445
3446 /**
3447 * @brief Get FIFO level.
3448 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
3449 * @param DMAx DMAx Instance
3450 * @param Channel This parameter can be one of the following values:
3451 * @arg @ref LL_DMA_CHANNEL_0
3452 * @arg @ref LL_DMA_CHANNEL_1
3453 * @arg @ref LL_DMA_CHANNEL_2
3454 * @arg @ref LL_DMA_CHANNEL_3
3455 * @arg @ref LL_DMA_CHANNEL_4
3456 * @arg @ref LL_DMA_CHANNEL_5
3457 * @arg @ref LL_DMA_CHANNEL_6
3458 * @arg @ref LL_DMA_CHANNEL_7
3459 * @retval Between 0 to 0x000000FF.
3460 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)3461 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
3462 {
3463 uint32_t dma_base_addr = (uint32_t)DMAx;
3464 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
3465 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
3466 }
3467
3468 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3469 /**
3470 * @brief Enable the DMA channel secure attribute.
3471 * @note This API is used for all available DMA channels.
3472 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
3473 * @param DMAx DMAx Instance
3474 * @param Channel This parameter can be one of the following values:
3475 * @arg @ref LL_DMA_CHANNEL_0
3476 * @arg @ref LL_DMA_CHANNEL_1
3477 * @arg @ref LL_DMA_CHANNEL_2
3478 * @arg @ref LL_DMA_CHANNEL_3
3479 * @arg @ref LL_DMA_CHANNEL_4
3480 * @arg @ref LL_DMA_CHANNEL_5
3481 * @arg @ref LL_DMA_CHANNEL_6
3482 * @arg @ref LL_DMA_CHANNEL_7
3483 * @retval None.
3484 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)3485 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
3486 {
3487 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
3488 }
3489
3490 /**
3491 * @brief Disable the DMA channel secure attribute.
3492 * @note This API is used for all available DMA channels.
3493 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
3494 * @param DMAx DMAx Instance
3495 * @param Channel This parameter can be one of the following values:
3496 * @arg @ref LL_DMA_CHANNEL_0
3497 * @arg @ref LL_DMA_CHANNEL_1
3498 * @arg @ref LL_DMA_CHANNEL_2
3499 * @arg @ref LL_DMA_CHANNEL_3
3500 * @arg @ref LL_DMA_CHANNEL_4
3501 * @arg @ref LL_DMA_CHANNEL_5
3502 * @arg @ref LL_DMA_CHANNEL_6
3503 * @arg @ref LL_DMA_CHANNEL_7
3504 * @retval None.
3505 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)3506 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
3507 {
3508 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
3509 }
3510 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3511
3512 #if defined (DMA_SECCFGR_SEC0)
3513 /**
3514 * @brief Check if DMA channel secure is enabled.
3515 * @note This API is used for all available DMA channels.
3516 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
3517 * @param DMAx DMAx Instance
3518 * @param Channel This parameter can be one of the following values:
3519 * @arg @ref LL_DMA_CHANNEL_0
3520 * @arg @ref LL_DMA_CHANNEL_1
3521 * @arg @ref LL_DMA_CHANNEL_2
3522 * @arg @ref LL_DMA_CHANNEL_3
3523 * @arg @ref LL_DMA_CHANNEL_4
3524 * @arg @ref LL_DMA_CHANNEL_5
3525 * @arg @ref LL_DMA_CHANNEL_6
3526 * @arg @ref LL_DMA_CHANNEL_7
3527 * @retval State of bit (1 or 0).
3528 */
LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef * DMAx,uint32_t Channel)3529 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
3530 {
3531 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
3532 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3533 }
3534 #endif /* DMA_SECCFGR_SEC0 */
3535 #if defined (DMA_PRIVCFGR_PRIV0)
3536 /**
3537 * @brief Enable the DMA channel privilege attribute.
3538 * @note This API is used for all available DMA channels.
3539 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
3540 * @param DMAx DMAx Instance
3541 * @param Channel This parameter can be one of the following values:
3542 * @arg @ref LL_DMA_CHANNEL_0
3543 * @arg @ref LL_DMA_CHANNEL_1
3544 * @arg @ref LL_DMA_CHANNEL_2
3545 * @arg @ref LL_DMA_CHANNEL_3
3546 * @arg @ref LL_DMA_CHANNEL_4
3547 * @arg @ref LL_DMA_CHANNEL_5
3548 * @arg @ref LL_DMA_CHANNEL_6
3549 * @arg @ref LL_DMA_CHANNEL_7
3550 * @retval None.
3551 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)3552 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
3553 {
3554 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
3555 }
3556
3557 /**
3558 * @brief Disable the DMA channel privilege attribute.
3559 * @note This API is used for all available DMA channels.
3560 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
3561 * @param DMAx DMAx Instance
3562 * @param Channel This parameter can be one of the following values:
3563 * @arg @ref LL_DMA_CHANNEL_0
3564 * @arg @ref LL_DMA_CHANNEL_1
3565 * @arg @ref LL_DMA_CHANNEL_2
3566 * @arg @ref LL_DMA_CHANNEL_3
3567 * @arg @ref LL_DMA_CHANNEL_4
3568 * @arg @ref LL_DMA_CHANNEL_5
3569 * @arg @ref LL_DMA_CHANNEL_6
3570 * @arg @ref LL_DMA_CHANNEL_7
3571 * @retval None.
3572 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)3573 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
3574 {
3575 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
3576 }
3577
3578 /**
3579 * @brief Check if DMA Channel privilege is enabled.
3580 * @note This API is used for all available DMA channels.
3581 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
3582 * @param DMAx DMAx Instance
3583 * @param Channel This parameter can be one of the following values:
3584 * @arg @ref LL_DMA_CHANNEL_0
3585 * @arg @ref LL_DMA_CHANNEL_1
3586 * @arg @ref LL_DMA_CHANNEL_2
3587 * @arg @ref LL_DMA_CHANNEL_3
3588 * @arg @ref LL_DMA_CHANNEL_4
3589 * @arg @ref LL_DMA_CHANNEL_5
3590 * @arg @ref LL_DMA_CHANNEL_6
3591 * @arg @ref LL_DMA_CHANNEL_7
3592 * @retval State of bit (1 or 0).
3593 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)3594 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
3595 {
3596 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
3597 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3598 }
3599 #endif /* DMA_PRIVCFGR_PRIV0 */
3600 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3601 /**
3602 * @brief Enable the DMA channel lock attributes.
3603 * @note This API is used for all available DMA channels.
3604 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
3605 * @param DMAx DMAx Instance
3606 * @param Channel This parameter can be one of the following values:
3607 * @arg @ref LL_DMA_CHANNEL_0
3608 * @arg @ref LL_DMA_CHANNEL_1
3609 * @arg @ref LL_DMA_CHANNEL_2
3610 * @arg @ref LL_DMA_CHANNEL_3
3611 * @arg @ref LL_DMA_CHANNEL_4
3612 * @arg @ref LL_DMA_CHANNEL_5
3613 * @arg @ref LL_DMA_CHANNEL_6
3614 * @arg @ref LL_DMA_CHANNEL_7
3615 * @retval None.
3616 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)3617 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
3618 {
3619 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
3620 }
3621 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3622 #if defined (DMA_RCFGLOCKR_LOCK0)
3623 /**
3624 * @brief Check if DMA channel attributes are locked.
3625 * @note This API is used for all available DMA channels.
3626 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
3627 * @param DMAx DMAx Instance
3628 * @param Channel This parameter can be one of the following values:
3629 * @arg @ref LL_DMA_CHANNEL_0
3630 * @arg @ref LL_DMA_CHANNEL_1
3631 * @arg @ref LL_DMA_CHANNEL_2
3632 * @arg @ref LL_DMA_CHANNEL_3
3633 * @arg @ref LL_DMA_CHANNEL_4
3634 * @arg @ref LL_DMA_CHANNEL_5
3635 * @arg @ref LL_DMA_CHANNEL_6
3636 * @arg @ref LL_DMA_CHANNEL_7
3637 * @retval State of bit (1 or 0).
3638 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)3639 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
3640 {
3641 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
3642 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3643 }
3644
3645 #endif /* DMA_RCFGLOCKR_LOCK0 */
3646 /**
3647 * @}
3648 */
3649
3650 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
3651 * @{
3652 */
3653
3654 /**
3655 * @brief Clear trigger overrun flag.
3656 * @note This API is used for all available DMA channels.
3657 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
3658 * @param DMAx DMAx Instance
3659 * @param Channel This parameter can be one of the following values:
3660 * @arg @ref LL_DMA_CHANNEL_0
3661 * @arg @ref LL_DMA_CHANNEL_1
3662 * @arg @ref LL_DMA_CHANNEL_2
3663 * @arg @ref LL_DMA_CHANNEL_3
3664 * @arg @ref LL_DMA_CHANNEL_4
3665 * @arg @ref LL_DMA_CHANNEL_5
3666 * @arg @ref LL_DMA_CHANNEL_6
3667 * @arg @ref LL_DMA_CHANNEL_7
3668 * @retval None.
3669 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)3670 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
3671 {
3672 uint32_t dma_base_addr = (uint32_t)DMAx;
3673 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
3674 }
3675
3676 /**
3677 * @brief Clear suspension flag.
3678 * @note This API is used for all available DMA channels.
3679 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
3680 * @param DMAx DMAx Instance
3681 * @param Channel This parameter can be one of the following values:
3682 * @arg @ref LL_DMA_CHANNEL_0
3683 * @arg @ref LL_DMA_CHANNEL_1
3684 * @arg @ref LL_DMA_CHANNEL_2
3685 * @arg @ref LL_DMA_CHANNEL_3
3686 * @arg @ref LL_DMA_CHANNEL_4
3687 * @arg @ref LL_DMA_CHANNEL_5
3688 * @arg @ref LL_DMA_CHANNEL_6
3689 * @arg @ref LL_DMA_CHANNEL_7
3690 * @retval None.
3691 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)3692 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
3693 {
3694 uint32_t dma_base_addr = (uint32_t)DMAx;
3695 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
3696 }
3697
3698 /**
3699 * @brief Clear user setting error flag.
3700 * @note This API is used for all available DMA channels.
3701 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
3702 * @param DMAx DMAx Instance
3703 * @param Channel This parameter can be one of the following values:
3704 * @arg @ref LL_DMA_CHANNEL_0
3705 * @arg @ref LL_DMA_CHANNEL_1
3706 * @arg @ref LL_DMA_CHANNEL_2
3707 * @arg @ref LL_DMA_CHANNEL_3
3708 * @arg @ref LL_DMA_CHANNEL_4
3709 * @arg @ref LL_DMA_CHANNEL_5
3710 * @arg @ref LL_DMA_CHANNEL_6
3711 * @arg @ref LL_DMA_CHANNEL_7
3712 * @retval None.
3713 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)3714 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
3715 {
3716 uint32_t dma_base_addr = (uint32_t)DMAx;
3717 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
3718 }
3719
3720 /**
3721 * @brief Clear link transfer error flag.
3722 * @note This API is used for all available DMA channels.
3723 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
3724 * @param DMAx DMAx Instance
3725 * @param Channel This parameter can be one of the following values:
3726 * @arg @ref LL_DMA_CHANNEL_0
3727 * @arg @ref LL_DMA_CHANNEL_1
3728 * @arg @ref LL_DMA_CHANNEL_2
3729 * @arg @ref LL_DMA_CHANNEL_3
3730 * @arg @ref LL_DMA_CHANNEL_4
3731 * @arg @ref LL_DMA_CHANNEL_5
3732 * @arg @ref LL_DMA_CHANNEL_6
3733 * @arg @ref LL_DMA_CHANNEL_7
3734 * @retval None.
3735 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)3736 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
3737 {
3738 uint32_t dma_base_addr = (uint32_t)DMAx;
3739 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
3740 }
3741
3742 /**
3743 * @brief Clear data transfer error flag.
3744 * @note This API is used for all available DMA channels.
3745 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
3746 * @param DMAx DMAx Instance
3747 * @param Channel This parameter can be one of the following values:
3748 * @arg @ref LL_DMA_CHANNEL_0
3749 * @arg @ref LL_DMA_CHANNEL_1
3750 * @arg @ref LL_DMA_CHANNEL_2
3751 * @arg @ref LL_DMA_CHANNEL_3
3752 * @arg @ref LL_DMA_CHANNEL_4
3753 * @arg @ref LL_DMA_CHANNEL_5
3754 * @arg @ref LL_DMA_CHANNEL_6
3755 * @arg @ref LL_DMA_CHANNEL_7
3756 * @retval None.
3757 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)3758 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
3759 {
3760 uint32_t dma_base_addr = (uint32_t)DMAx;
3761 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
3762 }
3763
3764 /**
3765 * @brief Clear half transfer flag.
3766 * @note This API is used for all available DMA channels.
3767 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
3768 * @param DMAx DMAx Instance
3769 * @param Channel This parameter can be one of the following values:
3770 * @arg @ref LL_DMA_CHANNEL_0
3771 * @arg @ref LL_DMA_CHANNEL_1
3772 * @arg @ref LL_DMA_CHANNEL_2
3773 * @arg @ref LL_DMA_CHANNEL_3
3774 * @arg @ref LL_DMA_CHANNEL_4
3775 * @arg @ref LL_DMA_CHANNEL_5
3776 * @arg @ref LL_DMA_CHANNEL_6
3777 * @arg @ref LL_DMA_CHANNEL_7
3778 * @retval None.
3779 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)3780 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
3781 {
3782 uint32_t dma_base_addr = (uint32_t)DMAx;
3783 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
3784 }
3785
3786 /**
3787 * @brief Clear transfer complete flag.
3788 * @note This API is used for all available DMA channels.
3789 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
3790 * @param DMAx DMAx Instance
3791 * @param Channel This parameter can be one of the following values:
3792 * @arg @ref LL_DMA_CHANNEL_0
3793 * @arg @ref LL_DMA_CHANNEL_1
3794 * @arg @ref LL_DMA_CHANNEL_2
3795 * @arg @ref LL_DMA_CHANNEL_3
3796 * @arg @ref LL_DMA_CHANNEL_4
3797 * @arg @ref LL_DMA_CHANNEL_5
3798 * @arg @ref LL_DMA_CHANNEL_6
3799 * @arg @ref LL_DMA_CHANNEL_7
3800 * @retval None.
3801 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)3802 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
3803 {
3804 uint32_t dma_base_addr = (uint32_t)DMAx;
3805 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
3806 }
3807
3808 /**
3809 * @brief Get trigger overrun flag.
3810 * @note This API is used for all available DMA channels.
3811 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
3812 * @param DMAx DMAx Instance
3813 * @param Channel This parameter can be one of the following values:
3814 * @arg @ref LL_DMA_CHANNEL_0
3815 * @arg @ref LL_DMA_CHANNEL_1
3816 * @arg @ref LL_DMA_CHANNEL_2
3817 * @arg @ref LL_DMA_CHANNEL_3
3818 * @arg @ref LL_DMA_CHANNEL_4
3819 * @arg @ref LL_DMA_CHANNEL_5
3820 * @arg @ref LL_DMA_CHANNEL_6
3821 * @arg @ref LL_DMA_CHANNEL_7
3822 * @retval State of bit (1 or 0).
3823 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)3824 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
3825 {
3826 uint32_t dma_base_addr = (uint32_t)DMAx;
3827 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
3828 == (DMA_CSR_TOF)) ? 1UL : 0UL);
3829 }
3830
3831 /**
3832 * @brief Get suspension flag.
3833 * @note This API is used for all available DMA channels.
3834 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
3835 * @param DMAx DMAx Instance
3836 * @param Channel This parameter can be one of the following values:
3837 * @arg @ref LL_DMA_CHANNEL_0
3838 * @arg @ref LL_DMA_CHANNEL_1
3839 * @arg @ref LL_DMA_CHANNEL_2
3840 * @arg @ref LL_DMA_CHANNEL_3
3841 * @arg @ref LL_DMA_CHANNEL_4
3842 * @arg @ref LL_DMA_CHANNEL_5
3843 * @arg @ref LL_DMA_CHANNEL_6
3844 * @arg @ref LL_DMA_CHANNEL_7
3845 * @retval State of bit (1 or 0).
3846 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)3847 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
3848 {
3849 uint32_t dma_base_addr = (uint32_t)DMAx;
3850 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
3851 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
3852 }
3853
3854 /**
3855 * @brief Get user setting error flag.
3856 * @note This API is used for all available DMA channels.
3857 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
3858 * @param DMAx DMAx Instance
3859 * @param Channel This parameter can be one of the following values:
3860 * @arg @ref LL_DMA_CHANNEL_0
3861 * @arg @ref LL_DMA_CHANNEL_1
3862 * @arg @ref LL_DMA_CHANNEL_2
3863 * @arg @ref LL_DMA_CHANNEL_3
3864 * @arg @ref LL_DMA_CHANNEL_4
3865 * @arg @ref LL_DMA_CHANNEL_5
3866 * @arg @ref LL_DMA_CHANNEL_6
3867 * @arg @ref LL_DMA_CHANNEL_7
3868 * @retval State of bit (1 or 0).
3869 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)3870 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
3871 {
3872 uint32_t dma_base_addr = (uint32_t)DMAx;
3873 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
3874 == (DMA_CSR_USEF)) ? 1UL : 0UL);
3875 }
3876
3877 /**
3878 * @brief Get user setting error flag.
3879 * @note This API is used for all available DMA channels.
3880 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
3881 * @param DMAx DMAx Instance
3882 * @param Channel This parameter can be one of the following values:
3883 * @arg @ref LL_DMA_CHANNEL_0
3884 * @arg @ref LL_DMA_CHANNEL_1
3885 * @arg @ref LL_DMA_CHANNEL_2
3886 * @arg @ref LL_DMA_CHANNEL_3
3887 * @arg @ref LL_DMA_CHANNEL_4
3888 * @arg @ref LL_DMA_CHANNEL_5
3889 * @arg @ref LL_DMA_CHANNEL_6
3890 * @arg @ref LL_DMA_CHANNEL_7
3891 * @retval State of bit (1 or 0).
3892 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)3893 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
3894 {
3895 uint32_t dma_base_addr = (uint32_t)DMAx;
3896 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
3897 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
3898 }
3899
3900 /**
3901 * @brief Get data transfer error flag.
3902 * @note This API is used for all available DMA channels.
3903 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
3904 * @param DMAx DMAx Instance
3905 * @param Channel This parameter can be one of the following values:
3906 * @arg @ref LL_DMA_CHANNEL_0
3907 * @arg @ref LL_DMA_CHANNEL_1
3908 * @arg @ref LL_DMA_CHANNEL_2
3909 * @arg @ref LL_DMA_CHANNEL_3
3910 * @arg @ref LL_DMA_CHANNEL_4
3911 * @arg @ref LL_DMA_CHANNEL_5
3912 * @arg @ref LL_DMA_CHANNEL_6
3913 * @arg @ref LL_DMA_CHANNEL_7
3914 * @retval State of bit (1 or 0).
3915 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)3916 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
3917 {
3918 uint32_t dma_base_addr = (uint32_t)DMAx;
3919 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
3920 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
3921 }
3922
3923 /**
3924 * @brief Get half transfer flag.
3925 * @note This API is used for all available DMA channels.
3926 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
3927 * @param DMAx DMAx Instance
3928 * @param Channel This parameter can be one of the following values:
3929 * @arg @ref LL_DMA_CHANNEL_0
3930 * @arg @ref LL_DMA_CHANNEL_1
3931 * @arg @ref LL_DMA_CHANNEL_2
3932 * @arg @ref LL_DMA_CHANNEL_3
3933 * @arg @ref LL_DMA_CHANNEL_4
3934 * @arg @ref LL_DMA_CHANNEL_5
3935 * @arg @ref LL_DMA_CHANNEL_6
3936 * @arg @ref LL_DMA_CHANNEL_7
3937 * @retval State of bit (1 or 0).
3938 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)3939 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
3940 {
3941 uint32_t dma_base_addr = (uint32_t)DMAx;
3942 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
3943 == (DMA_CSR_HTF)) ? 1UL : 0UL);
3944 }
3945
3946 /**
3947 * @brief Get transfer complete flag.
3948 * @note This API is used for all available DMA channels.
3949 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
3950 * @param DMAx DMAx Instance
3951 * @param Channel This parameter can be one of the following values:
3952 * @arg @ref LL_DMA_CHANNEL_0
3953 * @arg @ref LL_DMA_CHANNEL_1
3954 * @arg @ref LL_DMA_CHANNEL_2
3955 * @arg @ref LL_DMA_CHANNEL_3
3956 * @arg @ref LL_DMA_CHANNEL_4
3957 * @arg @ref LL_DMA_CHANNEL_5
3958 * @arg @ref LL_DMA_CHANNEL_6
3959 * @arg @ref LL_DMA_CHANNEL_7
3960 * @retval State of bit (1 or 0).
3961 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)3962 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
3963 {
3964 uint32_t dma_base_addr = (uint32_t)DMAx;
3965 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
3966 == (DMA_CSR_TCF)) ? 1UL : 0UL);
3967 }
3968
3969 /**
3970 * @brief Get idle flag.
3971 * @note This API is used for all available DMA channels.
3972 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
3973 * @param DMAx DMAx Instance
3974 * @param Channel This parameter can be one of the following values:
3975 * @arg @ref LL_DMA_CHANNEL_0
3976 * @arg @ref LL_DMA_CHANNEL_1
3977 * @arg @ref LL_DMA_CHANNEL_2
3978 * @arg @ref LL_DMA_CHANNEL_3
3979 * @arg @ref LL_DMA_CHANNEL_4
3980 * @arg @ref LL_DMA_CHANNEL_5
3981 * @arg @ref LL_DMA_CHANNEL_6
3982 * @arg @ref LL_DMA_CHANNEL_7
3983 * @retval State of bit (1 or 0).
3984 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)3985 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
3986 {
3987 uint32_t dma_base_addr = (uint32_t)DMAx;
3988 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
3989 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
3990 }
3991
3992 /**
3993 * @brief Check if nsecure masked interrupt is active.
3994 * @note This API is used for all available DMA channels.
3995 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
3996 * @param DMAx DMAx Instance
3997 * @param Channel This parameter can be one of the following values:
3998 * @arg @ref LL_DMA_CHANNEL_0
3999 * @arg @ref LL_DMA_CHANNEL_1
4000 * @arg @ref LL_DMA_CHANNEL_2
4001 * @arg @ref LL_DMA_CHANNEL_3
4002 * @arg @ref LL_DMA_CHANNEL_4
4003 * @arg @ref LL_DMA_CHANNEL_5
4004 * @arg @ref LL_DMA_CHANNEL_6
4005 * @arg @ref LL_DMA_CHANNEL_7
4006 * @retval State of bit (1 or 0).
4007 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)4008 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
4009 {
4010 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
4011 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
4012 }
4013
4014 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4015 /**
4016 * @brief Check if secure masked interrupt is active.
4017 * @note This API is used for all available DMA channels.
4018 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
4019 * @param DMAx DMAx Instance
4020 * @param Channel This parameter can be one of the following values:
4021 * @arg @ref LL_DMA_CHANNEL_0
4022 * @arg @ref LL_DMA_CHANNEL_1
4023 * @arg @ref LL_DMA_CHANNEL_2
4024 * @arg @ref LL_DMA_CHANNEL_3
4025 * @arg @ref LL_DMA_CHANNEL_4
4026 * @arg @ref LL_DMA_CHANNEL_5
4027 * @arg @ref LL_DMA_CHANNEL_6
4028 * @arg @ref LL_DMA_CHANNEL_7
4029 * @retval State of bit (1 or 0).
4030 */
LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef * DMAx,uint32_t Channel)4031 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
4032 {
4033 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
4034 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
4035 }
4036 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4037 /**
4038 * @}
4039 */
4040
4041 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
4042 * @{
4043 */
4044
4045 /**
4046 * @brief Enable trigger overrun interrupt.
4047 * @note This API is used for all available DMA channels.
4048 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
4049 * @param DMAx DMAx Instance
4050 * @param Channel This parameter can be one of the following values:
4051 * @arg @ref LL_DMA_CHANNEL_0
4052 * @arg @ref LL_DMA_CHANNEL_1
4053 * @arg @ref LL_DMA_CHANNEL_2
4054 * @arg @ref LL_DMA_CHANNEL_3
4055 * @arg @ref LL_DMA_CHANNEL_4
4056 * @arg @ref LL_DMA_CHANNEL_5
4057 * @arg @ref LL_DMA_CHANNEL_6
4058 * @arg @ref LL_DMA_CHANNEL_7
4059 * @retval None.
4060 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4061 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4062 {
4063 uint32_t dma_base_addr = (uint32_t)DMAx;
4064 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
4065 }
4066
4067 /**
4068 * @brief Enable suspension interrupt.
4069 * @note This API is used for all available DMA channels.
4070 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
4071 * @param DMAx DMAx Instance
4072 * @param Channel This parameter can be one of the following values:
4073 * @arg @ref LL_DMA_CHANNEL_0
4074 * @arg @ref LL_DMA_CHANNEL_1
4075 * @arg @ref LL_DMA_CHANNEL_2
4076 * @arg @ref LL_DMA_CHANNEL_3
4077 * @arg @ref LL_DMA_CHANNEL_4
4078 * @arg @ref LL_DMA_CHANNEL_5
4079 * @arg @ref LL_DMA_CHANNEL_6
4080 * @arg @ref LL_DMA_CHANNEL_7
4081 * @retval None.
4082 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4083 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4084 {
4085 uint32_t dma_base_addr = (uint32_t)DMAx;
4086 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
4087 }
4088
4089 /**
4090 * @brief Enable user setting error interrupt.
4091 * @note This API is used for all available DMA channels.
4092 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
4093 * @param DMAx DMAx Instance
4094 * @param Channel This parameter can be one of the following values:
4095 * @arg @ref LL_DMA_CHANNEL_0
4096 * @arg @ref LL_DMA_CHANNEL_1
4097 * @arg @ref LL_DMA_CHANNEL_2
4098 * @arg @ref LL_DMA_CHANNEL_3
4099 * @arg @ref LL_DMA_CHANNEL_4
4100 * @arg @ref LL_DMA_CHANNEL_5
4101 * @arg @ref LL_DMA_CHANNEL_6
4102 * @arg @ref LL_DMA_CHANNEL_7
4103 * @retval None.
4104 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4105 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4106 {
4107 uint32_t dma_base_addr = (uint32_t)DMAx;
4108 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
4109 }
4110
4111 /**
4112 * @brief Enable update link transfer error interrupt.
4113 * @note This API is used for all available DMA channels.
4114 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
4115 * @param DMAx DMAx Instance
4116 * @param Channel This parameter can be one of the following values:
4117 * @arg @ref LL_DMA_CHANNEL_0
4118 * @arg @ref LL_DMA_CHANNEL_1
4119 * @arg @ref LL_DMA_CHANNEL_2
4120 * @arg @ref LL_DMA_CHANNEL_3
4121 * @arg @ref LL_DMA_CHANNEL_4
4122 * @arg @ref LL_DMA_CHANNEL_5
4123 * @arg @ref LL_DMA_CHANNEL_6
4124 * @arg @ref LL_DMA_CHANNEL_7
4125 * @retval None.
4126 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4127 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4128 {
4129 uint32_t dma_base_addr = (uint32_t)DMAx;
4130 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
4131 }
4132
4133 /**
4134 * @brief Enable data transfer error interrupt.
4135 * @note This API is used for all available DMA channels.
4136 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
4137 * @param DMAx DMAx Instance
4138 * @param Channel This parameter can be one of the following values:
4139 * @arg @ref LL_DMA_CHANNEL_0
4140 * @arg @ref LL_DMA_CHANNEL_1
4141 * @arg @ref LL_DMA_CHANNEL_2
4142 * @arg @ref LL_DMA_CHANNEL_3
4143 * @arg @ref LL_DMA_CHANNEL_4
4144 * @arg @ref LL_DMA_CHANNEL_5
4145 * @arg @ref LL_DMA_CHANNEL_6
4146 * @arg @ref LL_DMA_CHANNEL_7
4147 * @retval None.
4148 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4149 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4150 {
4151 uint32_t dma_base_addr = (uint32_t)DMAx;
4152 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
4153 }
4154
4155 /**
4156 * @brief Enable half transfer complete interrupt.
4157 * @note This API is used for all available DMA channels.
4158 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
4159 * @param DMAx DMAx Instance
4160 * @param Channel This parameter can be one of the following values:
4161 * @arg @ref LL_DMA_CHANNEL_0
4162 * @arg @ref LL_DMA_CHANNEL_1
4163 * @arg @ref LL_DMA_CHANNEL_2
4164 * @arg @ref LL_DMA_CHANNEL_3
4165 * @arg @ref LL_DMA_CHANNEL_4
4166 * @arg @ref LL_DMA_CHANNEL_5
4167 * @arg @ref LL_DMA_CHANNEL_6
4168 * @arg @ref LL_DMA_CHANNEL_7
4169 * @retval None.
4170 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4171 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4172 {
4173 uint32_t dma_base_addr = (uint32_t)DMAx;
4174 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
4175 }
4176
4177 /**
4178 * @brief Enable transfer complete interrupt.
4179 * @note This API is used for all available DMA channels.
4180 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
4181 * @param DMAx DMAx Instance
4182 * @param Channel This parameter can be one of the following values:
4183 * @arg @ref LL_DMA_CHANNEL_0
4184 * @arg @ref LL_DMA_CHANNEL_1
4185 * @arg @ref LL_DMA_CHANNEL_2
4186 * @arg @ref LL_DMA_CHANNEL_3
4187 * @arg @ref LL_DMA_CHANNEL_4
4188 * @arg @ref LL_DMA_CHANNEL_5
4189 * @arg @ref LL_DMA_CHANNEL_6
4190 * @arg @ref LL_DMA_CHANNEL_7
4191 * @retval None.
4192 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4193 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4194 {
4195 uint32_t dma_base_addr = (uint32_t)DMAx;
4196 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
4197 }
4198
4199 /**
4200 * @brief Disable trigger overrun interrupt.
4201 * @note This API is used for all available DMA channels.
4202 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
4203 * @param DMAx DMAx Instance
4204 * @param Channel This parameter can be one of the following values:
4205 * @arg @ref LL_DMA_CHANNEL_0
4206 * @arg @ref LL_DMA_CHANNEL_1
4207 * @arg @ref LL_DMA_CHANNEL_2
4208 * @arg @ref LL_DMA_CHANNEL_3
4209 * @arg @ref LL_DMA_CHANNEL_4
4210 * @arg @ref LL_DMA_CHANNEL_5
4211 * @arg @ref LL_DMA_CHANNEL_6
4212 * @arg @ref LL_DMA_CHANNEL_7
4213 * @retval None.
4214 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4215 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4216 {
4217 uint32_t dma_base_addr = (uint32_t)DMAx;
4218 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
4219 }
4220
4221 /**
4222 * @brief Disable suspension interrupt.
4223 * @note This API is used for all available DMA channels.
4224 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
4225 * @param DMAx DMAx Instance
4226 * @param Channel This parameter can be one of the following values:
4227 * @arg @ref LL_DMA_CHANNEL_0
4228 * @arg @ref LL_DMA_CHANNEL_1
4229 * @arg @ref LL_DMA_CHANNEL_2
4230 * @arg @ref LL_DMA_CHANNEL_3
4231 * @arg @ref LL_DMA_CHANNEL_4
4232 * @arg @ref LL_DMA_CHANNEL_5
4233 * @arg @ref LL_DMA_CHANNEL_6
4234 * @arg @ref LL_DMA_CHANNEL_7
4235 * @retval None.
4236 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4237 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4238 {
4239 uint32_t dma_base_addr = (uint32_t)DMAx;
4240 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
4241 }
4242
4243 /**
4244 * @brief Disable user setting error interrupt.
4245 * @note This API is used for all available DMA channels.
4246 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
4247 * @param DMAx DMAx Instance
4248 * @param Channel This parameter can be one of the following values:
4249 * @arg @ref LL_DMA_CHANNEL_0
4250 * @arg @ref LL_DMA_CHANNEL_1
4251 * @arg @ref LL_DMA_CHANNEL_2
4252 * @arg @ref LL_DMA_CHANNEL_3
4253 * @arg @ref LL_DMA_CHANNEL_4
4254 * @arg @ref LL_DMA_CHANNEL_5
4255 * @arg @ref LL_DMA_CHANNEL_6
4256 * @arg @ref LL_DMA_CHANNEL_7
4257 * @retval None.
4258 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4259 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4260 {
4261 uint32_t dma_base_addr = (uint32_t)DMAx;
4262 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
4263 }
4264
4265 /**
4266 * @brief Disable update link transfer error interrupt.
4267 * @note This API is used for all available DMA channels.
4268 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
4269 * @param DMAx DMAx Instance
4270 * @param Channel This parameter can be one of the following values:
4271 * @arg @ref LL_DMA_CHANNEL_0
4272 * @arg @ref LL_DMA_CHANNEL_1
4273 * @arg @ref LL_DMA_CHANNEL_2
4274 * @arg @ref LL_DMA_CHANNEL_3
4275 * @arg @ref LL_DMA_CHANNEL_4
4276 * @arg @ref LL_DMA_CHANNEL_5
4277 * @arg @ref LL_DMA_CHANNEL_6
4278 * @arg @ref LL_DMA_CHANNEL_7
4279 * @retval None.
4280 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4281 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4282 {
4283 uint32_t dma_base_addr = (uint32_t)DMAx;
4284 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
4285 }
4286
4287 /**
4288 * @brief Disable data transfer error interrupt.
4289 * @note This API is used for all available DMA channels.
4290 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
4291 * @param DMAx DMAx Instance
4292 * @param Channel This parameter can be one of the following values:
4293 * @arg @ref LL_DMA_CHANNEL_0
4294 * @arg @ref LL_DMA_CHANNEL_1
4295 * @arg @ref LL_DMA_CHANNEL_2
4296 * @arg @ref LL_DMA_CHANNEL_3
4297 * @arg @ref LL_DMA_CHANNEL_4
4298 * @arg @ref LL_DMA_CHANNEL_5
4299 * @arg @ref LL_DMA_CHANNEL_6
4300 * @arg @ref LL_DMA_CHANNEL_7
4301 * @retval None.
4302 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4303 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4304 {
4305 uint32_t dma_base_addr = (uint32_t)DMAx;
4306 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
4307 }
4308
4309 /**
4310 * @brief Disable half transfer complete interrupt.
4311 * @note This API is used for all available DMA channels.
4312 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
4313 * @param DMAx DMAx Instance
4314 * @param Channel This parameter can be one of the following values:
4315 * @arg @ref LL_DMA_CHANNEL_0
4316 * @arg @ref LL_DMA_CHANNEL_1
4317 * @arg @ref LL_DMA_CHANNEL_2
4318 * @arg @ref LL_DMA_CHANNEL_3
4319 * @arg @ref LL_DMA_CHANNEL_4
4320 * @arg @ref LL_DMA_CHANNEL_5
4321 * @arg @ref LL_DMA_CHANNEL_6
4322 * @arg @ref LL_DMA_CHANNEL_7
4323 * @retval None.
4324 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4325 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4326 {
4327 uint32_t dma_base_addr = (uint32_t)DMAx;
4328 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
4329 }
4330
4331 /**
4332 * @brief Disable transfer complete interrupt.
4333 * @note This API is used for all available DMA channels.
4334 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
4335 * @param DMAx DMAx Instance
4336 * @param Channel This parameter can be one of the following values:
4337 * @arg @ref LL_DMA_CHANNEL_0
4338 * @arg @ref LL_DMA_CHANNEL_1
4339 * @arg @ref LL_DMA_CHANNEL_2
4340 * @arg @ref LL_DMA_CHANNEL_3
4341 * @arg @ref LL_DMA_CHANNEL_4
4342 * @arg @ref LL_DMA_CHANNEL_5
4343 * @arg @ref LL_DMA_CHANNEL_6
4344 * @arg @ref LL_DMA_CHANNEL_7
4345 * @retval None.
4346 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4347 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4348 {
4349 uint32_t dma_base_addr = (uint32_t)DMAx;
4350 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
4351 }
4352
4353 /**
4354 * @brief Check if trigger overrun interrupt is enabled.
4355 * @note This API is used for all available DMA channels.
4356 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
4357 * @param DMAx DMAx Instance
4358 * @param Channel This parameter can be one of the following values:
4359 * @arg @ref LL_DMA_CHANNEL_0
4360 * @arg @ref LL_DMA_CHANNEL_1
4361 * @arg @ref LL_DMA_CHANNEL_2
4362 * @arg @ref LL_DMA_CHANNEL_3
4363 * @arg @ref LL_DMA_CHANNEL_4
4364 * @arg @ref LL_DMA_CHANNEL_5
4365 * @arg @ref LL_DMA_CHANNEL_6
4366 * @arg @ref LL_DMA_CHANNEL_7
4367 * @retval State of bit (1 or 0).
4368 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4369 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4370 {
4371 uint32_t dma_base_addr = (uint32_t)DMAx;
4372 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
4373 == DMA_CCR_TOIE) ? 1UL : 0UL);
4374 }
4375
4376 /**
4377 * @brief Check if suspension interrupt is enabled.
4378 * @note This API is used for all available DMA channels.
4379 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
4380 * @param DMAx DMAx Instance
4381 * @param Channel This parameter can be one of the following values:
4382 * @arg @ref LL_DMA_CHANNEL_0
4383 * @arg @ref LL_DMA_CHANNEL_1
4384 * @arg @ref LL_DMA_CHANNEL_2
4385 * @arg @ref LL_DMA_CHANNEL_3
4386 * @arg @ref LL_DMA_CHANNEL_4
4387 * @arg @ref LL_DMA_CHANNEL_5
4388 * @arg @ref LL_DMA_CHANNEL_6
4389 * @arg @ref LL_DMA_CHANNEL_7
4390 * @retval State of bit (1 or 0).
4391 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4392 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4393 {
4394 uint32_t dma_base_addr = (uint32_t)DMAx;
4395 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
4396 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
4397 }
4398
4399 /**
4400 * @brief Check if user setting error interrupt is enabled.
4401 * @note This API is used for all available DMA channels.
4402 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
4403 * @param DMAx DMAx Instance
4404 * @param Channel This parameter can be one of the following values:
4405 * @arg @ref LL_DMA_CHANNEL_0
4406 * @arg @ref LL_DMA_CHANNEL_1
4407 * @arg @ref LL_DMA_CHANNEL_2
4408 * @arg @ref LL_DMA_CHANNEL_3
4409 * @arg @ref LL_DMA_CHANNEL_4
4410 * @arg @ref LL_DMA_CHANNEL_5
4411 * @arg @ref LL_DMA_CHANNEL_6
4412 * @arg @ref LL_DMA_CHANNEL_7
4413 * @retval State of bit (1 or 0).
4414 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4415 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4416 {
4417 uint32_t dma_base_addr = (uint32_t)DMAx;
4418 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
4419 == DMA_CCR_USEIE) ? 1UL : 0UL);
4420 }
4421
4422 /**
4423 * @brief Check if update link transfer error interrupt is enabled.
4424 * @note This API is used for all available DMA channels.
4425 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
4426 * @param DMAx DMAx Instance
4427 * @param Channel This parameter can be one of the following values:
4428 * @arg @ref LL_DMA_CHANNEL_0
4429 * @arg @ref LL_DMA_CHANNEL_1
4430 * @arg @ref LL_DMA_CHANNEL_2
4431 * @arg @ref LL_DMA_CHANNEL_3
4432 * @arg @ref LL_DMA_CHANNEL_4
4433 * @arg @ref LL_DMA_CHANNEL_5
4434 * @arg @ref LL_DMA_CHANNEL_6
4435 * @arg @ref LL_DMA_CHANNEL_7
4436 * @retval State of bit (1 or 0).
4437 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4438 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4439 {
4440 uint32_t dma_base_addr = (uint32_t)DMAx;
4441 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
4442 == DMA_CCR_ULEIE) ? 1UL : 0UL);
4443 }
4444
4445 /**
4446 * @brief Check if data transfer error interrupt is enabled.
4447 * @note This API is used for all available DMA channels.
4448 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
4449 * @param DMAx DMAx Instance
4450 * @param Channel This parameter can be one of the following values:
4451 * @arg @ref LL_DMA_CHANNEL_0
4452 * @arg @ref LL_DMA_CHANNEL_1
4453 * @arg @ref LL_DMA_CHANNEL_2
4454 * @arg @ref LL_DMA_CHANNEL_3
4455 * @arg @ref LL_DMA_CHANNEL_4
4456 * @arg @ref LL_DMA_CHANNEL_5
4457 * @arg @ref LL_DMA_CHANNEL_6
4458 * @arg @ref LL_DMA_CHANNEL_7
4459 * @retval State of bit (1 or 0).
4460 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4461 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4462 {
4463 uint32_t dma_base_addr = (uint32_t)DMAx;
4464 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
4465 == DMA_CCR_DTEIE) ? 1UL : 0UL);
4466 }
4467
4468 /**
4469 * @brief Check if half transfer complete interrupt is enabled.
4470 * @note This API is used for all available DMA channels.
4471 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
4472 * @param DMAx DMAx Instance
4473 * @param Channel This parameter can be one of the following values:
4474 * @arg @ref LL_DMA_CHANNEL_0
4475 * @arg @ref LL_DMA_CHANNEL_1
4476 * @arg @ref LL_DMA_CHANNEL_2
4477 * @arg @ref LL_DMA_CHANNEL_3
4478 * @arg @ref LL_DMA_CHANNEL_4
4479 * @arg @ref LL_DMA_CHANNEL_5
4480 * @arg @ref LL_DMA_CHANNEL_6
4481 * @arg @ref LL_DMA_CHANNEL_7
4482 * @retval State of bit (1 or 0).
4483 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4484 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4485 {
4486 uint32_t dma_base_addr = (uint32_t)DMAx;
4487 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
4488 == DMA_CCR_HTIE) ? 1UL : 0UL);
4489 }
4490
4491 /**
4492 * @brief Check if transfer complete interrupt is enabled.
4493 * @note This API is used for all available DMA channels.
4494 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
4495 * @param DMAx DMAx Instance
4496 * @param Channel This parameter can be one of the following values:
4497 * @arg @ref LL_DMA_CHANNEL_0
4498 * @arg @ref LL_DMA_CHANNEL_1
4499 * @arg @ref LL_DMA_CHANNEL_2
4500 * @arg @ref LL_DMA_CHANNEL_3
4501 * @arg @ref LL_DMA_CHANNEL_4
4502 * @arg @ref LL_DMA_CHANNEL_5
4503 * @arg @ref LL_DMA_CHANNEL_6
4504 * @arg @ref LL_DMA_CHANNEL_7
4505 * @retval State of bit (1 or 0).
4506 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4507 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4508 {
4509 uint32_t dma_base_addr = (uint32_t)DMAx;
4510 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
4511 == DMA_CCR_TCIE) ? 1UL : 0UL);
4512 }
4513 /**
4514 * @}
4515 */
4516
4517 #if defined (USE_FULL_LL_DRIVER)
4518 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
4519 * @{
4520 */
4521 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
4522 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
4523
4524 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
4525 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
4526 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
4527
4528 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
4529 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
4530 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
4531
4532 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
4533 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
4534 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
4535 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
4536 /**
4537 * @}
4538 */
4539 #endif /* USE_FULL_LL_DRIVER */
4540
4541 /**
4542 * @}
4543 */
4544
4545 /**
4546 * @}
4547 */
4548
4549 #endif /* GPDMA1 */
4550
4551 /**
4552 * @}
4553 */
4554
4555 #ifdef __cplusplus
4556 }
4557 #endif /* __cplusplus */
4558
4559 #endif /* STM32WBAxx_LL_DMA_H */
4560
4561
