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Searched refs:BWTR (Results 1 – 25 of 154) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c424 FMC_Bank1E->BWTR[2] = 0x0fffffff; in SystemInit_ExtMemCtl()
430 FMC_Bank1E->BWTR[2] = 0x0fffffff; in SystemInit_ExtMemCtl()
711 FMC_Bank1E->BWTR[2] = 0x0fffffff; in SystemInit_ExtMemCtl()
719 FMC_Bank1E->BWTR[2] = 0x0fffffff; in SystemInit_ExtMemCtl()
728 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; in SystemInit_ExtMemCtl()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c364 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
487 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
494 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
503 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c262 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
334 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
342 Device->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c315 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
400 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
410 Device->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c299 ExDevice->BWTR[Bank] = 0x000FFFFFU; in FMC_NORSRAM_DeInit()
405 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
418 Device->BWTR[Bank] = 0x000FFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c316 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
401 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
407 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
415 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c328 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
433 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
442 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c333 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
438 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
447 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c333 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
438 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
447 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c299 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
372 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
380 Device->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c313 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
401 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fsmc.c366 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
451 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
459 Device->BWTR[Bank] = 0x0FFFFFFFU; in FSMC_NORSRAM_Extended_Timing_Init()
Dstm32f4xx_ll_fmc.c385 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
470 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
478 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c311 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
392 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
400 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_fmc.c304 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
389 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
398 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c311 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
393 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
401 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c352 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
457 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
466 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dsystem_stm32f2xx.c327 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; in SystemInit_ExtMemCtl()
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dsystem_stm32l1xx.c377 FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; in SystemInit_ExtMemCtl()
Dstm32l151xd.h347 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ member
Dstm32l152xd.h348 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ member
Dstm32l162xd.h369 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ member
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f100xe.h386 __IO uint32_t BWTR[7]; member
Dstm32f101xg.h372 __IO uint32_t BWTR[7]; member
Dstm32f101xe.h360 __IO uint32_t BWTR[7]; member

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