1 /** 2 ****************************************************************************** 3 * @file stm32l151xd.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32L1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2017-2021 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 /** @addtogroup CMSIS 28 * @{ 29 */ 30 31 /** @addtogroup stm32l151xd 32 * @{ 33 */ 34 35 #ifndef __STM32L151xD_H 36 #define __STM32L151xD_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 /** @addtogroup Configuration_section_for_CMSIS 44 * @{ 45 */ 46 /** 47 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 48 */ 49 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ 50 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ 51 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ 52 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 53 54 /** 55 * @} 56 */ 57 58 /** @addtogroup Peripheral_interrupt_number_definition 59 * @{ 60 */ 61 62 /** 63 * @brief STM32L1xx Interrupt Number Definition, according to the selected device 64 * in @ref Library_configuration_section 65 */ 66 67 /*!< Interrupt Number Definition */ 68 typedef enum 69 { 70 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ 71 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 72 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 73 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 74 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 75 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 76 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 77 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 78 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 79 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 80 81 /****** STM32L specific Interrupt Numbers ***********************************************************/ 82 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 83 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 84 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 85 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ 86 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 87 RCC_IRQn = 5, /*!< RCC global Interrupt */ 88 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 89 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 90 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 91 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 92 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 93 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 94 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 95 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 96 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 97 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 98 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 99 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 100 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 101 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ 102 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ 103 DAC_IRQn = 21, /*!< DAC Interrupt */ 104 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ 105 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 106 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ 107 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ 108 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ 109 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 110 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 111 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 112 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 113 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 114 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 115 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 116 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 117 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 118 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 119 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 120 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 121 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 122 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 123 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ 124 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ 125 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ 126 SDIO_IRQn = 45, /*!< SDIO global Interrupt */ 127 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ 128 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ 129 UART4_IRQn = 48, /*!< UART4 global Interrupt */ 130 UART5_IRQn = 49, /*!< UART5 global Interrupt */ 131 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ 132 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ 133 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ 134 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ 135 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ 136 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ 137 } IRQn_Type; 138 139 /** 140 * @} 141 */ 142 143 #include "core_cm3.h" 144 #include "system_stm32l1xx.h" 145 #include <stdint.h> 146 147 /** @addtogroup Peripheral_registers_structures 148 * @{ 149 */ 150 151 /** 152 * @brief Analog to Digital Converter 153 */ 154 155 typedef struct 156 { 157 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ 158 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ 159 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ 160 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 161 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 162 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ 163 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ 164 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ 165 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ 166 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ 167 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ 168 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ 169 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 170 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 171 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 172 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 173 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ 174 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ 175 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ 176 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ 177 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ 178 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ 179 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ 180 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ 181 } ADC_TypeDef; 182 183 typedef struct 184 { 185 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ 186 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 187 } ADC_Common_TypeDef; 188 189 /** 190 * @brief Comparator 191 */ 192 193 typedef struct 194 { 195 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 196 } COMP_TypeDef; 197 198 typedef struct 199 { 200 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 201 } COMP_Common_TypeDef; 202 203 /** 204 * @brief CRC calculation unit 205 */ 206 207 typedef struct 208 { 209 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 210 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 211 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 212 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 213 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 214 } CRC_TypeDef; 215 216 /** 217 * @brief Digital to Analog Converter 218 */ 219 220 typedef struct 221 { 222 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 223 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 224 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 225 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 226 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 227 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 228 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 229 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 230 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 231 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 232 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 233 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 234 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 235 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 236 } DAC_TypeDef; 237 238 /** 239 * @brief Debug MCU 240 */ 241 242 typedef struct 243 { 244 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 245 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 246 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 247 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 248 }DBGMCU_TypeDef; 249 250 /** 251 * @brief DMA Controller 252 */ 253 254 typedef struct 255 { 256 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 257 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 258 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 259 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 260 } DMA_Channel_TypeDef; 261 262 typedef struct 263 { 264 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 265 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 266 } DMA_TypeDef; 267 268 /** 269 * @brief External Interrupt/Event Controller 270 */ 271 272 typedef struct 273 { 274 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 275 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 276 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 277 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 278 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 279 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 280 } EXTI_TypeDef; 281 282 /** 283 * @brief FLASH Registers 284 */ 285 typedef struct 286 { 287 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 288 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 289 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 290 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 291 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 292 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 293 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 294 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ 295 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */ 296 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */ 297 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ 298 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */ 299 } FLASH_TypeDef; 300 301 /** 302 * @brief Option Bytes Registers 303 */ 304 typedef struct 305 { 306 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 307 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 308 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ 309 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ 310 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ 311 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ 312 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ 313 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ 314 } OB_TypeDef; 315 316 /** 317 * @brief Operational Amplifier (OPAMP) 318 */ 319 typedef struct 320 { 321 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 322 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ 323 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ 324 } OPAMP_TypeDef; 325 326 typedef struct 327 { 328 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ 329 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 330 } OPAMP_Common_TypeDef; 331 332 /** 333 * @brief Flexible Static Memory Controller 334 */ 335 336 typedef struct 337 { 338 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 339 } FSMC_Bank1_TypeDef; 340 341 /** 342 * @brief Flexible Static Memory Controller Bank1E 343 */ 344 345 typedef struct 346 { 347 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 348 } FSMC_Bank1E_TypeDef; 349 350 /** 351 * @brief General Purpose IO 352 */ 353 354 typedef struct 355 { 356 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 357 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 358 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 359 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 360 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 361 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 362 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 363 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 364 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 365 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 366 } GPIO_TypeDef; 367 368 /** 369 * @brief SysTem Configuration 370 */ 371 372 typedef struct 373 { 374 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 375 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 376 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 377 } SYSCFG_TypeDef; 378 379 /** 380 * @brief Inter-integrated Circuit Interface 381 */ 382 383 typedef struct 384 { 385 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 386 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 387 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 388 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 389 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ 390 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 391 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 392 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 393 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 394 } I2C_TypeDef; 395 396 /** 397 * @brief Independent WATCHDOG 398 */ 399 400 typedef struct 401 { 402 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 403 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 404 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 405 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 406 } IWDG_TypeDef; 407 408 /** 409 * @brief Power Control 410 */ 411 412 typedef struct 413 { 414 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 415 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 416 } PWR_TypeDef; 417 418 /** 419 * @brief Reset and Clock Control 420 */ 421 422 typedef struct 423 { 424 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 425 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 426 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ 427 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ 428 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ 429 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ 430 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ 431 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ 432 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ 433 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ 434 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ 435 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ 436 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ 437 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ 438 } RCC_TypeDef; 439 440 /** 441 * @brief Routing Interface 442 */ 443 444 typedef struct 445 { 446 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ 447 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ 448 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ 449 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ 450 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ 451 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ 452 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ 453 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ 454 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ 455 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ 456 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ 457 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ 458 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ 459 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ 460 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ 461 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ 462 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ 463 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ 464 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ 465 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ 466 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ 467 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ 468 } RI_TypeDef; 469 470 /** 471 * @brief Real-Time Clock 472 */ 473 typedef struct 474 { 475 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 476 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 477 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 478 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 479 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 480 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 481 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 482 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 483 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 484 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 485 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 486 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 487 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 488 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 489 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 490 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ 491 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 492 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 493 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 494 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 495 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 496 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 497 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 498 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 499 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 500 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 501 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 502 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 503 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 504 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 505 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 506 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 507 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 508 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 509 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 510 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 511 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 512 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 513 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 514 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 515 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ 516 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ 517 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ 518 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ 519 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ 520 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ 521 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ 522 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ 523 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ 524 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ 525 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ 526 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ 527 } RTC_TypeDef; 528 529 /** 530 * @brief SD host Interface 531 */ 532 533 typedef struct 534 { 535 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ 536 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ 537 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ 538 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ 539 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ 540 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ 541 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ 542 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ 543 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ 544 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ 545 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ 546 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ 547 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ 548 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ 549 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ 550 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ 551 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ 552 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ 553 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ 554 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ 555 } SDIO_TypeDef; 556 557 /** 558 * @brief Serial Peripheral Interface 559 */ 560 561 typedef struct 562 { 563 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 564 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 565 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 566 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 567 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 568 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 569 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 570 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 571 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 572 } SPI_TypeDef; 573 574 /** 575 * @brief TIM 576 */ 577 typedef struct 578 { 579 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 580 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 581 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 582 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 583 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 584 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 585 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 586 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 587 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 588 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 589 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 590 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 591 uint32_t RESERVED12; /*!< Reserved, 0x30 */ 592 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 593 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 594 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 595 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 596 uint32_t RESERVED17; /*!< Reserved, 0x44 */ 597 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 598 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 599 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 600 } TIM_TypeDef; 601 /** 602 * @brief Universal Synchronous Asynchronous Receiver Transmitter 603 */ 604 605 typedef struct 606 { 607 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 608 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 609 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 610 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 611 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 612 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 613 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 614 } USART_TypeDef; 615 616 /** 617 * @brief Universal Serial Bus Full Speed Device 618 */ 619 620 typedef struct 621 { 622 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 623 __IO uint16_t RESERVED0; /*!< Reserved */ 624 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 625 __IO uint16_t RESERVED1; /*!< Reserved */ 626 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 627 __IO uint16_t RESERVED2; /*!< Reserved */ 628 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 629 __IO uint16_t RESERVED3; /*!< Reserved */ 630 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 631 __IO uint16_t RESERVED4; /*!< Reserved */ 632 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 633 __IO uint16_t RESERVED5; /*!< Reserved */ 634 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 635 __IO uint16_t RESERVED6; /*!< Reserved */ 636 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 637 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 638 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 639 __IO uint16_t RESERVED8; /*!< Reserved */ 640 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 641 __IO uint16_t RESERVED9; /*!< Reserved */ 642 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 643 __IO uint16_t RESERVEDA; /*!< Reserved */ 644 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 645 __IO uint16_t RESERVEDB; /*!< Reserved */ 646 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 647 __IO uint16_t RESERVEDC; /*!< Reserved */ 648 } USB_TypeDef; 649 650 /** 651 * @brief Window WATCHDOG 652 */ 653 typedef struct 654 { 655 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 656 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 657 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 658 } WWDG_TypeDef; 659 660 /** 661 * @brief Universal Serial Bus Full Speed Device 662 */ 663 /** 664 * @} 665 */ 666 667 /** @addtogroup Peripheral_memory_map 668 * @{ 669 */ 670 671 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ 672 #define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */ 673 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ 674 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ 675 #define FSMC_BASE (0x60000000UL) /*!< FSMC base address */ 676 #define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */ 677 #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ 678 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ 679 #define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */ 680 #define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */ 681 #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ 682 #define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */ 683 #define FLASH_EEPROM_END (0x08082FFFUL) /*!< FLASH EEPROM end address (12KB) */ 684 685 /*!< Peripheral memory map */ 686 #define APB1PERIPH_BASE PERIPH_BASE 687 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 688 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 689 690 /*!< APB1 peripherals */ 691 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 692 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 693 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 694 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) 695 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 696 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 697 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 698 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 699 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 700 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 701 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) 702 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 703 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 704 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) 705 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) 706 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 707 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 708 709 /* USB device FS */ 710 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ 711 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ 712 713 /* USB device FS SRAM */ 714 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 715 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 716 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL) 717 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL) 718 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL) 719 720 /*!< APB2 peripherals */ 721 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 722 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 723 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL) 724 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL) 725 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL) 726 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 727 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL) 728 #define SDIO_BASE (APB2PERIPH_BASE + 0x00002C00UL) 729 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 730 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 731 732 /*!< AHB peripherals */ 733 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL) 734 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL) 735 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL) 736 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL) 737 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL) 738 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL) 739 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL) 740 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL) 741 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 742 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL) 743 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */ 744 #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ 745 #define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 746 #define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 747 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) 748 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 749 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 750 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 751 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 752 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 753 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 754 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 755 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) 756 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) 757 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) 758 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) 759 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) 760 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) 761 #define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ 762 #define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ 763 #define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */ 764 #define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */ 765 #define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */ 766 #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000UL) /*!< FSMC Bank1 registers base address */ 767 #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104UL) /*!< FSMC Bank1E registers base address */ 768 #define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */ 769 770 /** 771 * @} 772 */ 773 774 /** @addtogroup Peripheral_declaration 775 * @{ 776 */ 777 778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 782 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 783 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 784 #define RTC ((RTC_TypeDef *) RTC_BASE) 785 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 786 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 787 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 788 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 789 #define USART2 ((USART_TypeDef *) USART2_BASE) 790 #define USART3 ((USART_TypeDef *) USART3_BASE) 791 #define UART4 ((USART_TypeDef *) UART4_BASE) 792 #define UART5 ((USART_TypeDef *) UART5_BASE) 793 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 794 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 795 /* USB device FS */ 796 #define USB ((USB_TypeDef *) USB_BASE) 797 /* USB device FS SRAM */ 798 #define PWR ((PWR_TypeDef *) PWR_BASE) 799 800 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 801 /* Legacy define */ 802 #define DAC DAC1 803 804 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ 805 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 806 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 807 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ 808 809 #define RI ((RI_TypeDef *) RI_BASE) 810 811 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 812 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) 813 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) 814 #define OPAMP3 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U)) 815 #define OPAMP123_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) 816 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 817 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 818 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 819 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 820 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 821 822 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 823 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 824 /* Legacy defines */ 825 #define ADC ADC1_COMMON 826 827 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 828 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 829 #define USART1 ((USART_TypeDef *) USART1_BASE) 830 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 831 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 832 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 833 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 834 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 835 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 836 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 837 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 838 #define CRC ((CRC_TypeDef *) CRC_BASE) 839 #define RCC ((RCC_TypeDef *) RCC_BASE) 840 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 841 #define OB ((OB_TypeDef *) OB_BASE) 842 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 843 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 844 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 845 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 846 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 847 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 848 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 849 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 850 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 851 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 852 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 853 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 854 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 855 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 856 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE) 857 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE) 858 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 859 860 /** 861 * @} 862 */ 863 864 /** @addtogroup Exported_constants 865 * @{ 866 */ 867 868 /** @addtogroup Hardware_Constant_Definition 869 * @{ 870 */ 871 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ 872 873 /** 874 * @} 875 */ 876 877 /** @addtogroup Peripheral_Registers_Bits_Definition 878 * @{ 879 */ 880 881 /******************************************************************************/ 882 /* Peripheral Registers Bits Definition */ 883 /******************************************************************************/ 884 /******************************************************************************/ 885 /* */ 886 /* Analog to Digital Converter (ADC) */ 887 /* */ 888 /******************************************************************************/ 889 #define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 890 #define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 891 #define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 892 893 /******************** Bit definition for ADC_SR register ********************/ 894 #define ADC_SR_AWD_Pos (0U) 895 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 896 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 897 #define ADC_SR_EOCS_Pos (1U) 898 #define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ 899 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ 900 #define ADC_SR_JEOS_Pos (2U) 901 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 902 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 903 #define ADC_SR_JSTRT_Pos (3U) 904 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 905 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 906 #define ADC_SR_STRT_Pos (4U) 907 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 908 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 909 #define ADC_SR_OVR_Pos (5U) 910 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ 911 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ 912 #define ADC_SR_ADONS_Pos (6U) 913 #define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ 914 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ 915 #define ADC_SR_RCNR_Pos (8U) 916 #define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ 917 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ 918 #define ADC_SR_JCNR_Pos (9U) 919 #define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ 920 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ 921 922 /* Legacy defines */ 923 #define ADC_SR_EOC (ADC_SR_EOCS) 924 #define ADC_SR_JEOC (ADC_SR_JEOS) 925 926 /******************* Bit definition for ADC_CR1 register ********************/ 927 #define ADC_CR1_AWDCH_Pos (0U) 928 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 929 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 930 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 931 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 932 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 933 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 934 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 935 936 #define ADC_CR1_EOCSIE_Pos (5U) 937 #define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ 938 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ 939 #define ADC_CR1_AWDIE_Pos (6U) 940 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 941 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 942 #define ADC_CR1_JEOSIE_Pos (7U) 943 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 944 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 945 #define ADC_CR1_SCAN_Pos (8U) 946 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 947 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 948 #define ADC_CR1_AWDSGL_Pos (9U) 949 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 950 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 951 #define ADC_CR1_JAUTO_Pos (10U) 952 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 953 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 954 #define ADC_CR1_DISCEN_Pos (11U) 955 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 956 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 957 #define ADC_CR1_JDISCEN_Pos (12U) 958 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 959 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 960 961 #define ADC_CR1_DISCNUM_Pos (13U) 962 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 963 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 964 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 965 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 966 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 967 968 #define ADC_CR1_PDD_Pos (16U) 969 #define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ 970 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ 971 #define ADC_CR1_PDI_Pos (17U) 972 #define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ 973 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ 974 975 #define ADC_CR1_JAWDEN_Pos (22U) 976 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 977 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 978 #define ADC_CR1_AWDEN_Pos (23U) 979 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 980 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 981 982 #define ADC_CR1_RES_Pos (24U) 983 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ 984 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ 985 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ 986 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ 987 988 #define ADC_CR1_OVRIE_Pos (26U) 989 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ 990 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 991 992 /* Legacy defines */ 993 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) 994 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 995 996 /******************* Bit definition for ADC_CR2 register ********************/ 997 #define ADC_CR2_ADON_Pos (0U) 998 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 999 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 1000 #define ADC_CR2_CONT_Pos (1U) 1001 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 1002 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1003 #define ADC_CR2_CFG_Pos (2U) 1004 #define ADC_CR2_CFG_Msk (0x1UL << ADC_CR2_CFG_Pos) /*!< 0x00000004 */ 1005 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */ 1006 1007 #define ADC_CR2_DELS_Pos (4U) 1008 #define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ 1009 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ 1010 #define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ 1011 #define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ 1012 #define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ 1013 1014 #define ADC_CR2_DMA_Pos (8U) 1015 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 1016 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 1017 #define ADC_CR2_DDS_Pos (9U) 1018 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ 1019 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ 1020 #define ADC_CR2_EOCS_Pos (10U) 1021 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ 1022 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ 1023 #define ADC_CR2_ALIGN_Pos (11U) 1024 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 1025 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */ 1026 1027 #define ADC_CR2_JEXTSEL_Pos (16U) 1028 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ 1029 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1030 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ 1031 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ 1032 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ 1033 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ 1034 1035 #define ADC_CR2_JEXTEN_Pos (20U) 1036 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ 1037 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1038 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ 1039 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ 1040 1041 #define ADC_CR2_JSWSTART_Pos (22U) 1042 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ 1043 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 1044 1045 #define ADC_CR2_EXTSEL_Pos (24U) 1046 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ 1047 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1048 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ 1049 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ 1050 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ 1051 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ 1052 1053 #define ADC_CR2_EXTEN_Pos (28U) 1054 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ 1055 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1056 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ 1057 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ 1058 1059 #define ADC_CR2_SWSTART_Pos (30U) 1060 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ 1061 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 1062 1063 /****************** Bit definition for ADC_SMPR1 register *******************/ 1064 #define ADC_SMPR1_SMP20_Pos (0U) 1065 #define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ 1066 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ 1067 #define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ 1068 #define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ 1069 #define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ 1070 1071 #define ADC_SMPR1_SMP21_Pos (3U) 1072 #define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ 1073 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ 1074 #define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ 1075 #define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ 1076 #define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ 1077 1078 #define ADC_SMPR1_SMP22_Pos (6U) 1079 #define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ 1080 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ 1081 #define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ 1082 #define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ 1083 #define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ 1084 1085 #define ADC_SMPR1_SMP23_Pos (9U) 1086 #define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ 1087 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ 1088 #define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ 1089 #define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ 1090 #define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ 1091 1092 #define ADC_SMPR1_SMP24_Pos (12U) 1093 #define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ 1094 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ 1095 #define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ 1096 #define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ 1097 #define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ 1098 1099 #define ADC_SMPR1_SMP25_Pos (15U) 1100 #define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ 1101 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ 1102 #define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ 1103 #define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ 1104 #define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ 1105 1106 #define ADC_SMPR1_SMP26_Pos (18U) 1107 #define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ 1108 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ 1109 #define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ 1110 #define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ 1111 #define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ 1112 1113 #define ADC_SMPR1_SMP27_Pos (21U) 1114 #define ADC_SMPR1_SMP27_Msk (0x7UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */ 1115 #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */ 1116 #define ADC_SMPR1_SMP27_0 (0x1UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */ 1117 #define ADC_SMPR1_SMP27_1 (0x2UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */ 1118 #define ADC_SMPR1_SMP27_2 (0x4UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */ 1119 1120 #define ADC_SMPR1_SMP28_Pos (24U) 1121 #define ADC_SMPR1_SMP28_Msk (0x7UL << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */ 1122 #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */ 1123 #define ADC_SMPR1_SMP28_0 (0x1UL << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */ 1124 #define ADC_SMPR1_SMP28_1 (0x2UL << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */ 1125 #define ADC_SMPR1_SMP28_2 (0x4UL << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */ 1126 1127 #define ADC_SMPR1_SMP29_Pos (27U) 1128 #define ADC_SMPR1_SMP29_Msk (0x7UL << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */ 1129 #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */ 1130 #define ADC_SMPR1_SMP29_0 (0x1UL << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */ 1131 #define ADC_SMPR1_SMP29_1 (0x2UL << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */ 1132 #define ADC_SMPR1_SMP29_2 (0x4UL << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */ 1133 1134 /****************** Bit definition for ADC_SMPR2 register *******************/ 1135 #define ADC_SMPR2_SMP10_Pos (0U) 1136 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1137 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1138 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1139 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1140 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1141 1142 #define ADC_SMPR2_SMP11_Pos (3U) 1143 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1144 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1145 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1146 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1147 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1148 1149 #define ADC_SMPR2_SMP12_Pos (6U) 1150 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1151 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1152 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1153 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1154 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1155 1156 #define ADC_SMPR2_SMP13_Pos (9U) 1157 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1158 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1159 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1160 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1161 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1162 1163 #define ADC_SMPR2_SMP14_Pos (12U) 1164 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1165 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1166 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1167 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1168 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1169 1170 #define ADC_SMPR2_SMP15_Pos (15U) 1171 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1172 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ 1173 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1174 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1175 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1176 1177 #define ADC_SMPR2_SMP16_Pos (18U) 1178 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1179 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1180 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1181 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1182 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1183 1184 #define ADC_SMPR2_SMP17_Pos (21U) 1185 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1186 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1187 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1188 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1189 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1190 1191 #define ADC_SMPR2_SMP18_Pos (24U) 1192 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1193 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1194 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1195 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1196 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1197 1198 #define ADC_SMPR2_SMP19_Pos (27U) 1199 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ 1200 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ 1201 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ 1202 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ 1203 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ 1204 1205 /****************** Bit definition for ADC_SMPR3 register *******************/ 1206 #define ADC_SMPR3_SMP0_Pos (0U) 1207 #define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ 1208 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1209 #define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ 1210 #define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ 1211 #define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ 1212 1213 #define ADC_SMPR3_SMP1_Pos (3U) 1214 #define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ 1215 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1216 #define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ 1217 #define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ 1218 #define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ 1219 1220 #define ADC_SMPR3_SMP2_Pos (6U) 1221 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ 1222 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1223 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ 1224 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ 1225 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ 1226 1227 #define ADC_SMPR3_SMP3_Pos (9U) 1228 #define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ 1229 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1230 #define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ 1231 #define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ 1232 #define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ 1233 1234 #define ADC_SMPR3_SMP4_Pos (12U) 1235 #define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ 1236 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1237 #define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ 1238 #define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ 1239 #define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ 1240 1241 #define ADC_SMPR3_SMP5_Pos (15U) 1242 #define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ 1243 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1244 #define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ 1245 #define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ 1246 #define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ 1247 1248 #define ADC_SMPR3_SMP6_Pos (18U) 1249 #define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ 1250 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1251 #define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ 1252 #define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ 1253 #define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ 1254 1255 #define ADC_SMPR3_SMP7_Pos (21U) 1256 #define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ 1257 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1258 #define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ 1259 #define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ 1260 #define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ 1261 1262 #define ADC_SMPR3_SMP8_Pos (24U) 1263 #define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ 1264 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1265 #define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ 1266 #define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ 1267 #define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ 1268 1269 #define ADC_SMPR3_SMP9_Pos (27U) 1270 #define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ 1271 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1272 #define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ 1273 #define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ 1274 #define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ 1275 1276 /****************** Bit definition for ADC_JOFR1 register *******************/ 1277 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1278 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 1279 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 1280 1281 /****************** Bit definition for ADC_JOFR2 register *******************/ 1282 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1283 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 1284 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 1285 1286 /****************** Bit definition for ADC_JOFR3 register *******************/ 1287 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1288 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 1289 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 1290 1291 /****************** Bit definition for ADC_JOFR4 register *******************/ 1292 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1293 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 1294 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 1295 1296 /******************* Bit definition for ADC_HTR register ********************/ 1297 #define ADC_HTR_HT_Pos (0U) 1298 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 1299 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 1300 1301 /******************* Bit definition for ADC_LTR register ********************/ 1302 #define ADC_LTR_LT_Pos (0U) 1303 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 1304 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 1305 1306 /******************* Bit definition for ADC_SQR1 register *******************/ 1307 #define ADC_SQR1_L_Pos (20U) 1308 #define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ 1309 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1310 #define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 1311 #define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 1312 #define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 1313 #define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 1314 #define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /*!< 0x01000000 */ 1315 1316 #define ADC_SQR1_SQ28_Pos (15U) 1317 #define ADC_SQR1_SQ28_Msk (0x1FUL << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */ 1318 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */ 1319 #define ADC_SQR1_SQ28_0 (0x01UL << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */ 1320 #define ADC_SQR1_SQ28_1 (0x02UL << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */ 1321 #define ADC_SQR1_SQ28_2 (0x04UL << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */ 1322 #define ADC_SQR1_SQ28_3 (0x08UL << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */ 1323 #define ADC_SQR1_SQ28_4 (0x10UL << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */ 1324 1325 #define ADC_SQR1_SQ27_Pos (10U) 1326 #define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ 1327 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ 1328 #define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ 1329 #define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ 1330 #define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ 1331 #define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ 1332 #define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ 1333 1334 #define ADC_SQR1_SQ26_Pos (5U) 1335 #define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ 1336 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ 1337 #define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ 1338 #define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ 1339 #define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ 1340 #define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ 1341 #define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ 1342 1343 #define ADC_SQR1_SQ25_Pos (0U) 1344 #define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ 1345 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ 1346 #define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ 1347 #define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ 1348 #define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ 1349 #define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ 1350 #define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ 1351 1352 /******************* Bit definition for ADC_SQR2 register *******************/ 1353 #define ADC_SQR2_SQ19_Pos (0U) 1354 #define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ 1355 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ 1356 #define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ 1357 #define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ 1358 #define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ 1359 #define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ 1360 #define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ 1361 1362 #define ADC_SQR2_SQ20_Pos (5U) 1363 #define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ 1364 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ 1365 #define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ 1366 #define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ 1367 #define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ 1368 #define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ 1369 #define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ 1370 1371 #define ADC_SQR2_SQ21_Pos (10U) 1372 #define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ 1373 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ 1374 #define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ 1375 #define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ 1376 #define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ 1377 #define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ 1378 #define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ 1379 1380 #define ADC_SQR2_SQ22_Pos (15U) 1381 #define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ 1382 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ 1383 #define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ 1384 #define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ 1385 #define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ 1386 #define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ 1387 #define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ 1388 1389 #define ADC_SQR2_SQ23_Pos (20U) 1390 #define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ 1391 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ 1392 #define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ 1393 #define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ 1394 #define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ 1395 #define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ 1396 #define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ 1397 1398 #define ADC_SQR2_SQ24_Pos (25U) 1399 #define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ 1400 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ 1401 #define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ 1402 #define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ 1403 #define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ 1404 #define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ 1405 #define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ 1406 1407 /******************* Bit definition for ADC_SQR3 register *******************/ 1408 #define ADC_SQR3_SQ13_Pos (0U) 1409 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ 1410 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1411 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ 1412 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ 1413 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ 1414 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ 1415 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ 1416 1417 #define ADC_SQR3_SQ14_Pos (5U) 1418 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ 1419 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1420 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ 1421 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ 1422 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ 1423 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ 1424 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ 1425 1426 #define ADC_SQR3_SQ15_Pos (10U) 1427 #define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ 1428 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1429 #define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ 1430 #define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ 1431 #define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ 1432 #define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ 1433 #define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ 1434 1435 #define ADC_SQR3_SQ16_Pos (15U) 1436 #define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ 1437 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1438 #define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ 1439 #define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ 1440 #define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ 1441 #define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ 1442 #define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ 1443 1444 #define ADC_SQR3_SQ17_Pos (20U) 1445 #define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ 1446 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ 1447 #define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ 1448 #define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ 1449 #define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ 1450 #define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ 1451 #define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ 1452 1453 #define ADC_SQR3_SQ18_Pos (25U) 1454 #define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ 1455 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ 1456 #define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ 1457 #define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ 1458 #define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ 1459 #define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ 1460 #define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ 1461 1462 /******************* Bit definition for ADC_SQR4 register *******************/ 1463 #define ADC_SQR4_SQ7_Pos (0U) 1464 #define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ 1465 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1466 #define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ 1467 #define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ 1468 #define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ 1469 #define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ 1470 #define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ 1471 1472 #define ADC_SQR4_SQ8_Pos (5U) 1473 #define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ 1474 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1475 #define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ 1476 #define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ 1477 #define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ 1478 #define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ 1479 #define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ 1480 1481 #define ADC_SQR4_SQ9_Pos (10U) 1482 #define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ 1483 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1484 #define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ 1485 #define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ 1486 #define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ 1487 #define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ 1488 #define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ 1489 1490 #define ADC_SQR4_SQ10_Pos (15U) 1491 #define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ 1492 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1493 #define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ 1494 #define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ 1495 #define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ 1496 #define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ 1497 #define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ 1498 1499 #define ADC_SQR4_SQ11_Pos (20U) 1500 #define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ 1501 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1502 #define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ 1503 #define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ 1504 #define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ 1505 #define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ 1506 #define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ 1507 1508 #define ADC_SQR4_SQ12_Pos (25U) 1509 #define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ 1510 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1511 #define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ 1512 #define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ 1513 #define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ 1514 #define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ 1515 #define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ 1516 1517 /******************* Bit definition for ADC_SQR5 register *******************/ 1518 #define ADC_SQR5_SQ1_Pos (0U) 1519 #define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ 1520 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1521 #define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ 1522 #define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ 1523 #define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ 1524 #define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ 1525 #define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ 1526 1527 #define ADC_SQR5_SQ2_Pos (5U) 1528 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ 1529 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1530 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ 1531 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ 1532 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ 1533 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ 1534 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ 1535 1536 #define ADC_SQR5_SQ3_Pos (10U) 1537 #define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ 1538 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1539 #define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ 1540 #define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ 1541 #define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ 1542 #define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ 1543 #define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ 1544 1545 #define ADC_SQR5_SQ4_Pos (15U) 1546 #define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ 1547 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1548 #define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ 1549 #define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ 1550 #define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ 1551 #define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ 1552 #define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ 1553 1554 #define ADC_SQR5_SQ5_Pos (20U) 1555 #define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ 1556 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1557 #define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ 1558 #define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ 1559 #define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ 1560 #define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ 1561 #define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ 1562 1563 #define ADC_SQR5_SQ6_Pos (25U) 1564 #define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ 1565 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1566 #define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ 1567 #define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ 1568 #define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ 1569 #define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ 1570 #define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ 1571 1572 1573 /******************* Bit definition for ADC_JSQR register *******************/ 1574 #define ADC_JSQR_JSQ1_Pos (0U) 1575 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 1576 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1577 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 1578 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 1579 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 1580 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 1581 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 1582 1583 #define ADC_JSQR_JSQ2_Pos (5U) 1584 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 1585 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1586 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 1587 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 1588 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 1589 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 1590 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 1591 1592 #define ADC_JSQR_JSQ3_Pos (10U) 1593 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 1594 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1595 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 1596 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 1597 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 1598 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 1599 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 1600 1601 #define ADC_JSQR_JSQ4_Pos (15U) 1602 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 1603 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1604 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 1605 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 1606 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 1607 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 1608 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 1609 1610 #define ADC_JSQR_JL_Pos (20U) 1611 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 1612 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1613 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 1614 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 1615 1616 /******************* Bit definition for ADC_JDR1 register *******************/ 1617 #define ADC_JDR1_JDATA_Pos (0U) 1618 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1619 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1620 1621 /******************* Bit definition for ADC_JDR2 register *******************/ 1622 #define ADC_JDR2_JDATA_Pos (0U) 1623 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1624 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1625 1626 /******************* Bit definition for ADC_JDR3 register *******************/ 1627 #define ADC_JDR3_JDATA_Pos (0U) 1628 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1629 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1630 1631 /******************* Bit definition for ADC_JDR4 register *******************/ 1632 #define ADC_JDR4_JDATA_Pos (0U) 1633 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1634 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1635 1636 /******************** Bit definition for ADC_DR register ********************/ 1637 #define ADC_DR_DATA_Pos (0U) 1638 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1639 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1640 1641 /****************** Bit definition for ADC_SMPR0 register *******************/ 1642 #define ADC_SMPR0_SMP30_Pos (0U) 1643 #define ADC_SMPR0_SMP30_Msk (0x7UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */ 1644 #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */ 1645 #define ADC_SMPR0_SMP30_0 (0x1UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */ 1646 #define ADC_SMPR0_SMP30_1 (0x2UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */ 1647 #define ADC_SMPR0_SMP30_2 (0x4UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */ 1648 1649 #define ADC_SMPR0_SMP31_Pos (3U) 1650 #define ADC_SMPR0_SMP31_Msk (0x7UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */ 1651 #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */ 1652 #define ADC_SMPR0_SMP31_0 (0x1UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */ 1653 #define ADC_SMPR0_SMP31_1 (0x2UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */ 1654 #define ADC_SMPR0_SMP31_2 (0x4UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */ 1655 1656 /******************* Bit definition for ADC_CSR register ********************/ 1657 #define ADC_CSR_AWD1_Pos (0U) 1658 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ 1659 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1660 #define ADC_CSR_EOCS1_Pos (1U) 1661 #define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ 1662 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ 1663 #define ADC_CSR_JEOS1_Pos (2U) 1664 #define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ 1665 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1666 #define ADC_CSR_JSTRT1_Pos (3U) 1667 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ 1668 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ 1669 #define ADC_CSR_STRT1_Pos (4U) 1670 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ 1671 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ 1672 #define ADC_CSR_OVR1_Pos (5U) 1673 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ 1674 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ 1675 #define ADC_CSR_ADONS1_Pos (6U) 1676 #define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ 1677 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ 1678 1679 /* Legacy defines */ 1680 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) 1681 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) 1682 1683 /******************* Bit definition for ADC_CCR register ********************/ 1684 #define ADC_CCR_ADCPRE_Pos (16U) 1685 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ 1686 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ 1687 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ 1688 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ 1689 #define ADC_CCR_TSVREFE_Pos (23U) 1690 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ 1691 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 1692 1693 /******************************************************************************/ 1694 /* */ 1695 /* Analog Comparators (COMP) */ 1696 /* */ 1697 /******************************************************************************/ 1698 1699 /****************** Bit definition for COMP_CSR register ********************/ 1700 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ 1701 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ 1702 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ 1703 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ 1704 #define COMP_CSR_CMP1EN_Pos (4U) 1705 #define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ 1706 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ 1707 #define COMP_CSR_CMP1OUT_Pos (7U) 1708 #define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ 1709 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ 1710 #define COMP_CSR_SPEED_Pos (12U) 1711 #define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ 1712 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ 1713 #define COMP_CSR_CMP2OUT_Pos (13U) 1714 #define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ 1715 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ 1716 1717 #define COMP_CSR_WNDWE_Pos (17U) 1718 #define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ 1719 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1720 1721 #define COMP_CSR_INSEL_Pos (18U) 1722 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ 1723 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ 1724 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ 1725 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ 1726 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ 1727 #define COMP_CSR_OUTSEL_Pos (21U) 1728 #define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ 1729 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ 1730 #define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ 1731 #define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ 1732 #define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ 1733 1734 /* Bits present in COMP register but not related to comparator */ 1735 /* (or partially related to comparator, in addition to other peripherals) */ 1736 #define COMP_CSR_SW1_Pos (5U) 1737 #define COMP_CSR_SW1_Msk (0x1UL << COMP_CSR_SW1_Pos) /*!< 0x00000020 */ 1738 #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */ 1739 #define COMP_CSR_VREFOUTEN_Pos (16U) 1740 #define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ 1741 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ 1742 1743 #define COMP_CSR_FCH3_Pos (26U) 1744 #define COMP_CSR_FCH3_Msk (0x1UL << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */ 1745 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */ 1746 #define COMP_CSR_FCH8_Pos (27U) 1747 #define COMP_CSR_FCH8_Msk (0x1UL << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */ 1748 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */ 1749 #define COMP_CSR_RCH13_Pos (28U) 1750 #define COMP_CSR_RCH13_Msk (0x1UL << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */ 1751 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */ 1752 1753 #define COMP_CSR_CAIE_Pos (29U) 1754 #define COMP_CSR_CAIE_Msk (0x1UL << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */ 1755 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */ 1756 #define COMP_CSR_CAIF_Pos (30U) 1757 #define COMP_CSR_CAIF_Msk (0x1UL << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */ 1758 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */ 1759 #define COMP_CSR_TSUSP_Pos (31U) 1760 #define COMP_CSR_TSUSP_Msk (0x1UL << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */ 1761 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */ 1762 1763 /******************************************************************************/ 1764 /* */ 1765 /* Operational Amplifier (OPAMP) */ 1766 /* */ 1767 /******************************************************************************/ 1768 /******************* Bit definition for OPAMP_CSR register ******************/ 1769 #define OPAMP_CSR_OPA1PD_Pos (0U) 1770 #define OPAMP_CSR_OPA1PD_Msk (0x1UL << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */ 1771 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */ 1772 #define OPAMP_CSR_S3SEL1_Pos (1U) 1773 #define OPAMP_CSR_S3SEL1_Msk (0x1UL << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */ 1774 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */ 1775 #define OPAMP_CSR_S4SEL1_Pos (2U) 1776 #define OPAMP_CSR_S4SEL1_Msk (0x1UL << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */ 1777 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */ 1778 #define OPAMP_CSR_S5SEL1_Pos (3U) 1779 #define OPAMP_CSR_S5SEL1_Msk (0x1UL << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */ 1780 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */ 1781 #define OPAMP_CSR_S6SEL1_Pos (4U) 1782 #define OPAMP_CSR_S6SEL1_Msk (0x1UL << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */ 1783 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */ 1784 #define OPAMP_CSR_OPA1CAL_L_Pos (5U) 1785 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */ 1786 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */ 1787 #define OPAMP_CSR_OPA1CAL_H_Pos (6U) 1788 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */ 1789 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */ 1790 #define OPAMP_CSR_OPA1LPM_Pos (7U) 1791 #define OPAMP_CSR_OPA1LPM_Msk (0x1UL << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */ 1792 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */ 1793 #define OPAMP_CSR_OPA2PD_Pos (8U) 1794 #define OPAMP_CSR_OPA2PD_Msk (0x1UL << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */ 1795 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */ 1796 #define OPAMP_CSR_S3SEL2_Pos (9U) 1797 #define OPAMP_CSR_S3SEL2_Msk (0x1UL << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */ 1798 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */ 1799 #define OPAMP_CSR_S4SEL2_Pos (10U) 1800 #define OPAMP_CSR_S4SEL2_Msk (0x1UL << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */ 1801 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */ 1802 #define OPAMP_CSR_S5SEL2_Pos (11U) 1803 #define OPAMP_CSR_S5SEL2_Msk (0x1UL << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */ 1804 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */ 1805 #define OPAMP_CSR_S6SEL2_Pos (12U) 1806 #define OPAMP_CSR_S6SEL2_Msk (0x1UL << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */ 1807 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */ 1808 #define OPAMP_CSR_OPA2CAL_L_Pos (13U) 1809 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */ 1810 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */ 1811 #define OPAMP_CSR_OPA2CAL_H_Pos (14U) 1812 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */ 1813 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */ 1814 #define OPAMP_CSR_OPA2LPM_Pos (15U) 1815 #define OPAMP_CSR_OPA2LPM_Msk (0x1UL << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */ 1816 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */ 1817 #define OPAMP_CSR_OPA3PD_Pos (16U) 1818 #define OPAMP_CSR_OPA3PD_Msk (0x1UL << OPAMP_CSR_OPA3PD_Pos) /*!< 0x00010000 */ 1819 #define OPAMP_CSR_OPA3PD OPAMP_CSR_OPA3PD_Msk /*!< OPAMP3 disable */ 1820 #define OPAMP_CSR_S3SEL3_Pos (17U) 1821 #define OPAMP_CSR_S3SEL3_Msk (0x1UL << OPAMP_CSR_S3SEL3_Pos) /*!< 0x00020000 */ 1822 #define OPAMP_CSR_S3SEL3 OPAMP_CSR_S3SEL3_Msk /*!< Switch 3 for OPAMP3 Enable */ 1823 #define OPAMP_CSR_S4SEL3_Pos (18U) 1824 #define OPAMP_CSR_S4SEL3_Msk (0x1UL << OPAMP_CSR_S4SEL3_Pos) /*!< 0x00040000 */ 1825 #define OPAMP_CSR_S4SEL3 OPAMP_CSR_S4SEL3_Msk /*!< Switch 4 for OPAMP3 Enable */ 1826 #define OPAMP_CSR_S5SEL3_Pos (19U) 1827 #define OPAMP_CSR_S5SEL3_Msk (0x1UL << OPAMP_CSR_S5SEL3_Pos) /*!< 0x00080000 */ 1828 #define OPAMP_CSR_S5SEL3 OPAMP_CSR_S5SEL3_Msk /*!< Switch 5 for OPAMP3 Enable */ 1829 #define OPAMP_CSR_S6SEL3_Pos (20U) 1830 #define OPAMP_CSR_S6SEL3_Msk (0x1UL << OPAMP_CSR_S6SEL3_Pos) /*!< 0x00100000 */ 1831 #define OPAMP_CSR_S6SEL3 OPAMP_CSR_S6SEL3_Msk /*!< Switch 6 for OPAMP3 Enable */ 1832 #define OPAMP_CSR_OPA3CAL_L_Pos (21U) 1833 #define OPAMP_CSR_OPA3CAL_L_Msk (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */ 1834 #define OPAMP_CSR_OPA3CAL_L OPAMP_CSR_OPA3CAL_L_Msk /*!< OPAMP3 Offset calibration for P differential pair */ 1835 #define OPAMP_CSR_OPA3CAL_H_Pos (22U) 1836 #define OPAMP_CSR_OPA3CAL_H_Msk (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */ 1837 #define OPAMP_CSR_OPA3CAL_H OPAMP_CSR_OPA3CAL_H_Msk /*!< OPAMP3 Offset calibration for N differential pair */ 1838 #define OPAMP_CSR_OPA3LPM_Pos (23U) 1839 #define OPAMP_CSR_OPA3LPM_Msk (0x1UL << OPAMP_CSR_OPA3LPM_Pos) /*!< 0x00800000 */ 1840 #define OPAMP_CSR_OPA3LPM OPAMP_CSR_OPA3LPM_Msk /*!< OPAMP3 Low power enable */ 1841 #define OPAMP_CSR_ANAWSEL1_Pos (24U) 1842 #define OPAMP_CSR_ANAWSEL1_Msk (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */ 1843 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ 1844 #define OPAMP_CSR_ANAWSEL2_Pos (25U) 1845 #define OPAMP_CSR_ANAWSEL2_Msk (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */ 1846 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */ 1847 #define OPAMP_CSR_ANAWSEL3_Pos (26U) 1848 #define OPAMP_CSR_ANAWSEL3_Msk (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */ 1849 #define OPAMP_CSR_ANAWSEL3 OPAMP_CSR_ANAWSEL3_Msk /*!< Switch ANA Enable for OPAMP3 */ 1850 #define OPAMP_CSR_S7SEL2_Pos (27U) 1851 #define OPAMP_CSR_S7SEL2_Msk (0x1UL << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */ 1852 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */ 1853 #define OPAMP_CSR_AOP_RANGE_Pos (28U) 1854 #define OPAMP_CSR_AOP_RANGE_Msk (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */ 1855 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ 1856 #define OPAMP_CSR_OPA1CALOUT_Pos (29U) 1857 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */ 1858 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */ 1859 #define OPAMP_CSR_OPA2CALOUT_Pos (30U) 1860 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */ 1861 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */ 1862 #define OPAMP_CSR_OPA3CALOUT_Pos (31U) 1863 #define OPAMP_CSR_OPA3CALOUT_Msk (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */ 1864 #define OPAMP_CSR_OPA3CALOUT OPAMP_CSR_OPA3CALOUT_Msk /*!< OPAMP3 calibration output */ 1865 1866 /******************* Bit definition for OPAMP_OTR register ******************/ 1867 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) 1868 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */ 1869 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1870 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) 1871 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */ 1872 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1873 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) 1874 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */ 1875 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1876 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) 1877 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */ 1878 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1879 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U) 1880 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */ 1881 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ 1882 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U) 1883 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */ 1884 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ 1885 #define OPAMP_OTR_OT_USER_Pos (31U) 1886 #define OPAMP_OTR_OT_USER_Msk (0x1UL << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */ 1887 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */ 1888 1889 /******************* Bit definition for OPAMP_LPOTR register ****************/ 1890 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) 1891 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */ 1892 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1893 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) 1894 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */ 1895 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1896 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) 1897 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */ 1898 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1899 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) 1900 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */ 1901 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1902 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U) 1903 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */ 1904 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ 1905 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U) 1906 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */ 1907 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ 1908 1909 /******************************************************************************/ 1910 /* */ 1911 /* CRC calculation unit (CRC) */ 1912 /* */ 1913 /******************************************************************************/ 1914 1915 /******************* Bit definition for CRC_DR register *********************/ 1916 #define CRC_DR_DR_Pos (0U) 1917 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1918 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1919 1920 /******************* Bit definition for CRC_IDR register ********************/ 1921 #define CRC_IDR_IDR_Pos (0U) 1922 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 1923 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 1924 1925 /******************** Bit definition for CRC_CR register ********************/ 1926 #define CRC_CR_RESET_Pos (0U) 1927 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1928 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 1929 1930 /******************************************************************************/ 1931 /* */ 1932 /* Digital to Analog Converter (DAC) */ 1933 /* */ 1934 /******************************************************************************/ 1935 1936 /******************** Bit definition for DAC_CR register ********************/ 1937 #define DAC_CR_EN1_Pos (0U) 1938 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1939 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 1940 #define DAC_CR_BOFF1_Pos (1U) 1941 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 1942 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ 1943 #define DAC_CR_TEN1_Pos (2U) 1944 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 1945 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 1946 1947 #define DAC_CR_TSEL1_Pos (3U) 1948 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 1949 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 1950 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1951 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1952 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1953 1954 #define DAC_CR_WAVE1_Pos (6U) 1955 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 1956 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 1957 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 1958 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 1959 1960 #define DAC_CR_MAMP1_Pos (8U) 1961 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 1962 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 1963 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 1964 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 1965 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 1966 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 1967 1968 #define DAC_CR_DMAEN1_Pos (12U) 1969 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1970 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 1971 #define DAC_CR_DMAUDRIE1_Pos (13U) 1972 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1973 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */ 1974 #define DAC_CR_EN2_Pos (16U) 1975 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 1976 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 1977 #define DAC_CR_BOFF2_Pos (17U) 1978 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 1979 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ 1980 #define DAC_CR_TEN2_Pos (18U) 1981 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 1982 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 1983 1984 #define DAC_CR_TSEL2_Pos (19U) 1985 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 1986 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 1987 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 1988 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 1989 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 1990 1991 #define DAC_CR_WAVE2_Pos (22U) 1992 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 1993 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 1994 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 1995 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 1996 1997 #define DAC_CR_MAMP2_Pos (24U) 1998 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 1999 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 2000 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 2001 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 2002 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 2003 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 2004 2005 #define DAC_CR_DMAEN2_Pos (28U) 2006 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 2007 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 2008 #define DAC_CR_DMAUDRIE2_Pos (29U) 2009 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 2010 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */ 2011 /***************** Bit definition for DAC_SWTRIGR register ******************/ 2012 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 2013 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 2014 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 2015 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 2016 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 2017 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 2018 2019 /***************** Bit definition for DAC_DHR12R1 register ******************/ 2020 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 2021 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 2022 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2023 2024 /***************** Bit definition for DAC_DHR12L1 register ******************/ 2025 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 2026 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2027 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2028 2029 /****************** Bit definition for DAC_DHR8R1 register ******************/ 2030 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 2031 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 2032 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2033 2034 /***************** Bit definition for DAC_DHR12R2 register ******************/ 2035 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 2036 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 2037 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2038 2039 /***************** Bit definition for DAC_DHR12L2 register ******************/ 2040 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 2041 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 2042 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2043 2044 /****************** Bit definition for DAC_DHR8R2 register ******************/ 2045 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 2046 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 2047 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2048 2049 /***************** Bit definition for DAC_DHR12RD register ******************/ 2050 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 2051 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 2052 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2053 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 2054 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 2055 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2056 2057 /***************** Bit definition for DAC_DHR12LD register ******************/ 2058 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 2059 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2060 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2061 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 2062 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 2063 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2064 2065 /****************** Bit definition for DAC_DHR8RD register ******************/ 2066 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 2067 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 2068 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2069 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 2070 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 2071 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2072 2073 /******************* Bit definition for DAC_DOR1 register *******************/ 2074 #define DAC_DOR1_DACC1DOR_Pos (0U) 2075 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 2076 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 2077 2078 /******************* Bit definition for DAC_DOR2 register *******************/ 2079 #define DAC_DOR2_DACC2DOR_Pos (0U) 2080 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 2081 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 2082 2083 /******************** Bit definition for DAC_SR register ********************/ 2084 #define DAC_SR_DMAUDR1_Pos (13U) 2085 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 2086 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 2087 #define DAC_SR_DMAUDR2_Pos (29U) 2088 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 2089 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 2090 2091 /******************************************************************************/ 2092 /* */ 2093 /* Debug MCU (DBGMCU) */ 2094 /* */ 2095 /******************************************************************************/ 2096 2097 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 2098 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 2099 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 2100 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 2101 2102 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 2103 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 2104 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 2105 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 2106 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 2107 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 2108 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 2109 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 2110 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 2111 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 2112 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 2113 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 2114 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 2115 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 2116 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 2117 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 2118 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 2119 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 2120 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 2121 2122 /****************** Bit definition for DBGMCU_CR register *******************/ 2123 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 2124 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 2125 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 2126 #define DBGMCU_CR_DBG_STOP_Pos (1U) 2127 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 2128 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 2129 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 2130 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 2131 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 2132 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 2133 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 2134 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 2135 2136 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 2137 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 2138 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 2139 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 2140 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 2141 2142 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 2143 2144 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 2145 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 2146 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 2147 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 2148 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 2149 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 2150 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 2151 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ 2152 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 2153 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) 2154 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ 2155 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ 2156 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 2157 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 2158 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 2159 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 2160 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 2161 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 2162 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 2163 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 2164 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */ 2165 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 2166 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 2167 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 2168 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 2169 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 2170 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 2171 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 2172 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 2173 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2174 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 2175 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 2176 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2177 2178 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 2179 2180 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) 2181 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */ 2182 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */ 2183 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) 2184 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */ 2185 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */ 2186 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) 2187 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */ 2188 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */ 2189 2190 /******************************************************************************/ 2191 /* */ 2192 /* DMA Controller (DMA) */ 2193 /* */ 2194 /******************************************************************************/ 2195 2196 /******************* Bit definition for DMA_ISR register ********************/ 2197 #define DMA_ISR_GIF1_Pos (0U) 2198 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2199 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2200 #define DMA_ISR_TCIF1_Pos (1U) 2201 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2202 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2203 #define DMA_ISR_HTIF1_Pos (2U) 2204 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2205 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2206 #define DMA_ISR_TEIF1_Pos (3U) 2207 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2208 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2209 #define DMA_ISR_GIF2_Pos (4U) 2210 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2211 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2212 #define DMA_ISR_TCIF2_Pos (5U) 2213 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2214 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2215 #define DMA_ISR_HTIF2_Pos (6U) 2216 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2217 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2218 #define DMA_ISR_TEIF2_Pos (7U) 2219 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2220 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2221 #define DMA_ISR_GIF3_Pos (8U) 2222 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2223 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2224 #define DMA_ISR_TCIF3_Pos (9U) 2225 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2226 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2227 #define DMA_ISR_HTIF3_Pos (10U) 2228 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2229 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2230 #define DMA_ISR_TEIF3_Pos (11U) 2231 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2232 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2233 #define DMA_ISR_GIF4_Pos (12U) 2234 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2235 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2236 #define DMA_ISR_TCIF4_Pos (13U) 2237 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2238 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2239 #define DMA_ISR_HTIF4_Pos (14U) 2240 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2241 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2242 #define DMA_ISR_TEIF4_Pos (15U) 2243 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2244 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2245 #define DMA_ISR_GIF5_Pos (16U) 2246 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2247 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2248 #define DMA_ISR_TCIF5_Pos (17U) 2249 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2250 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2251 #define DMA_ISR_HTIF5_Pos (18U) 2252 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2253 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2254 #define DMA_ISR_TEIF5_Pos (19U) 2255 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2256 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2257 #define DMA_ISR_GIF6_Pos (20U) 2258 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2259 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2260 #define DMA_ISR_TCIF6_Pos (21U) 2261 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2262 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2263 #define DMA_ISR_HTIF6_Pos (22U) 2264 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2265 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2266 #define DMA_ISR_TEIF6_Pos (23U) 2267 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2268 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2269 #define DMA_ISR_GIF7_Pos (24U) 2270 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2271 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2272 #define DMA_ISR_TCIF7_Pos (25U) 2273 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2274 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2275 #define DMA_ISR_HTIF7_Pos (26U) 2276 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2277 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2278 #define DMA_ISR_TEIF7_Pos (27U) 2279 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2280 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2281 2282 /******************* Bit definition for DMA_IFCR register *******************/ 2283 #define DMA_IFCR_CGIF1_Pos (0U) 2284 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2285 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2286 #define DMA_IFCR_CTCIF1_Pos (1U) 2287 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2288 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2289 #define DMA_IFCR_CHTIF1_Pos (2U) 2290 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2291 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2292 #define DMA_IFCR_CTEIF1_Pos (3U) 2293 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2294 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2295 #define DMA_IFCR_CGIF2_Pos (4U) 2296 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2297 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2298 #define DMA_IFCR_CTCIF2_Pos (5U) 2299 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2300 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2301 #define DMA_IFCR_CHTIF2_Pos (6U) 2302 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2303 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2304 #define DMA_IFCR_CTEIF2_Pos (7U) 2305 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2306 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2307 #define DMA_IFCR_CGIF3_Pos (8U) 2308 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2309 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2310 #define DMA_IFCR_CTCIF3_Pos (9U) 2311 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2312 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2313 #define DMA_IFCR_CHTIF3_Pos (10U) 2314 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2315 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2316 #define DMA_IFCR_CTEIF3_Pos (11U) 2317 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2318 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2319 #define DMA_IFCR_CGIF4_Pos (12U) 2320 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2321 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2322 #define DMA_IFCR_CTCIF4_Pos (13U) 2323 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2324 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2325 #define DMA_IFCR_CHTIF4_Pos (14U) 2326 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2327 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2328 #define DMA_IFCR_CTEIF4_Pos (15U) 2329 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2330 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2331 #define DMA_IFCR_CGIF5_Pos (16U) 2332 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2333 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2334 #define DMA_IFCR_CTCIF5_Pos (17U) 2335 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2336 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2337 #define DMA_IFCR_CHTIF5_Pos (18U) 2338 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2339 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2340 #define DMA_IFCR_CTEIF5_Pos (19U) 2341 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2342 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2343 #define DMA_IFCR_CGIF6_Pos (20U) 2344 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2345 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2346 #define DMA_IFCR_CTCIF6_Pos (21U) 2347 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2348 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2349 #define DMA_IFCR_CHTIF6_Pos (22U) 2350 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2351 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2352 #define DMA_IFCR_CTEIF6_Pos (23U) 2353 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2354 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2355 #define DMA_IFCR_CGIF7_Pos (24U) 2356 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2357 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2358 #define DMA_IFCR_CTCIF7_Pos (25U) 2359 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2360 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2361 #define DMA_IFCR_CHTIF7_Pos (26U) 2362 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2363 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2364 #define DMA_IFCR_CTEIF7_Pos (27U) 2365 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2366 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2367 2368 /******************* Bit definition for DMA_CCR register *******************/ 2369 #define DMA_CCR_EN_Pos (0U) 2370 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2371 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/ 2372 #define DMA_CCR_TCIE_Pos (1U) 2373 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2374 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2375 #define DMA_CCR_HTIE_Pos (2U) 2376 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2377 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2378 #define DMA_CCR_TEIE_Pos (3U) 2379 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2380 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2381 #define DMA_CCR_DIR_Pos (4U) 2382 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2383 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2384 #define DMA_CCR_CIRC_Pos (5U) 2385 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2386 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2387 #define DMA_CCR_PINC_Pos (6U) 2388 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2389 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2390 #define DMA_CCR_MINC_Pos (7U) 2391 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2392 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2393 2394 #define DMA_CCR_PSIZE_Pos (8U) 2395 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2396 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2397 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2398 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2399 2400 #define DMA_CCR_MSIZE_Pos (10U) 2401 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2402 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2403 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2404 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2405 2406 #define DMA_CCR_PL_Pos (12U) 2407 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2408 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 2409 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2410 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2411 2412 #define DMA_CCR_MEM2MEM_Pos (14U) 2413 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2414 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2415 2416 /****************** Bit definition generic for DMA_CNDTR register *******************/ 2417 #define DMA_CNDTR_NDT_Pos (0U) 2418 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2419 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2420 2421 /****************** Bit definition for DMA_CNDTR1 register ******************/ 2422 #define DMA_CNDTR1_NDT_Pos (0U) 2423 #define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */ 2424 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */ 2425 2426 /****************** Bit definition for DMA_CNDTR2 register ******************/ 2427 #define DMA_CNDTR2_NDT_Pos (0U) 2428 #define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */ 2429 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */ 2430 2431 /****************** Bit definition for DMA_CNDTR3 register ******************/ 2432 #define DMA_CNDTR3_NDT_Pos (0U) 2433 #define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */ 2434 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */ 2435 2436 /****************** Bit definition for DMA_CNDTR4 register ******************/ 2437 #define DMA_CNDTR4_NDT_Pos (0U) 2438 #define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */ 2439 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */ 2440 2441 /****************** Bit definition for DMA_CNDTR5 register ******************/ 2442 #define DMA_CNDTR5_NDT_Pos (0U) 2443 #define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */ 2444 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */ 2445 2446 /****************** Bit definition for DMA_CNDTR6 register ******************/ 2447 #define DMA_CNDTR6_NDT_Pos (0U) 2448 #define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */ 2449 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */ 2450 2451 /****************** Bit definition for DMA_CNDTR7 register ******************/ 2452 #define DMA_CNDTR7_NDT_Pos (0U) 2453 #define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */ 2454 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */ 2455 2456 /****************** Bit definition generic for DMA_CPAR register ********************/ 2457 #define DMA_CPAR_PA_Pos (0U) 2458 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2459 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2460 2461 /****************** Bit definition for DMA_CPAR1 register *******************/ 2462 #define DMA_CPAR1_PA_Pos (0U) 2463 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */ 2464 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */ 2465 2466 /****************** Bit definition for DMA_CPAR2 register *******************/ 2467 #define DMA_CPAR2_PA_Pos (0U) 2468 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */ 2469 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */ 2470 2471 /****************** Bit definition for DMA_CPAR3 register *******************/ 2472 #define DMA_CPAR3_PA_Pos (0U) 2473 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */ 2474 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */ 2475 2476 2477 /****************** Bit definition for DMA_CPAR4 register *******************/ 2478 #define DMA_CPAR4_PA_Pos (0U) 2479 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */ 2480 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */ 2481 2482 /****************** Bit definition for DMA_CPAR5 register *******************/ 2483 #define DMA_CPAR5_PA_Pos (0U) 2484 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */ 2485 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */ 2486 2487 /****************** Bit definition for DMA_CPAR6 register *******************/ 2488 #define DMA_CPAR6_PA_Pos (0U) 2489 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */ 2490 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */ 2491 2492 2493 /****************** Bit definition for DMA_CPAR7 register *******************/ 2494 #define DMA_CPAR7_PA_Pos (0U) 2495 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */ 2496 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */ 2497 2498 /****************** Bit definition generic for DMA_CMAR register ********************/ 2499 #define DMA_CMAR_MA_Pos (0U) 2500 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2501 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2502 2503 /****************** Bit definition for DMA_CMAR1 register *******************/ 2504 #define DMA_CMAR1_MA_Pos (0U) 2505 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */ 2506 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */ 2507 2508 /****************** Bit definition for DMA_CMAR2 register *******************/ 2509 #define DMA_CMAR2_MA_Pos (0U) 2510 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */ 2511 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */ 2512 2513 /****************** Bit definition for DMA_CMAR3 register *******************/ 2514 #define DMA_CMAR3_MA_Pos (0U) 2515 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */ 2516 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */ 2517 2518 2519 /****************** Bit definition for DMA_CMAR4 register *******************/ 2520 #define DMA_CMAR4_MA_Pos (0U) 2521 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */ 2522 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */ 2523 2524 /****************** Bit definition for DMA_CMAR5 register *******************/ 2525 #define DMA_CMAR5_MA_Pos (0U) 2526 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */ 2527 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */ 2528 2529 /****************** Bit definition for DMA_CMAR6 register *******************/ 2530 #define DMA_CMAR6_MA_Pos (0U) 2531 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */ 2532 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */ 2533 2534 /****************** Bit definition for DMA_CMAR7 register *******************/ 2535 #define DMA_CMAR7_MA_Pos (0U) 2536 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */ 2537 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */ 2538 2539 /******************************************************************************/ 2540 /* */ 2541 /* External Interrupt/Event Controller (EXTI) */ 2542 /* */ 2543 /******************************************************************************/ 2544 2545 /******************* Bit definition for EXTI_IMR register *******************/ 2546 #define EXTI_IMR_MR0_Pos (0U) 2547 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2548 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2549 #define EXTI_IMR_MR1_Pos (1U) 2550 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2551 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2552 #define EXTI_IMR_MR2_Pos (2U) 2553 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2554 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2555 #define EXTI_IMR_MR3_Pos (3U) 2556 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2557 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2558 #define EXTI_IMR_MR4_Pos (4U) 2559 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2560 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2561 #define EXTI_IMR_MR5_Pos (5U) 2562 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2563 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2564 #define EXTI_IMR_MR6_Pos (6U) 2565 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2566 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2567 #define EXTI_IMR_MR7_Pos (7U) 2568 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2569 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2570 #define EXTI_IMR_MR8_Pos (8U) 2571 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2572 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2573 #define EXTI_IMR_MR9_Pos (9U) 2574 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2575 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2576 #define EXTI_IMR_MR10_Pos (10U) 2577 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2578 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2579 #define EXTI_IMR_MR11_Pos (11U) 2580 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2581 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2582 #define EXTI_IMR_MR12_Pos (12U) 2583 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2584 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2585 #define EXTI_IMR_MR13_Pos (13U) 2586 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2587 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2588 #define EXTI_IMR_MR14_Pos (14U) 2589 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2590 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2591 #define EXTI_IMR_MR15_Pos (15U) 2592 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2593 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2594 #define EXTI_IMR_MR16_Pos (16U) 2595 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2596 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2597 #define EXTI_IMR_MR17_Pos (17U) 2598 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2599 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2600 #define EXTI_IMR_MR18_Pos (18U) 2601 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 2602 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 2603 #define EXTI_IMR_MR19_Pos (19U) 2604 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 2605 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 2606 #define EXTI_IMR_MR20_Pos (20U) 2607 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 2608 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 2609 #define EXTI_IMR_MR21_Pos (21U) 2610 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 2611 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 2612 #define EXTI_IMR_MR22_Pos (22U) 2613 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 2614 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 2615 #define EXTI_IMR_MR23_Pos (23U) 2616 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 2617 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 2618 2619 /* References Defines */ 2620 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2621 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2622 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2623 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2624 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2625 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2626 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2627 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2628 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2629 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2630 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2631 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2632 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2633 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2634 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2635 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2636 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2637 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2638 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2639 #define EXTI_IMR_IM19 EXTI_IMR_MR19 2640 #define EXTI_IMR_IM20 EXTI_IMR_MR20 2641 #define EXTI_IMR_IM21 EXTI_IMR_MR21 2642 #define EXTI_IMR_IM22 EXTI_IMR_MR22 2643 /* Category 3, 4 & 5 */ 2644 #define EXTI_IMR_IM23 EXTI_IMR_MR23 2645 #define EXTI_IMR_IM_Pos (0U) 2646 #define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */ 2647 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 2648 2649 /******************* Bit definition for EXTI_EMR register *******************/ 2650 #define EXTI_EMR_MR0_Pos (0U) 2651 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2652 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2653 #define EXTI_EMR_MR1_Pos (1U) 2654 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2655 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2656 #define EXTI_EMR_MR2_Pos (2U) 2657 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2658 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2659 #define EXTI_EMR_MR3_Pos (3U) 2660 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2661 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2662 #define EXTI_EMR_MR4_Pos (4U) 2663 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2664 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2665 #define EXTI_EMR_MR5_Pos (5U) 2666 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2667 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2668 #define EXTI_EMR_MR6_Pos (6U) 2669 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2670 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2671 #define EXTI_EMR_MR7_Pos (7U) 2672 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2673 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2674 #define EXTI_EMR_MR8_Pos (8U) 2675 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2676 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2677 #define EXTI_EMR_MR9_Pos (9U) 2678 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2679 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2680 #define EXTI_EMR_MR10_Pos (10U) 2681 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2682 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2683 #define EXTI_EMR_MR11_Pos (11U) 2684 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2685 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2686 #define EXTI_EMR_MR12_Pos (12U) 2687 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2688 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2689 #define EXTI_EMR_MR13_Pos (13U) 2690 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2691 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2692 #define EXTI_EMR_MR14_Pos (14U) 2693 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2694 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2695 #define EXTI_EMR_MR15_Pos (15U) 2696 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2697 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2698 #define EXTI_EMR_MR16_Pos (16U) 2699 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2700 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2701 #define EXTI_EMR_MR17_Pos (17U) 2702 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2703 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2704 #define EXTI_EMR_MR18_Pos (18U) 2705 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 2706 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 2707 #define EXTI_EMR_MR19_Pos (19U) 2708 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 2709 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 2710 #define EXTI_EMR_MR20_Pos (20U) 2711 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 2712 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 2713 #define EXTI_EMR_MR21_Pos (21U) 2714 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 2715 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 2716 #define EXTI_EMR_MR22_Pos (22U) 2717 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 2718 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 2719 #define EXTI_EMR_MR23_Pos (23U) 2720 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 2721 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 2722 2723 /* References Defines */ 2724 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2725 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2726 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2727 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2728 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2729 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2730 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2731 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2732 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2733 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2734 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2735 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2736 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2737 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2738 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2739 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2740 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2741 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2742 #define EXTI_EMR_EM18 EXTI_EMR_MR18 2743 #define EXTI_EMR_EM19 EXTI_EMR_MR19 2744 #define EXTI_EMR_EM20 EXTI_EMR_MR20 2745 #define EXTI_EMR_EM21 EXTI_EMR_MR21 2746 #define EXTI_EMR_EM22 EXTI_EMR_MR22 2747 #define EXTI_EMR_EM23 EXTI_EMR_MR23 2748 2749 /****************** Bit definition for EXTI_RTSR register *******************/ 2750 #define EXTI_RTSR_TR0_Pos (0U) 2751 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2752 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2753 #define EXTI_RTSR_TR1_Pos (1U) 2754 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2755 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2756 #define EXTI_RTSR_TR2_Pos (2U) 2757 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2758 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2759 #define EXTI_RTSR_TR3_Pos (3U) 2760 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2761 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2762 #define EXTI_RTSR_TR4_Pos (4U) 2763 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2764 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2765 #define EXTI_RTSR_TR5_Pos (5U) 2766 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2767 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2768 #define EXTI_RTSR_TR6_Pos (6U) 2769 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2770 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2771 #define EXTI_RTSR_TR7_Pos (7U) 2772 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2773 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2774 #define EXTI_RTSR_TR8_Pos (8U) 2775 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2776 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2777 #define EXTI_RTSR_TR9_Pos (9U) 2778 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2779 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2780 #define EXTI_RTSR_TR10_Pos (10U) 2781 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2782 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2783 #define EXTI_RTSR_TR11_Pos (11U) 2784 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2785 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2786 #define EXTI_RTSR_TR12_Pos (12U) 2787 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2788 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2789 #define EXTI_RTSR_TR13_Pos (13U) 2790 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2791 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2792 #define EXTI_RTSR_TR14_Pos (14U) 2793 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2794 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2795 #define EXTI_RTSR_TR15_Pos (15U) 2796 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2797 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2798 #define EXTI_RTSR_TR16_Pos (16U) 2799 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2800 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2801 #define EXTI_RTSR_TR17_Pos (17U) 2802 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2803 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2804 #define EXTI_RTSR_TR18_Pos (18U) 2805 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 2806 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2807 #define EXTI_RTSR_TR19_Pos (19U) 2808 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 2809 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 2810 #define EXTI_RTSR_TR20_Pos (20U) 2811 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 2812 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 2813 #define EXTI_RTSR_TR21_Pos (21U) 2814 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 2815 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 2816 #define EXTI_RTSR_TR22_Pos (22U) 2817 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 2818 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 2819 #define EXTI_RTSR_TR23_Pos (23U) 2820 #define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */ 2821 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */ 2822 2823 /* References Defines */ 2824 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2825 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2826 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2827 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2828 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2829 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2830 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2831 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2832 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2833 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2834 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2835 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2836 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2837 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2838 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2839 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2840 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2841 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2842 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 2843 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 2844 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 2845 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 2846 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 2847 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 2848 2849 /****************** Bit definition for EXTI_FTSR register *******************/ 2850 #define EXTI_FTSR_TR0_Pos (0U) 2851 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2852 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2853 #define EXTI_FTSR_TR1_Pos (1U) 2854 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2855 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2856 #define EXTI_FTSR_TR2_Pos (2U) 2857 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2858 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2859 #define EXTI_FTSR_TR3_Pos (3U) 2860 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2861 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2862 #define EXTI_FTSR_TR4_Pos (4U) 2863 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2864 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2865 #define EXTI_FTSR_TR5_Pos (5U) 2866 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2867 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2868 #define EXTI_FTSR_TR6_Pos (6U) 2869 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2870 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2871 #define EXTI_FTSR_TR7_Pos (7U) 2872 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2873 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2874 #define EXTI_FTSR_TR8_Pos (8U) 2875 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2876 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2877 #define EXTI_FTSR_TR9_Pos (9U) 2878 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2879 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2880 #define EXTI_FTSR_TR10_Pos (10U) 2881 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2882 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2883 #define EXTI_FTSR_TR11_Pos (11U) 2884 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2885 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2886 #define EXTI_FTSR_TR12_Pos (12U) 2887 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2888 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2889 #define EXTI_FTSR_TR13_Pos (13U) 2890 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2891 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2892 #define EXTI_FTSR_TR14_Pos (14U) 2893 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2894 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2895 #define EXTI_FTSR_TR15_Pos (15U) 2896 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2897 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2898 #define EXTI_FTSR_TR16_Pos (16U) 2899 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2900 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2901 #define EXTI_FTSR_TR17_Pos (17U) 2902 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2903 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2904 #define EXTI_FTSR_TR18_Pos (18U) 2905 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 2906 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2907 #define EXTI_FTSR_TR19_Pos (19U) 2908 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 2909 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 2910 #define EXTI_FTSR_TR20_Pos (20U) 2911 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 2912 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 2913 #define EXTI_FTSR_TR21_Pos (21U) 2914 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 2915 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 2916 #define EXTI_FTSR_TR22_Pos (22U) 2917 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 2918 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 2919 #define EXTI_FTSR_TR23_Pos (23U) 2920 #define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */ 2921 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */ 2922 2923 /* References Defines */ 2924 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2925 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2926 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2927 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2928 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2929 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2930 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2931 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2932 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2933 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2934 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2935 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2936 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2937 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2938 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2939 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2940 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2941 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2942 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 2943 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 2944 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 2945 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 2946 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 2947 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 2948 2949 /****************** Bit definition for EXTI_SWIER register ******************/ 2950 #define EXTI_SWIER_SWIER0_Pos (0U) 2951 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2952 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2953 #define EXTI_SWIER_SWIER1_Pos (1U) 2954 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2955 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2956 #define EXTI_SWIER_SWIER2_Pos (2U) 2957 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2958 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2959 #define EXTI_SWIER_SWIER3_Pos (3U) 2960 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2961 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2962 #define EXTI_SWIER_SWIER4_Pos (4U) 2963 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2964 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2965 #define EXTI_SWIER_SWIER5_Pos (5U) 2966 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2967 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2968 #define EXTI_SWIER_SWIER6_Pos (6U) 2969 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2970 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2971 #define EXTI_SWIER_SWIER7_Pos (7U) 2972 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2973 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2974 #define EXTI_SWIER_SWIER8_Pos (8U) 2975 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2976 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2977 #define EXTI_SWIER_SWIER9_Pos (9U) 2978 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2979 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2980 #define EXTI_SWIER_SWIER10_Pos (10U) 2981 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2982 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2983 #define EXTI_SWIER_SWIER11_Pos (11U) 2984 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2985 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2986 #define EXTI_SWIER_SWIER12_Pos (12U) 2987 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2988 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2989 #define EXTI_SWIER_SWIER13_Pos (13U) 2990 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2991 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2992 #define EXTI_SWIER_SWIER14_Pos (14U) 2993 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2994 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2995 #define EXTI_SWIER_SWIER15_Pos (15U) 2996 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2997 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2998 #define EXTI_SWIER_SWIER16_Pos (16U) 2999 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 3000 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 3001 #define EXTI_SWIER_SWIER17_Pos (17U) 3002 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 3003 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 3004 #define EXTI_SWIER_SWIER18_Pos (18U) 3005 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 3006 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 3007 #define EXTI_SWIER_SWIER19_Pos (19U) 3008 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 3009 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 3010 #define EXTI_SWIER_SWIER20_Pos (20U) 3011 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 3012 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 3013 #define EXTI_SWIER_SWIER21_Pos (21U) 3014 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 3015 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 3016 #define EXTI_SWIER_SWIER22_Pos (22U) 3017 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 3018 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 3019 #define EXTI_SWIER_SWIER23_Pos (23U) 3020 #define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */ 3021 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */ 3022 3023 /* References Defines */ 3024 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 3025 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 3026 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 3027 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 3028 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 3029 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 3030 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 3031 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 3032 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 3033 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 3034 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 3035 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 3036 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 3037 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 3038 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 3039 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 3040 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 3041 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 3042 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 3043 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 3044 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 3045 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 3046 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 3047 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 3048 3049 /******************* Bit definition for EXTI_PR register ********************/ 3050 #define EXTI_PR_PR0_Pos (0U) 3051 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 3052 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 3053 #define EXTI_PR_PR1_Pos (1U) 3054 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 3055 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 3056 #define EXTI_PR_PR2_Pos (2U) 3057 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 3058 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 3059 #define EXTI_PR_PR3_Pos (3U) 3060 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 3061 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 3062 #define EXTI_PR_PR4_Pos (4U) 3063 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 3064 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 3065 #define EXTI_PR_PR5_Pos (5U) 3066 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 3067 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 3068 #define EXTI_PR_PR6_Pos (6U) 3069 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 3070 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 3071 #define EXTI_PR_PR7_Pos (7U) 3072 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 3073 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 3074 #define EXTI_PR_PR8_Pos (8U) 3075 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 3076 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 3077 #define EXTI_PR_PR9_Pos (9U) 3078 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 3079 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 3080 #define EXTI_PR_PR10_Pos (10U) 3081 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 3082 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 3083 #define EXTI_PR_PR11_Pos (11U) 3084 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 3085 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 3086 #define EXTI_PR_PR12_Pos (12U) 3087 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3088 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3089 #define EXTI_PR_PR13_Pos (13U) 3090 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3091 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3092 #define EXTI_PR_PR14_Pos (14U) 3093 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3094 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3095 #define EXTI_PR_PR15_Pos (15U) 3096 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3097 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3098 #define EXTI_PR_PR16_Pos (16U) 3099 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3100 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3101 #define EXTI_PR_PR17_Pos (17U) 3102 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3103 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3104 #define EXTI_PR_PR18_Pos (18U) 3105 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 3106 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 3107 #define EXTI_PR_PR19_Pos (19U) 3108 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 3109 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 3110 #define EXTI_PR_PR20_Pos (20U) 3111 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 3112 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 3113 #define EXTI_PR_PR21_Pos (21U) 3114 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 3115 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ 3116 #define EXTI_PR_PR22_Pos (22U) 3117 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 3118 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 3119 #define EXTI_PR_PR23_Pos (23U) 3120 #define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */ 3121 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */ 3122 3123 /* References Defines */ 3124 #define EXTI_PR_PIF0 EXTI_PR_PR0 3125 #define EXTI_PR_PIF1 EXTI_PR_PR1 3126 #define EXTI_PR_PIF2 EXTI_PR_PR2 3127 #define EXTI_PR_PIF3 EXTI_PR_PR3 3128 #define EXTI_PR_PIF4 EXTI_PR_PR4 3129 #define EXTI_PR_PIF5 EXTI_PR_PR5 3130 #define EXTI_PR_PIF6 EXTI_PR_PR6 3131 #define EXTI_PR_PIF7 EXTI_PR_PR7 3132 #define EXTI_PR_PIF8 EXTI_PR_PR8 3133 #define EXTI_PR_PIF9 EXTI_PR_PR9 3134 #define EXTI_PR_PIF10 EXTI_PR_PR10 3135 #define EXTI_PR_PIF11 EXTI_PR_PR11 3136 #define EXTI_PR_PIF12 EXTI_PR_PR12 3137 #define EXTI_PR_PIF13 EXTI_PR_PR13 3138 #define EXTI_PR_PIF14 EXTI_PR_PR14 3139 #define EXTI_PR_PIF15 EXTI_PR_PR15 3140 #define EXTI_PR_PIF16 EXTI_PR_PR16 3141 #define EXTI_PR_PIF17 EXTI_PR_PR17 3142 #define EXTI_PR_PIF18 EXTI_PR_PR18 3143 #define EXTI_PR_PIF19 EXTI_PR_PR19 3144 #define EXTI_PR_PIF20 EXTI_PR_PR20 3145 #define EXTI_PR_PIF21 EXTI_PR_PR21 3146 #define EXTI_PR_PIF22 EXTI_PR_PR22 3147 #define EXTI_PR_PIF23 EXTI_PR_PR23 3148 3149 /******************************************************************************/ 3150 /* */ 3151 /* FLASH, DATA EEPROM and Option Bytes Registers */ 3152 /* (FLASH, DATA_EEPROM, OB) */ 3153 /* */ 3154 /******************************************************************************/ 3155 /* 3156 * @brief Specific device feature definitions (not present on all devices in the STM32L1 series) 3157 */ 3158 #define FLASH_CUT4 3159 3160 /******************* Bit definition for FLASH_ACR register ******************/ 3161 #define FLASH_ACR_LATENCY_Pos (0U) 3162 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3163 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 3164 #define FLASH_ACR_PRFTEN_Pos (1U) 3165 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 3166 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 3167 #define FLASH_ACR_ACC64_Pos (2U) 3168 #define FLASH_ACR_ACC64_Msk (0x1UL << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */ 3169 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */ 3170 #define FLASH_ACR_SLEEP_PD_Pos (3U) 3171 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 3172 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 3173 #define FLASH_ACR_RUN_PD_Pos (4U) 3174 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 3175 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 3176 3177 /******************* Bit definition for FLASH_PECR register ******************/ 3178 #define FLASH_PECR_PELOCK_Pos (0U) 3179 #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 3180 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 3181 #define FLASH_PECR_PRGLOCK_Pos (1U) 3182 #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 3183 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 3184 #define FLASH_PECR_OPTLOCK_Pos (2U) 3185 #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 3186 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 3187 #define FLASH_PECR_PROG_Pos (3U) 3188 #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 3189 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 3190 #define FLASH_PECR_DATA_Pos (4U) 3191 #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 3192 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 3193 #define FLASH_PECR_FTDW_Pos (8U) 3194 #define FLASH_PECR_FTDW_Msk (0x1UL << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */ 3195 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 3196 #define FLASH_PECR_ERASE_Pos (9U) 3197 #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 3198 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 3199 #define FLASH_PECR_FPRG_Pos (10U) 3200 #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 3201 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 3202 #define FLASH_PECR_PARALLBANK_Pos (15U) 3203 #define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ 3204 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ 3205 #define FLASH_PECR_EOPIE_Pos (16U) 3206 #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 3207 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 3208 #define FLASH_PECR_ERRIE_Pos (17U) 3209 #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 3210 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 3211 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 3212 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 3213 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 3214 3215 /****************** Bit definition for FLASH_PDKEYR register ******************/ 3216 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 3217 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 3218 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3219 3220 /****************** Bit definition for FLASH_PEKEYR register ******************/ 3221 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 3222 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 3223 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3224 3225 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 3226 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 3227 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 3228 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 3229 3230 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 3231 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 3232 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 3233 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 3234 3235 /****************** Bit definition for FLASH_SR register *******************/ 3236 #define FLASH_SR_BSY_Pos (0U) 3237 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 3238 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 3239 #define FLASH_SR_EOP_Pos (1U) 3240 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 3241 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 3242 #define FLASH_SR_ENDHV_Pos (2U) 3243 #define FLASH_SR_ENDHV_Msk (0x1UL << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */ 3244 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */ 3245 #define FLASH_SR_READY_Pos (3U) 3246 #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 3247 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 3248 3249 #define FLASH_SR_WRPERR_Pos (8U) 3250 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 3251 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */ 3252 #define FLASH_SR_PGAERR_Pos (9U) 3253 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 3254 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 3255 #define FLASH_SR_SIZERR_Pos (10U) 3256 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 3257 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 3258 #define FLASH_SR_OPTVERR_Pos (11U) 3259 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 3260 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 3261 #define FLASH_SR_OPTVERRUSR_Pos (12U) 3262 #define FLASH_SR_OPTVERRUSR_Msk (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */ 3263 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */ 3264 3265 /****************** Bit definition for FLASH_OBR register *******************/ 3266 #define FLASH_OBR_RDPRT_Pos (0U) 3267 #define FLASH_OBR_RDPRT_Msk (0xFFUL << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */ 3268 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */ 3269 #define FLASH_OBR_BOR_LEV_Pos (16U) 3270 #define FLASH_OBR_BOR_LEV_Msk (0xFUL << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */ 3271 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 3272 #define FLASH_OBR_USER_Pos (20U) 3273 #define FLASH_OBR_USER_Msk (0xFUL << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */ 3274 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 3275 #define FLASH_OBR_IWDG_SW_Pos (20U) 3276 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */ 3277 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */ 3278 #define FLASH_OBR_nRST_STOP_Pos (21U) 3279 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */ 3280 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 3281 #define FLASH_OBR_nRST_STDBY_Pos (22U) 3282 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */ 3283 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 3284 #define FLASH_OBR_nRST_BFB2_Pos (23U) 3285 #define FLASH_OBR_nRST_BFB2_Msk (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */ 3286 #define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */ 3287 3288 /****************** Bit definition for FLASH_WRPR register ******************/ 3289 #define FLASH_WRPR1_WRP_Pos (0U) 3290 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */ 3291 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */ 3292 #define FLASH_WRPR2_WRP_Pos (0U) 3293 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */ 3294 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */ 3295 #define FLASH_WRPR3_WRP_Pos (0U) 3296 #define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */ 3297 #define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */ 3298 3299 /******************************************************************************/ 3300 /* */ 3301 /* Flexible Static Memory Controller */ 3302 /* */ 3303 /******************************************************************************/ 3304 /****************** Bit definition for FSMC_BCRx register (x=1..4) *******************/ 3305 #define FSMC_BCRx_MBKEN_Pos (0U) 3306 #define FSMC_BCRx_MBKEN_Msk (0x1UL << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */ 3307 #define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */ 3308 #define FSMC_BCRx_MUXEN_Pos (1U) 3309 #define FSMC_BCRx_MUXEN_Msk (0x1UL << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */ 3310 #define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */ 3311 3312 #define FSMC_BCRx_MTYP_Pos (2U) 3313 #define FSMC_BCRx_MTYP_Msk (0x3UL << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */ 3314 #define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */ 3315 #define FSMC_BCRx_MTYP_0 (0x1UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */ 3316 #define FSMC_BCRx_MTYP_1 (0x2UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */ 3317 3318 #define FSMC_BCRx_MWID_Pos (4U) 3319 #define FSMC_BCRx_MWID_Msk (0x3UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */ 3320 #define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */ 3321 #define FSMC_BCRx_MWID_0 (0x1UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */ 3322 #define FSMC_BCRx_MWID_1 (0x2UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */ 3323 3324 #define FSMC_BCRx_FACCEN_Pos (6U) 3325 #define FSMC_BCRx_FACCEN_Msk (0x1UL << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */ 3326 #define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */ 3327 #define FSMC_BCRx_BURSTEN_Pos (8U) 3328 #define FSMC_BCRx_BURSTEN_Msk (0x1UL << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */ 3329 #define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */ 3330 #define FSMC_BCRx_WAITPOL_Pos (9U) 3331 #define FSMC_BCRx_WAITPOL_Msk (0x1UL << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */ 3332 #define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */ 3333 #define FSMC_BCRx_WRAPMOD_Pos (10U) 3334 #define FSMC_BCRx_WRAPMOD_Msk (0x1UL << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */ 3335 #define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */ 3336 #define FSMC_BCRx_WAITCFG_Pos (11U) 3337 #define FSMC_BCRx_WAITCFG_Msk (0x1UL << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */ 3338 #define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */ 3339 #define FSMC_BCRx_WREN_Pos (12U) 3340 #define FSMC_BCRx_WREN_Msk (0x1UL << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */ 3341 #define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */ 3342 #define FSMC_BCRx_WAITEN_Pos (13U) 3343 #define FSMC_BCRx_WAITEN_Msk (0x1UL << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */ 3344 #define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */ 3345 #define FSMC_BCRx_EXTMOD_Pos (14U) 3346 #define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ 3347 #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ 3348 #define FSMC_BCRx_ASYNCWAIT_Pos (15U) 3349 #define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ 3350 #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ 3351 #define FSMC_BCRx_CPSIZE_Pos (16U) 3352 #define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */ 3353 #define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */ 3354 #define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */ 3355 #define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */ 3356 #define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */ 3357 #define FSMC_BCRx_CBURSTRW_Pos (19U) 3358 #define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ 3359 #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ 3360 3361 /****************** Bit definition for FSMC_BTRx register (x=1..4) ******************/ 3362 #define FSMC_BTRx_ADDSET_Pos (0U) 3363 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */ 3364 #define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 3365 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */ 3366 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */ 3367 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */ 3368 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */ 3369 3370 #define FSMC_BTRx_ADDHLD_Pos (4U) 3371 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 3372 #define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 3373 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */ 3374 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */ 3375 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */ 3376 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */ 3377 3378 #define FSMC_BTRx_DATAST_Pos (8U) 3379 #define FSMC_BTRx_DATAST_Msk (0xFFUL << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */ 3380 #define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ 3381 #define FSMC_BTRx_DATAST_0 (0x01UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */ 3382 #define FSMC_BTRx_DATAST_1 (0x02UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */ 3383 #define FSMC_BTRx_DATAST_2 (0x04UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */ 3384 #define FSMC_BTRx_DATAST_3 (0x08UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */ 3385 #define FSMC_BTRx_DATAST_4 (0x10UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */ 3386 #define FSMC_BTRx_DATAST_5 (0x20UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */ 3387 #define FSMC_BTRx_DATAST_6 (0x40UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */ 3388 #define FSMC_BTRx_DATAST_7 (0x80UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */ 3389 3390 #define FSMC_BTRx_BUSTURN_Pos (16U) 3391 #define FSMC_BTRx_BUSTURN_Msk (0xFUL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */ 3392 #define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ 3393 #define FSMC_BTRx_BUSTURN_0 (0x1UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */ 3394 #define FSMC_BTRx_BUSTURN_1 (0x2UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */ 3395 #define FSMC_BTRx_BUSTURN_2 (0x4UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */ 3396 #define FSMC_BTRx_BUSTURN_3 (0x8UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */ 3397 3398 #define FSMC_BTRx_CLKDIV_Pos (20U) 3399 #define FSMC_BTRx_CLKDIV_Msk (0xFUL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */ 3400 #define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */ 3401 #define FSMC_BTRx_CLKDIV_0 (0x1UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */ 3402 #define FSMC_BTRx_CLKDIV_1 (0x2UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */ 3403 #define FSMC_BTRx_CLKDIV_2 (0x4UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */ 3404 #define FSMC_BTRx_CLKDIV_3 (0x8UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */ 3405 3406 #define FSMC_BTRx_DATLAT_Pos (24U) 3407 #define FSMC_BTRx_DATLAT_Msk (0xFUL << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */ 3408 #define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */ 3409 #define FSMC_BTRx_DATLAT_0 (0x1UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */ 3410 #define FSMC_BTRx_DATLAT_1 (0x2UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */ 3411 #define FSMC_BTRx_DATLAT_2 (0x4UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */ 3412 #define FSMC_BTRx_DATLAT_3 (0x8UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */ 3413 3414 #define FSMC_BTRx_ACCMOD_Pos (28U) 3415 #define FSMC_BTRx_ACCMOD_Msk (0x3UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */ 3416 #define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 3417 #define FSMC_BTRx_ACCMOD_0 (0x1UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */ 3418 #define FSMC_BTRx_ACCMOD_1 (0x2UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */ 3419 3420 /****************** Bit definition for FSMC_BWTRx register (x=1..4) ******************/ 3421 #define FSMC_BWTRx_ADDSET_Pos (0U) 3422 #define FSMC_BWTRx_ADDSET_Msk (0xFUL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */ 3423 #define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 3424 #define FSMC_BWTRx_ADDSET_0 (0x1UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */ 3425 #define FSMC_BWTRx_ADDSET_1 (0x2UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */ 3426 #define FSMC_BWTRx_ADDSET_2 (0x4UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */ 3427 #define FSMC_BWTRx_ADDSET_3 (0x8UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */ 3428 3429 #define FSMC_BWTRx_ADDHLD_Pos (4U) 3430 #define FSMC_BWTRx_ADDHLD_Msk (0xFUL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 3431 #define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 3432 #define FSMC_BWTRx_ADDHLD_0 (0x1UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */ 3433 #define FSMC_BWTRx_ADDHLD_1 (0x2UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */ 3434 #define FSMC_BWTRx_ADDHLD_2 (0x4UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */ 3435 #define FSMC_BWTRx_ADDHLD_3 (0x8UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */ 3436 3437 #define FSMC_BWTRx_DATAST_Pos (8U) 3438 #define FSMC_BWTRx_DATAST_Msk (0xFFUL << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */ 3439 #define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ 3440 #define FSMC_BWTRx_DATAST_0 (0x01UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */ 3441 #define FSMC_BWTRx_DATAST_1 (0x02UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */ 3442 #define FSMC_BWTRx_DATAST_2 (0x04UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */ 3443 #define FSMC_BWTRx_DATAST_3 (0x08UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */ 3444 #define FSMC_BWTRx_DATAST_4 (0x10UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */ 3445 #define FSMC_BWTRx_DATAST_5 (0x20UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */ 3446 #define FSMC_BWTRx_DATAST_6 (0x40UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */ 3447 #define FSMC_BWTRx_DATAST_7 (0x80UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */ 3448 3449 #define FSMC_BWTRx_BUSTURN_Pos (16U) 3450 #define FSMC_BWTRx_BUSTURN_Msk (0xFUL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */ 3451 #define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ 3452 #define FSMC_BWTRx_BUSTURN_0 (0x1UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */ 3453 #define FSMC_BWTRx_BUSTURN_1 (0x2UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */ 3454 #define FSMC_BWTRx_BUSTURN_2 (0x4UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */ 3455 #define FSMC_BWTRx_BUSTURN_3 (0x8UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */ 3456 3457 #define FSMC_BWTRx_ACCMOD_Pos (28U) 3458 #define FSMC_BWTRx_ACCMOD_Msk (0x3UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */ 3459 #define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 3460 #define FSMC_BWTRx_ACCMOD_0 (0x1UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */ 3461 #define FSMC_BWTRx_ACCMOD_1 (0x2UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */ 3462 3463 /******************************************************************************/ 3464 /* */ 3465 /* General Purpose I/O */ 3466 /* */ 3467 /******************************************************************************/ 3468 /****************** Bits definition for GPIO_MODER register *****************/ 3469 #define GPIO_MODER_MODER0_Pos (0U) 3470 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 3471 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 3472 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 3473 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 3474 3475 #define GPIO_MODER_MODER1_Pos (2U) 3476 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 3477 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 3478 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 3479 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 3480 3481 #define GPIO_MODER_MODER2_Pos (4U) 3482 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 3483 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 3484 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 3485 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 3486 3487 #define GPIO_MODER_MODER3_Pos (6U) 3488 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 3489 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 3490 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 3491 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 3492 3493 #define GPIO_MODER_MODER4_Pos (8U) 3494 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 3495 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 3496 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 3497 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 3498 3499 #define GPIO_MODER_MODER5_Pos (10U) 3500 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 3501 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 3502 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 3503 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 3504 3505 #define GPIO_MODER_MODER6_Pos (12U) 3506 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 3507 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 3508 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 3509 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 3510 3511 #define GPIO_MODER_MODER7_Pos (14U) 3512 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 3513 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 3514 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 3515 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 3516 3517 #define GPIO_MODER_MODER8_Pos (16U) 3518 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 3519 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 3520 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 3521 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 3522 3523 #define GPIO_MODER_MODER9_Pos (18U) 3524 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 3525 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 3526 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 3527 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 3528 3529 #define GPIO_MODER_MODER10_Pos (20U) 3530 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 3531 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 3532 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 3533 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 3534 3535 #define GPIO_MODER_MODER11_Pos (22U) 3536 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 3537 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 3538 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 3539 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 3540 3541 #define GPIO_MODER_MODER12_Pos (24U) 3542 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 3543 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 3544 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 3545 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 3546 3547 #define GPIO_MODER_MODER13_Pos (26U) 3548 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 3549 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 3550 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 3551 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 3552 3553 #define GPIO_MODER_MODER14_Pos (28U) 3554 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 3555 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 3556 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 3557 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 3558 3559 #define GPIO_MODER_MODER15_Pos (30U) 3560 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 3561 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 3562 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 3563 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 3564 3565 /****************** Bits definition for GPIO_OTYPER register ****************/ 3566 #define GPIO_OTYPER_OT_0 (0x00000001U) 3567 #define GPIO_OTYPER_OT_1 (0x00000002U) 3568 #define GPIO_OTYPER_OT_2 (0x00000004U) 3569 #define GPIO_OTYPER_OT_3 (0x00000008U) 3570 #define GPIO_OTYPER_OT_4 (0x00000010U) 3571 #define GPIO_OTYPER_OT_5 (0x00000020U) 3572 #define GPIO_OTYPER_OT_6 (0x00000040U) 3573 #define GPIO_OTYPER_OT_7 (0x00000080U) 3574 #define GPIO_OTYPER_OT_8 (0x00000100U) 3575 #define GPIO_OTYPER_OT_9 (0x00000200U) 3576 #define GPIO_OTYPER_OT_10 (0x00000400U) 3577 #define GPIO_OTYPER_OT_11 (0x00000800U) 3578 #define GPIO_OTYPER_OT_12 (0x00001000U) 3579 #define GPIO_OTYPER_OT_13 (0x00002000U) 3580 #define GPIO_OTYPER_OT_14 (0x00004000U) 3581 #define GPIO_OTYPER_OT_15 (0x00008000U) 3582 3583 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 3584 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 3585 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 3586 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 3587 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 3588 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 3589 3590 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 3591 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 3592 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 3593 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 3594 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 3595 3596 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 3597 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 3598 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 3599 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 3600 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 3601 3602 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 3603 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 3604 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 3605 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 3606 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 3607 3608 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 3609 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 3610 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 3611 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 3612 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 3613 3614 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 3615 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 3616 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 3617 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 3618 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 3619 3620 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 3621 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 3622 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 3623 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 3624 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 3625 3626 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 3627 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 3628 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 3629 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 3630 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 3631 3632 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 3633 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 3634 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 3635 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 3636 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 3637 3638 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 3639 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 3640 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 3641 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 3642 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 3643 3644 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 3645 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 3646 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 3647 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 3648 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 3649 3650 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 3651 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 3652 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 3653 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 3654 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 3655 3656 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 3657 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 3658 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 3659 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 3660 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 3661 3662 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 3663 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 3664 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 3665 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 3666 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 3667 3668 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 3669 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 3670 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 3671 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 3672 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 3673 3674 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 3675 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 3676 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 3677 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 3678 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 3679 3680 /****************** Bits definition for GPIO_PUPDR register *****************/ 3681 #define GPIO_PUPDR_PUPDR0_Pos (0U) 3682 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 3683 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 3684 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 3685 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 3686 3687 #define GPIO_PUPDR_PUPDR1_Pos (2U) 3688 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 3689 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 3690 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 3691 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 3692 3693 #define GPIO_PUPDR_PUPDR2_Pos (4U) 3694 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 3695 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 3696 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 3697 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 3698 3699 #define GPIO_PUPDR_PUPDR3_Pos (6U) 3700 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 3701 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 3702 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 3703 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 3704 3705 #define GPIO_PUPDR_PUPDR4_Pos (8U) 3706 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 3707 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 3708 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 3709 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 3710 3711 #define GPIO_PUPDR_PUPDR5_Pos (10U) 3712 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 3713 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 3714 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 3715 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 3716 3717 #define GPIO_PUPDR_PUPDR6_Pos (12U) 3718 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 3719 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 3720 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 3721 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 3722 3723 #define GPIO_PUPDR_PUPDR7_Pos (14U) 3724 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 3725 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 3726 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 3727 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 3728 3729 #define GPIO_PUPDR_PUPDR8_Pos (16U) 3730 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 3731 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 3732 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 3733 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 3734 3735 #define GPIO_PUPDR_PUPDR9_Pos (18U) 3736 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 3737 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 3738 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 3739 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 3740 3741 #define GPIO_PUPDR_PUPDR10_Pos (20U) 3742 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 3743 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 3744 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 3745 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 3746 3747 #define GPIO_PUPDR_PUPDR11_Pos (22U) 3748 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 3749 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 3750 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 3751 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 3752 3753 #define GPIO_PUPDR_PUPDR12_Pos (24U) 3754 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 3755 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 3756 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 3757 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 3758 3759 #define GPIO_PUPDR_PUPDR13_Pos (26U) 3760 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 3761 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 3762 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 3763 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 3764 3765 #define GPIO_PUPDR_PUPDR14_Pos (28U) 3766 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 3767 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 3768 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 3769 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 3770 #define GPIO_PUPDR_PUPDR15_Pos (30U) 3771 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 3772 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 3773 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 3774 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 3775 3776 /****************** Bits definition for GPIO_IDR register *******************/ 3777 #define GPIO_IDR_IDR_0 (0x00000001U) 3778 #define GPIO_IDR_IDR_1 (0x00000002U) 3779 #define GPIO_IDR_IDR_2 (0x00000004U) 3780 #define GPIO_IDR_IDR_3 (0x00000008U) 3781 #define GPIO_IDR_IDR_4 (0x00000010U) 3782 #define GPIO_IDR_IDR_5 (0x00000020U) 3783 #define GPIO_IDR_IDR_6 (0x00000040U) 3784 #define GPIO_IDR_IDR_7 (0x00000080U) 3785 #define GPIO_IDR_IDR_8 (0x00000100U) 3786 #define GPIO_IDR_IDR_9 (0x00000200U) 3787 #define GPIO_IDR_IDR_10 (0x00000400U) 3788 #define GPIO_IDR_IDR_11 (0x00000800U) 3789 #define GPIO_IDR_IDR_12 (0x00001000U) 3790 #define GPIO_IDR_IDR_13 (0x00002000U) 3791 #define GPIO_IDR_IDR_14 (0x00004000U) 3792 #define GPIO_IDR_IDR_15 (0x00008000U) 3793 3794 /****************** Bits definition for GPIO_ODR register *******************/ 3795 #define GPIO_ODR_ODR_0 (0x00000001U) 3796 #define GPIO_ODR_ODR_1 (0x00000002U) 3797 #define GPIO_ODR_ODR_2 (0x00000004U) 3798 #define GPIO_ODR_ODR_3 (0x00000008U) 3799 #define GPIO_ODR_ODR_4 (0x00000010U) 3800 #define GPIO_ODR_ODR_5 (0x00000020U) 3801 #define GPIO_ODR_ODR_6 (0x00000040U) 3802 #define GPIO_ODR_ODR_7 (0x00000080U) 3803 #define GPIO_ODR_ODR_8 (0x00000100U) 3804 #define GPIO_ODR_ODR_9 (0x00000200U) 3805 #define GPIO_ODR_ODR_10 (0x00000400U) 3806 #define GPIO_ODR_ODR_11 (0x00000800U) 3807 #define GPIO_ODR_ODR_12 (0x00001000U) 3808 #define GPIO_ODR_ODR_13 (0x00002000U) 3809 #define GPIO_ODR_ODR_14 (0x00004000U) 3810 #define GPIO_ODR_ODR_15 (0x00008000U) 3811 3812 /****************** Bits definition for GPIO_BSRR register ******************/ 3813 #define GPIO_BSRR_BS_0 (0x00000001U) 3814 #define GPIO_BSRR_BS_1 (0x00000002U) 3815 #define GPIO_BSRR_BS_2 (0x00000004U) 3816 #define GPIO_BSRR_BS_3 (0x00000008U) 3817 #define GPIO_BSRR_BS_4 (0x00000010U) 3818 #define GPIO_BSRR_BS_5 (0x00000020U) 3819 #define GPIO_BSRR_BS_6 (0x00000040U) 3820 #define GPIO_BSRR_BS_7 (0x00000080U) 3821 #define GPIO_BSRR_BS_8 (0x00000100U) 3822 #define GPIO_BSRR_BS_9 (0x00000200U) 3823 #define GPIO_BSRR_BS_10 (0x00000400U) 3824 #define GPIO_BSRR_BS_11 (0x00000800U) 3825 #define GPIO_BSRR_BS_12 (0x00001000U) 3826 #define GPIO_BSRR_BS_13 (0x00002000U) 3827 #define GPIO_BSRR_BS_14 (0x00004000U) 3828 #define GPIO_BSRR_BS_15 (0x00008000U) 3829 #define GPIO_BSRR_BR_0 (0x00010000U) 3830 #define GPIO_BSRR_BR_1 (0x00020000U) 3831 #define GPIO_BSRR_BR_2 (0x00040000U) 3832 #define GPIO_BSRR_BR_3 (0x00080000U) 3833 #define GPIO_BSRR_BR_4 (0x00100000U) 3834 #define GPIO_BSRR_BR_5 (0x00200000U) 3835 #define GPIO_BSRR_BR_6 (0x00400000U) 3836 #define GPIO_BSRR_BR_7 (0x00800000U) 3837 #define GPIO_BSRR_BR_8 (0x01000000U) 3838 #define GPIO_BSRR_BR_9 (0x02000000U) 3839 #define GPIO_BSRR_BR_10 (0x04000000U) 3840 #define GPIO_BSRR_BR_11 (0x08000000U) 3841 #define GPIO_BSRR_BR_12 (0x10000000U) 3842 #define GPIO_BSRR_BR_13 (0x20000000U) 3843 #define GPIO_BSRR_BR_14 (0x40000000U) 3844 #define GPIO_BSRR_BR_15 (0x80000000U) 3845 3846 /****************** Bit definition for GPIO_LCKR register ********************/ 3847 #define GPIO_LCKR_LCK0_Pos (0U) 3848 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 3849 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 3850 #define GPIO_LCKR_LCK1_Pos (1U) 3851 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 3852 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 3853 #define GPIO_LCKR_LCK2_Pos (2U) 3854 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 3855 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 3856 #define GPIO_LCKR_LCK3_Pos (3U) 3857 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 3858 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 3859 #define GPIO_LCKR_LCK4_Pos (4U) 3860 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3861 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3862 #define GPIO_LCKR_LCK5_Pos (5U) 3863 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3864 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3865 #define GPIO_LCKR_LCK6_Pos (6U) 3866 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3867 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3868 #define GPIO_LCKR_LCK7_Pos (7U) 3869 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3870 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3871 #define GPIO_LCKR_LCK8_Pos (8U) 3872 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3873 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3874 #define GPIO_LCKR_LCK9_Pos (9U) 3875 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3876 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3877 #define GPIO_LCKR_LCK10_Pos (10U) 3878 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3879 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3880 #define GPIO_LCKR_LCK11_Pos (11U) 3881 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3882 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3883 #define GPIO_LCKR_LCK12_Pos (12U) 3884 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3885 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3886 #define GPIO_LCKR_LCK13_Pos (13U) 3887 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3888 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3889 #define GPIO_LCKR_LCK14_Pos (14U) 3890 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3891 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3892 #define GPIO_LCKR_LCK15_Pos (15U) 3893 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3894 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3895 #define GPIO_LCKR_LCKK_Pos (16U) 3896 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3897 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3898 3899 /****************** Bit definition for GPIO_AFRL register ********************/ 3900 #define GPIO_AFRL_AFSEL0_Pos (0U) 3901 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3902 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3903 #define GPIO_AFRL_AFSEL1_Pos (4U) 3904 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3905 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3906 #define GPIO_AFRL_AFSEL2_Pos (8U) 3907 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3908 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3909 #define GPIO_AFRL_AFSEL3_Pos (12U) 3910 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3911 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3912 #define GPIO_AFRL_AFSEL4_Pos (16U) 3913 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3914 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3915 #define GPIO_AFRL_AFSEL5_Pos (20U) 3916 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3917 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3918 #define GPIO_AFRL_AFSEL6_Pos (24U) 3919 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3920 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3921 #define GPIO_AFRL_AFSEL7_Pos (28U) 3922 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3923 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3924 3925 /****************** Bit definition for GPIO_AFRH register ********************/ 3926 #define GPIO_AFRH_AFSEL8_Pos (0U) 3927 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3928 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3929 #define GPIO_AFRH_AFSEL9_Pos (4U) 3930 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3931 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3932 #define GPIO_AFRH_AFSEL10_Pos (8U) 3933 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3934 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3935 #define GPIO_AFRH_AFSEL11_Pos (12U) 3936 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3937 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3938 #define GPIO_AFRH_AFSEL12_Pos (16U) 3939 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3940 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3941 #define GPIO_AFRH_AFSEL13_Pos (20U) 3942 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3943 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3944 #define GPIO_AFRH_AFSEL14_Pos (24U) 3945 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3946 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3947 #define GPIO_AFRH_AFSEL15_Pos (28U) 3948 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3949 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3950 3951 /****************** Bit definition for GPIO_BRR register *********************/ 3952 #define GPIO_BRR_BR_0 (0x00000001U) 3953 #define GPIO_BRR_BR_1 (0x00000002U) 3954 #define GPIO_BRR_BR_2 (0x00000004U) 3955 #define GPIO_BRR_BR_3 (0x00000008U) 3956 #define GPIO_BRR_BR_4 (0x00000010U) 3957 #define GPIO_BRR_BR_5 (0x00000020U) 3958 #define GPIO_BRR_BR_6 (0x00000040U) 3959 #define GPIO_BRR_BR_7 (0x00000080U) 3960 #define GPIO_BRR_BR_8 (0x00000100U) 3961 #define GPIO_BRR_BR_9 (0x00000200U) 3962 #define GPIO_BRR_BR_10 (0x00000400U) 3963 #define GPIO_BRR_BR_11 (0x00000800U) 3964 #define GPIO_BRR_BR_12 (0x00001000U) 3965 #define GPIO_BRR_BR_13 (0x00002000U) 3966 #define GPIO_BRR_BR_14 (0x00004000U) 3967 #define GPIO_BRR_BR_15 (0x00008000U) 3968 3969 /******************************************************************************/ 3970 /* */ 3971 /* Inter-integrated Circuit Interface (I2C) */ 3972 /* */ 3973 /******************************************************************************/ 3974 3975 /******************* Bit definition for I2C_CR1 register ********************/ 3976 #define I2C_CR1_PE_Pos (0U) 3977 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3978 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 3979 #define I2C_CR1_SMBUS_Pos (1U) 3980 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 3981 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 3982 #define I2C_CR1_SMBTYPE_Pos (3U) 3983 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 3984 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 3985 #define I2C_CR1_ENARP_Pos (4U) 3986 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 3987 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 3988 #define I2C_CR1_ENPEC_Pos (5U) 3989 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 3990 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 3991 #define I2C_CR1_ENGC_Pos (6U) 3992 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 3993 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 3994 #define I2C_CR1_NOSTRETCH_Pos (7U) 3995 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 3996 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 3997 #define I2C_CR1_START_Pos (8U) 3998 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 3999 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 4000 #define I2C_CR1_STOP_Pos (9U) 4001 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 4002 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 4003 #define I2C_CR1_ACK_Pos (10U) 4004 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 4005 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 4006 #define I2C_CR1_POS_Pos (11U) 4007 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 4008 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 4009 #define I2C_CR1_PEC_Pos (12U) 4010 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 4011 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 4012 #define I2C_CR1_ALERT_Pos (13U) 4013 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 4014 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 4015 #define I2C_CR1_SWRST_Pos (15U) 4016 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 4017 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 4018 4019 /******************* Bit definition for I2C_CR2 register ********************/ 4020 #define I2C_CR2_FREQ_Pos (0U) 4021 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 4022 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 4023 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 4024 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 4025 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 4026 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 4027 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 4028 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 4029 4030 #define I2C_CR2_ITERREN_Pos (8U) 4031 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 4032 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 4033 #define I2C_CR2_ITEVTEN_Pos (9U) 4034 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 4035 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 4036 #define I2C_CR2_ITBUFEN_Pos (10U) 4037 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 4038 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 4039 #define I2C_CR2_DMAEN_Pos (11U) 4040 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 4041 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 4042 #define I2C_CR2_LAST_Pos (12U) 4043 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 4044 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 4045 4046 /******************* Bit definition for I2C_OAR1 register *******************/ 4047 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */ 4048 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */ 4049 4050 #define I2C_OAR1_ADD0_Pos (0U) 4051 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 4052 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 4053 #define I2C_OAR1_ADD1_Pos (1U) 4054 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 4055 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 4056 #define I2C_OAR1_ADD2_Pos (2U) 4057 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 4058 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 4059 #define I2C_OAR1_ADD3_Pos (3U) 4060 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 4061 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 4062 #define I2C_OAR1_ADD4_Pos (4U) 4063 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 4064 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 4065 #define I2C_OAR1_ADD5_Pos (5U) 4066 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 4067 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 4068 #define I2C_OAR1_ADD6_Pos (6U) 4069 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 4070 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 4071 #define I2C_OAR1_ADD7_Pos (7U) 4072 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 4073 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 4074 #define I2C_OAR1_ADD8_Pos (8U) 4075 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 4076 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 4077 #define I2C_OAR1_ADD9_Pos (9U) 4078 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 4079 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 4080 4081 #define I2C_OAR1_ADDMODE_Pos (15U) 4082 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 4083 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 4084 4085 /******************* Bit definition for I2C_OAR2 register *******************/ 4086 #define I2C_OAR2_ENDUAL_Pos (0U) 4087 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 4088 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 4089 #define I2C_OAR2_ADD2_Pos (1U) 4090 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 4091 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 4092 4093 /******************** Bit definition for I2C_DR register ********************/ 4094 #define I2C_DR_DR_Pos (0U) 4095 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 4096 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 4097 4098 /******************* Bit definition for I2C_SR1 register ********************/ 4099 #define I2C_SR1_SB_Pos (0U) 4100 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 4101 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 4102 #define I2C_SR1_ADDR_Pos (1U) 4103 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 4104 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 4105 #define I2C_SR1_BTF_Pos (2U) 4106 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 4107 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 4108 #define I2C_SR1_ADD10_Pos (3U) 4109 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 4110 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 4111 #define I2C_SR1_STOPF_Pos (4U) 4112 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 4113 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 4114 #define I2C_SR1_RXNE_Pos (6U) 4115 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 4116 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 4117 #define I2C_SR1_TXE_Pos (7U) 4118 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 4119 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 4120 #define I2C_SR1_BERR_Pos (8U) 4121 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 4122 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 4123 #define I2C_SR1_ARLO_Pos (9U) 4124 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 4125 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 4126 #define I2C_SR1_AF_Pos (10U) 4127 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 4128 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 4129 #define I2C_SR1_OVR_Pos (11U) 4130 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 4131 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 4132 #define I2C_SR1_PECERR_Pos (12U) 4133 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 4134 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 4135 #define I2C_SR1_TIMEOUT_Pos (14U) 4136 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 4137 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 4138 #define I2C_SR1_SMBALERT_Pos (15U) 4139 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 4140 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 4141 4142 /******************* Bit definition for I2C_SR2 register ********************/ 4143 #define I2C_SR2_MSL_Pos (0U) 4144 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 4145 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 4146 #define I2C_SR2_BUSY_Pos (1U) 4147 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 4148 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 4149 #define I2C_SR2_TRA_Pos (2U) 4150 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 4151 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 4152 #define I2C_SR2_GENCALL_Pos (4U) 4153 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 4154 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 4155 #define I2C_SR2_SMBDEFAULT_Pos (5U) 4156 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 4157 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 4158 #define I2C_SR2_SMBHOST_Pos (6U) 4159 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 4160 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 4161 #define I2C_SR2_DUALF_Pos (7U) 4162 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 4163 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 4164 #define I2C_SR2_PEC_Pos (8U) 4165 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 4166 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 4167 4168 /******************* Bit definition for I2C_CCR register ********************/ 4169 #define I2C_CCR_CCR_Pos (0U) 4170 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 4171 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 4172 #define I2C_CCR_DUTY_Pos (14U) 4173 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 4174 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 4175 #define I2C_CCR_FS_Pos (15U) 4176 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 4177 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 4178 4179 /****************** Bit definition for I2C_TRISE register *******************/ 4180 #define I2C_TRISE_TRISE_Pos (0U) 4181 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 4182 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 4183 4184 /******************************************************************************/ 4185 /* */ 4186 /* Independent WATCHDOG (IWDG) */ 4187 /* */ 4188 /******************************************************************************/ 4189 4190 /******************* Bit definition for IWDG_KR register ********************/ 4191 #define IWDG_KR_KEY_Pos (0U) 4192 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 4193 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 4194 4195 /******************* Bit definition for IWDG_PR register ********************/ 4196 #define IWDG_PR_PR_Pos (0U) 4197 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 4198 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 4199 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 4200 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 4201 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 4202 4203 /******************* Bit definition for IWDG_RLR register *******************/ 4204 #define IWDG_RLR_RL_Pos (0U) 4205 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 4206 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 4207 4208 /******************* Bit definition for IWDG_SR register ********************/ 4209 #define IWDG_SR_PVU_Pos (0U) 4210 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 4211 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 4212 #define IWDG_SR_RVU_Pos (1U) 4213 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 4214 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 4215 4216 /******************************************************************************/ 4217 /* */ 4218 /* Power Control (PWR) */ 4219 /* */ 4220 /******************************************************************************/ 4221 4222 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 4223 4224 /******************** Bit definition for PWR_CR register ********************/ 4225 #define PWR_CR_LPSDSR_Pos (0U) 4226 #define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 4227 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 4228 #define PWR_CR_PDDS_Pos (1U) 4229 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 4230 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 4231 #define PWR_CR_CWUF_Pos (2U) 4232 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 4233 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 4234 #define PWR_CR_CSBF_Pos (3U) 4235 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 4236 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 4237 #define PWR_CR_PVDE_Pos (4U) 4238 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 4239 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 4240 4241 #define PWR_CR_PLS_Pos (5U) 4242 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 4243 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 4244 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 4245 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 4246 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 4247 4248 /*!< PVD level configuration */ 4249 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 4250 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 4251 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 4252 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 4253 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 4254 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 4255 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 4256 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 4257 4258 #define PWR_CR_DBP_Pos (8U) 4259 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 4260 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 4261 #define PWR_CR_ULP_Pos (9U) 4262 #define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 4263 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 4264 #define PWR_CR_FWU_Pos (10U) 4265 #define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 4266 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 4267 4268 #define PWR_CR_VOS_Pos (11U) 4269 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 4270 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 4271 #define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 4272 #define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 4273 #define PWR_CR_LPRUN_Pos (14U) 4274 #define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 4275 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 4276 4277 /******************* Bit definition for PWR_CSR register ********************/ 4278 #define PWR_CSR_WUF_Pos (0U) 4279 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 4280 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 4281 #define PWR_CSR_SBF_Pos (1U) 4282 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 4283 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 4284 #define PWR_CSR_PVDO_Pos (2U) 4285 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 4286 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 4287 #define PWR_CSR_VREFINTRDYF_Pos (3U) 4288 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 4289 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 4290 #define PWR_CSR_VOSF_Pos (4U) 4291 #define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 4292 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 4293 #define PWR_CSR_REGLPF_Pos (5U) 4294 #define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 4295 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 4296 4297 #define PWR_CSR_EWUP1_Pos (8U) 4298 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 4299 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 4300 #define PWR_CSR_EWUP2_Pos (9U) 4301 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 4302 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 4303 #define PWR_CSR_EWUP3_Pos (10U) 4304 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 4305 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 4306 4307 /******************************************************************************/ 4308 /* */ 4309 /* Reset and Clock Control (RCC) */ 4310 /* */ 4311 /******************************************************************************/ 4312 /* 4313 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 4314 */ 4315 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */ 4316 4317 /******************** Bit definition for RCC_CR register ********************/ 4318 #define RCC_CR_HSION_Pos (0U) 4319 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 4320 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 4321 #define RCC_CR_HSIRDY_Pos (1U) 4322 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 4323 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 4324 4325 #define RCC_CR_MSION_Pos (8U) 4326 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 4327 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 4328 #define RCC_CR_MSIRDY_Pos (9U) 4329 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 4330 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 4331 4332 #define RCC_CR_HSEON_Pos (16U) 4333 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 4334 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 4335 #define RCC_CR_HSERDY_Pos (17U) 4336 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 4337 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 4338 #define RCC_CR_HSEBYP_Pos (18U) 4339 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 4340 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 4341 4342 #define RCC_CR_PLLON_Pos (24U) 4343 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 4344 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 4345 #define RCC_CR_PLLRDY_Pos (25U) 4346 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 4347 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 4348 #define RCC_CR_CSSON_Pos (28U) 4349 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x10000000 */ 4350 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 4351 4352 #define RCC_CR_RTCPRE_Pos (29U) 4353 #define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */ 4354 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC Prescaler */ 4355 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */ 4356 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */ 4357 4358 /******************** Bit definition for RCC_ICSCR register *****************/ 4359 #define RCC_ICSCR_HSICAL_Pos (0U) 4360 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 4361 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 4362 #define RCC_ICSCR_HSITRIM_Pos (8U) 4363 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 4364 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 4365 4366 #define RCC_ICSCR_MSIRANGE_Pos (13U) 4367 #define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 4368 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 4369 #define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 4370 #define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 4371 #define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 4372 #define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 4373 #define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 4374 #define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 4375 #define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 4376 #define RCC_ICSCR_MSICAL_Pos (16U) 4377 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 4378 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 4379 #define RCC_ICSCR_MSITRIM_Pos (24U) 4380 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 4381 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 4382 4383 /******************** Bit definition for RCC_CFGR register ******************/ 4384 #define RCC_CFGR_SW_Pos (0U) 4385 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 4386 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 4387 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4388 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4389 4390 /*!< SW configuration */ 4391 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 4392 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 4393 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 4394 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 4395 4396 #define RCC_CFGR_SWS_Pos (2U) 4397 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 4398 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 4399 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 4400 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4401 4402 /*!< SWS configuration */ 4403 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 4404 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 4405 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 4406 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 4407 4408 #define RCC_CFGR_HPRE_Pos (4U) 4409 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 4410 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4411 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 4412 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 4413 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 4414 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 4415 4416 /*!< HPRE configuration */ 4417 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 4418 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 4419 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 4420 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 4421 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 4422 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 4423 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 4424 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 4425 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 4426 4427 #define RCC_CFGR_PPRE1_Pos (8U) 4428 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 4429 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 4430 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 4431 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 4432 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 4433 4434 /*!< PPRE1 configuration */ 4435 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 4436 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 4437 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 4438 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 4439 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 4440 4441 #define RCC_CFGR_PPRE2_Pos (11U) 4442 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 4443 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 4444 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 4445 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 4446 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 4447 4448 /*!< PPRE2 configuration */ 4449 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 4450 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 4451 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 4452 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 4453 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 4454 4455 /*!< PLL entry clock source*/ 4456 #define RCC_CFGR_PLLSRC_Pos (16U) 4457 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 4458 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 4459 4460 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 4461 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 4462 4463 4464 /*!< PLLMUL configuration */ 4465 #define RCC_CFGR_PLLMUL_Pos (18U) 4466 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 4467 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4468 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 4469 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 4470 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 4471 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 4472 4473 /*!< PLLMUL configuration */ 4474 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 4475 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 4476 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 4477 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 4478 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 4479 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 4480 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 4481 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 4482 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 4483 4484 /*!< PLLDIV configuration */ 4485 #define RCC_CFGR_PLLDIV_Pos (22U) 4486 #define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 4487 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 4488 #define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 4489 #define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 4490 4491 4492 /*!< PLLDIV configuration */ 4493 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */ 4494 #define RCC_CFGR_PLLDIV2_Pos (22U) 4495 #define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 4496 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 4497 #define RCC_CFGR_PLLDIV3_Pos (23U) 4498 #define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 4499 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 4500 #define RCC_CFGR_PLLDIV4_Pos (22U) 4501 #define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 4502 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 4503 4504 4505 #define RCC_CFGR_MCOSEL_Pos (24U) 4506 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4507 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4508 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4509 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4510 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4511 4512 /*!< MCO configuration */ 4513 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4514 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 4515 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 4516 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */ 4517 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 4518 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 4519 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 4520 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 4521 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 4522 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 4523 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 4524 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 4525 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 4526 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 4527 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 4528 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 4529 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 4530 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 4531 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 4532 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 4533 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 4534 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 4535 4536 #define RCC_CFGR_MCOPRE_Pos (28U) 4537 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4538 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */ 4539 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4540 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4541 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4542 4543 /*!< MCO Prescaler configuration */ 4544 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 4545 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 4546 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 4547 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 4548 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 4549 4550 /* Legacy aliases */ 4551 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1 4552 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2 4553 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4 4554 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8 4555 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16 4556 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 4557 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 4558 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 4559 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 4560 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 4561 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 4562 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 4563 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 4564 4565 /*!<****************** Bit definition for RCC_CIR register ********************/ 4566 #define RCC_CIR_LSIRDYF_Pos (0U) 4567 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 4568 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 4569 #define RCC_CIR_LSERDYF_Pos (1U) 4570 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 4571 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 4572 #define RCC_CIR_HSIRDYF_Pos (2U) 4573 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 4574 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 4575 #define RCC_CIR_HSERDYF_Pos (3U) 4576 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 4577 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 4578 #define RCC_CIR_PLLRDYF_Pos (4U) 4579 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 4580 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 4581 #define RCC_CIR_MSIRDYF_Pos (5U) 4582 #define RCC_CIR_MSIRDYF_Msk (0x1UL << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */ 4583 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 4584 #define RCC_CIR_LSECSSF_Pos (6U) 4585 #define RCC_CIR_LSECSSF_Msk (0x1UL << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */ 4586 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */ 4587 #define RCC_CIR_CSSF_Pos (7U) 4588 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 4589 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 4590 4591 #define RCC_CIR_LSIRDYIE_Pos (8U) 4592 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 4593 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 4594 #define RCC_CIR_LSERDYIE_Pos (9U) 4595 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 4596 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 4597 #define RCC_CIR_HSIRDYIE_Pos (10U) 4598 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 4599 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 4600 #define RCC_CIR_HSERDYIE_Pos (11U) 4601 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 4602 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 4603 #define RCC_CIR_PLLRDYIE_Pos (12U) 4604 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 4605 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 4606 #define RCC_CIR_MSIRDYIE_Pos (13U) 4607 #define RCC_CIR_MSIRDYIE_Msk (0x1UL << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */ 4608 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 4609 #define RCC_CIR_LSECSSIE_Pos (14U) 4610 #define RCC_CIR_LSECSSIE_Msk (0x1UL << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */ 4611 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */ 4612 4613 #define RCC_CIR_LSIRDYC_Pos (16U) 4614 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 4615 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 4616 #define RCC_CIR_LSERDYC_Pos (17U) 4617 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 4618 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 4619 #define RCC_CIR_HSIRDYC_Pos (18U) 4620 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 4621 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 4622 #define RCC_CIR_HSERDYC_Pos (19U) 4623 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 4624 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 4625 #define RCC_CIR_PLLRDYC_Pos (20U) 4626 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 4627 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 4628 #define RCC_CIR_MSIRDYC_Pos (21U) 4629 #define RCC_CIR_MSIRDYC_Msk (0x1UL << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */ 4630 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 4631 #define RCC_CIR_LSECSSC_Pos (22U) 4632 #define RCC_CIR_LSECSSC_Msk (0x1UL << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */ 4633 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */ 4634 #define RCC_CIR_CSSC_Pos (23U) 4635 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 4636 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 4637 4638 /***************** Bit definition for RCC_AHBRSTR register ******************/ 4639 #define RCC_AHBRSTR_GPIOARST_Pos (0U) 4640 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4641 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */ 4642 #define RCC_AHBRSTR_GPIOBRST_Pos (1U) 4643 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4644 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */ 4645 #define RCC_AHBRSTR_GPIOCRST_Pos (2U) 4646 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4647 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */ 4648 #define RCC_AHBRSTR_GPIODRST_Pos (3U) 4649 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4650 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */ 4651 #define RCC_AHBRSTR_GPIOERST_Pos (4U) 4652 #define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */ 4653 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */ 4654 #define RCC_AHBRSTR_GPIOHRST_Pos (5U) 4655 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */ 4656 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */ 4657 #define RCC_AHBRSTR_GPIOFRST_Pos (6U) 4658 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */ 4659 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */ 4660 #define RCC_AHBRSTR_GPIOGRST_Pos (7U) 4661 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */ 4662 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */ 4663 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4664 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4665 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 4666 #define RCC_AHBRSTR_FLITFRST_Pos (15U) 4667 #define RCC_AHBRSTR_FLITFRST_Msk (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */ 4668 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */ 4669 #define RCC_AHBRSTR_DMA1RST_Pos (24U) 4670 #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */ 4671 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */ 4672 #define RCC_AHBRSTR_DMA2RST_Pos (25U) 4673 #define RCC_AHBRSTR_DMA2RST_Msk (0x1UL << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */ 4674 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */ 4675 #define RCC_AHBRSTR_FSMCRST_Pos (30U) 4676 #define RCC_AHBRSTR_FSMCRST_Msk (0x1UL << RCC_AHBRSTR_FSMCRST_Pos) /*!< 0x40000000 */ 4677 #define RCC_AHBRSTR_FSMCRST RCC_AHBRSTR_FSMCRST_Msk /*!< FSMC reset */ 4678 4679 /***************** Bit definition for RCC_APB2RSTR register *****************/ 4680 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 4681 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 4682 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */ 4683 #define RCC_APB2RSTR_TIM9RST_Pos (2U) 4684 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */ 4685 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ 4686 #define RCC_APB2RSTR_TIM10RST_Pos (3U) 4687 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */ 4688 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */ 4689 #define RCC_APB2RSTR_TIM11RST_Pos (4U) 4690 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */ 4691 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */ 4692 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 4693 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 4694 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */ 4695 #define RCC_APB2RSTR_SDIORST_Pos (11U) 4696 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ 4697 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk /*!< SDIO reset */ 4698 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 4699 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 4700 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 4701 #define RCC_APB2RSTR_USART1RST_Pos (14U) 4702 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 4703 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 4704 4705 /***************** Bit definition for RCC_APB1RSTR register *****************/ 4706 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 4707 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 4708 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 4709 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 4710 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 4711 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 4712 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 4713 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 4714 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 4715 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 4716 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ 4717 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ 4718 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 4719 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 4720 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 4721 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 4722 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 4723 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 4724 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 4725 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 4726 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 4727 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 4728 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 4729 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 4730 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 4731 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 4732 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ 4733 #define RCC_APB1RSTR_USART2RST_Pos (17U) 4734 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 4735 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 4736 #define RCC_APB1RSTR_USART3RST_Pos (18U) 4737 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 4738 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 4739 #define RCC_APB1RSTR_UART4RST_Pos (19U) 4740 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ 4741 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ 4742 #define RCC_APB1RSTR_UART5RST_Pos (20U) 4743 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ 4744 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ 4745 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 4746 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 4747 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 4748 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 4749 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 4750 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 4751 #define RCC_APB1RSTR_USBRST_Pos (23U) 4752 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 4753 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ 4754 #define RCC_APB1RSTR_PWRRST_Pos (28U) 4755 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 4756 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 4757 #define RCC_APB1RSTR_DACRST_Pos (29U) 4758 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 4759 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 4760 #define RCC_APB1RSTR_COMPRST_Pos (31U) 4761 #define RCC_APB1RSTR_COMPRST_Msk (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */ 4762 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */ 4763 4764 /****************** Bit definition for RCC_AHBENR register ******************/ 4765 #define RCC_AHBENR_GPIOAEN_Pos (0U) 4766 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4767 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */ 4768 #define RCC_AHBENR_GPIOBEN_Pos (1U) 4769 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4770 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */ 4771 #define RCC_AHBENR_GPIOCEN_Pos (2U) 4772 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4773 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */ 4774 #define RCC_AHBENR_GPIODEN_Pos (3U) 4775 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */ 4776 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */ 4777 #define RCC_AHBENR_GPIOEEN_Pos (4U) 4778 #define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */ 4779 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */ 4780 #define RCC_AHBENR_GPIOHEN_Pos (5U) 4781 #define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */ 4782 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */ 4783 #define RCC_AHBENR_GPIOFEN_Pos (6U) 4784 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */ 4785 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */ 4786 #define RCC_AHBENR_GPIOGEN_Pos (7U) 4787 #define RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */ 4788 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */ 4789 #define RCC_AHBENR_CRCEN_Pos (12U) 4790 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4791 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 4792 #define RCC_AHBENR_FLITFEN_Pos (15U) 4793 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */ 4794 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when 4795 the Flash memory is in power down mode) */ 4796 #define RCC_AHBENR_DMA1EN_Pos (24U) 4797 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */ 4798 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 4799 #define RCC_AHBENR_DMA2EN_Pos (25U) 4800 #define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */ 4801 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ 4802 #define RCC_AHBENR_FSMCEN_Pos (30U) 4803 #define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /*!< 0x40000000 */ 4804 #define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */ 4805 4806 /****************** Bit definition for RCC_APB2ENR register *****************/ 4807 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 4808 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 4809 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */ 4810 #define RCC_APB2ENR_TIM9EN_Pos (2U) 4811 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */ 4812 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */ 4813 #define RCC_APB2ENR_TIM10EN_Pos (3U) 4814 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */ 4815 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */ 4816 #define RCC_APB2ENR_TIM11EN_Pos (4U) 4817 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */ 4818 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */ 4819 #define RCC_APB2ENR_ADC1EN_Pos (9U) 4820 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 4821 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */ 4822 #define RCC_APB2ENR_SDIOEN_Pos (11U) 4823 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ 4824 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk /*!< SDIO clock enable */ 4825 #define RCC_APB2ENR_SPI1EN_Pos (12U) 4826 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 4827 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 4828 #define RCC_APB2ENR_USART1EN_Pos (14U) 4829 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 4830 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 4831 4832 /***************** Bit definition for RCC_APB1ENR register ******************/ 4833 #define RCC_APB1ENR_TIM2EN_Pos (0U) 4834 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 4835 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 4836 #define RCC_APB1ENR_TIM3EN_Pos (1U) 4837 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 4838 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 4839 #define RCC_APB1ENR_TIM4EN_Pos (2U) 4840 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 4841 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 4842 #define RCC_APB1ENR_TIM5EN_Pos (3U) 4843 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ 4844 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ 4845 #define RCC_APB1ENR_TIM6EN_Pos (4U) 4846 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 4847 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 4848 #define RCC_APB1ENR_TIM7EN_Pos (5U) 4849 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 4850 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 4851 #define RCC_APB1ENR_WWDGEN_Pos (11U) 4852 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 4853 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 4854 #define RCC_APB1ENR_SPI2EN_Pos (14U) 4855 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 4856 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 4857 #define RCC_APB1ENR_SPI3EN_Pos (15U) 4858 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 4859 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ 4860 #define RCC_APB1ENR_USART2EN_Pos (17U) 4861 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 4862 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 4863 #define RCC_APB1ENR_USART3EN_Pos (18U) 4864 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 4865 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 4866 #define RCC_APB1ENR_UART4EN_Pos (19U) 4867 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ 4868 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ 4869 #define RCC_APB1ENR_UART5EN_Pos (20U) 4870 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ 4871 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ 4872 #define RCC_APB1ENR_I2C1EN_Pos (21U) 4873 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 4874 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 4875 #define RCC_APB1ENR_I2C2EN_Pos (22U) 4876 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 4877 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 4878 #define RCC_APB1ENR_USBEN_Pos (23U) 4879 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 4880 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ 4881 #define RCC_APB1ENR_PWREN_Pos (28U) 4882 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 4883 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 4884 #define RCC_APB1ENR_DACEN_Pos (29U) 4885 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 4886 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 4887 #define RCC_APB1ENR_COMPEN_Pos (31U) 4888 #define RCC_APB1ENR_COMPEN_Msk (0x1UL << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */ 4889 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */ 4890 4891 /****************** Bit definition for RCC_AHBLPENR register ****************/ 4892 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U) 4893 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ 4894 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 4895 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) 4896 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ 4897 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 4898 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) 4899 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ 4900 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 4901 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U) 4902 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ 4903 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 4904 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U) 4905 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ 4906 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 4907 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) 4908 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */ 4909 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 4910 #define RCC_AHBLPENR_GPIOFLPEN_Pos (6U) 4911 #define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */ 4912 #define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */ 4913 #define RCC_AHBLPENR_GPIOGLPEN_Pos (7U) 4914 #define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */ 4915 #define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */ 4916 #define RCC_AHBLPENR_CRCLPEN_Pos (12U) 4917 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */ 4918 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */ 4919 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U) 4920 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ 4921 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode 4922 (has effect only when the Flash memory is 4923 in power down mode) */ 4924 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U) 4925 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */ 4926 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */ 4927 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U) 4928 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */ 4929 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */ 4930 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U) 4931 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */ 4932 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */ 4933 #define RCC_AHBLPENR_FSMCLPEN_Pos (30U) 4934 #define RCC_AHBLPENR_FSMCLPEN_Msk (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */ 4935 #define RCC_AHBLPENR_FSMCLPEN RCC_AHBLPENR_FSMCLPEN_Msk /*!< FSMC clock enabled in sleep mode */ 4936 4937 /****************** Bit definition for RCC_APB2LPENR register ***************/ 4938 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) 4939 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */ 4940 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */ 4941 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U) 4942 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */ 4943 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */ 4944 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U) 4945 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */ 4946 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */ 4947 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U) 4948 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */ 4949 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */ 4950 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U) 4951 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */ 4952 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */ 4953 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) 4954 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ 4955 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk /*!< SDIO clock enabled in sleep mode */ 4956 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 4957 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ 4958 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */ 4959 #define RCC_APB2LPENR_USART1LPEN_Pos (14U) 4960 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ 4961 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */ 4962 4963 /***************** Bit definition for RCC_APB1LPENR register ****************/ 4964 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 4965 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ 4966 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 4967 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 4968 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ 4969 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 4970 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 4971 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ 4972 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */ 4973 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) 4974 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ 4975 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */ 4976 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 4977 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ 4978 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 4979 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 4980 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ 4981 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 4982 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 4983 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ 4984 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 4985 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 4986 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ 4987 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */ 4988 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) 4989 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ 4990 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */ 4991 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 4992 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ 4993 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */ 4994 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 4995 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ 4996 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */ 4997 #define RCC_APB1LPENR_UART4LPEN_Pos (19U) 4998 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ 4999 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */ 5000 #define RCC_APB1LPENR_UART5LPEN_Pos (20U) 5001 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ 5002 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */ 5003 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 5004 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ 5005 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */ 5006 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 5007 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ 5008 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */ 5009 #define RCC_APB1LPENR_USBLPEN_Pos (23U) 5010 #define RCC_APB1LPENR_USBLPEN_Msk (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */ 5011 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */ 5012 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 5013 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ 5014 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */ 5015 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 5016 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ 5017 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */ 5018 #define RCC_APB1LPENR_COMPLPEN_Pos (31U) 5019 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */ 5020 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/ 5021 5022 /******************* Bit definition for RCC_CSR register ********************/ 5023 #define RCC_CSR_LSION_Pos (0U) 5024 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 5025 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 5026 #define RCC_CSR_LSIRDY_Pos (1U) 5027 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 5028 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 5029 5030 #define RCC_CSR_LSEON_Pos (8U) 5031 #define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 5032 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 5033 #define RCC_CSR_LSERDY_Pos (9U) 5034 #define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 5035 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 5036 #define RCC_CSR_LSEBYP_Pos (10U) 5037 #define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 5038 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 5039 5040 #define RCC_CSR_LSECSSON_Pos (11U) 5041 #define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */ 5042 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 5043 #define RCC_CSR_LSECSSD_Pos (12U) 5044 #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */ 5045 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 5046 5047 #define RCC_CSR_RTCSEL_Pos (16U) 5048 #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 5049 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 5050 #define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 5051 #define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 5052 5053 /*!< RTC configuration */ 5054 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 5055 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 5056 #define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 5057 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 5058 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 5059 #define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 5060 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 5061 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 5062 #define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 5063 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */ 5064 5065 #define RCC_CSR_RTCEN_Pos (22U) 5066 #define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */ 5067 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 5068 #define RCC_CSR_RTCRST_Pos (23U) 5069 #define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */ 5070 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */ 5071 5072 #define RCC_CSR_RMVF_Pos (24U) 5073 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 5074 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 5075 #define RCC_CSR_OBLRSTF_Pos (25U) 5076 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 5077 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */ 5078 #define RCC_CSR_PINRSTF_Pos (26U) 5079 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 5080 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 5081 #define RCC_CSR_PORRSTF_Pos (27U) 5082 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 5083 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 5084 #define RCC_CSR_SFTRSTF_Pos (28U) 5085 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 5086 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 5087 #define RCC_CSR_IWDGRSTF_Pos (29U) 5088 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 5089 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 5090 #define RCC_CSR_WWDGRSTF_Pos (30U) 5091 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 5092 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 5093 #define RCC_CSR_LPWRRSTF_Pos (31U) 5094 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 5095 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 5096 5097 /******************************************************************************/ 5098 /* */ 5099 /* Real-Time Clock (RTC) */ 5100 /* */ 5101 /******************************************************************************/ 5102 /* 5103 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 5104 */ 5105 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 5106 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 5107 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */ 5108 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 5109 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 5110 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */ 5111 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */ 5112 5113 /******************** Bits definition for RTC_TR register *******************/ 5114 #define RTC_TR_PM_Pos (22U) 5115 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 5116 #define RTC_TR_PM RTC_TR_PM_Msk 5117 #define RTC_TR_HT_Pos (20U) 5118 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 5119 #define RTC_TR_HT RTC_TR_HT_Msk 5120 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 5121 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 5122 #define RTC_TR_HU_Pos (16U) 5123 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 5124 #define RTC_TR_HU RTC_TR_HU_Msk 5125 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 5126 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 5127 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 5128 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 5129 #define RTC_TR_MNT_Pos (12U) 5130 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 5131 #define RTC_TR_MNT RTC_TR_MNT_Msk 5132 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 5133 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 5134 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 5135 #define RTC_TR_MNU_Pos (8U) 5136 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 5137 #define RTC_TR_MNU RTC_TR_MNU_Msk 5138 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 5139 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 5140 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 5141 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 5142 #define RTC_TR_ST_Pos (4U) 5143 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 5144 #define RTC_TR_ST RTC_TR_ST_Msk 5145 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 5146 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 5147 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 5148 #define RTC_TR_SU_Pos (0U) 5149 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 5150 #define RTC_TR_SU RTC_TR_SU_Msk 5151 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 5152 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 5153 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 5154 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 5155 5156 /******************** Bits definition for RTC_DR register *******************/ 5157 #define RTC_DR_YT_Pos (20U) 5158 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 5159 #define RTC_DR_YT RTC_DR_YT_Msk 5160 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 5161 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 5162 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 5163 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 5164 #define RTC_DR_YU_Pos (16U) 5165 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 5166 #define RTC_DR_YU RTC_DR_YU_Msk 5167 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 5168 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 5169 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 5170 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 5171 #define RTC_DR_WDU_Pos (13U) 5172 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 5173 #define RTC_DR_WDU RTC_DR_WDU_Msk 5174 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 5175 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 5176 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 5177 #define RTC_DR_MT_Pos (12U) 5178 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 5179 #define RTC_DR_MT RTC_DR_MT_Msk 5180 #define RTC_DR_MU_Pos (8U) 5181 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 5182 #define RTC_DR_MU RTC_DR_MU_Msk 5183 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 5184 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 5185 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 5186 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 5187 #define RTC_DR_DT_Pos (4U) 5188 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 5189 #define RTC_DR_DT RTC_DR_DT_Msk 5190 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 5191 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 5192 #define RTC_DR_DU_Pos (0U) 5193 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 5194 #define RTC_DR_DU RTC_DR_DU_Msk 5195 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 5196 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 5197 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 5198 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 5199 5200 /******************** Bits definition for RTC_CR register *******************/ 5201 #define RTC_CR_COE_Pos (23U) 5202 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 5203 #define RTC_CR_COE RTC_CR_COE_Msk 5204 #define RTC_CR_OSEL_Pos (21U) 5205 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 5206 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 5207 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 5208 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 5209 #define RTC_CR_POL_Pos (20U) 5210 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 5211 #define RTC_CR_POL RTC_CR_POL_Msk 5212 #define RTC_CR_COSEL_Pos (19U) 5213 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 5214 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 5215 #define RTC_CR_BKP_Pos (18U) 5216 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 5217 #define RTC_CR_BKP RTC_CR_BKP_Msk 5218 #define RTC_CR_SUB1H_Pos (17U) 5219 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 5220 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 5221 #define RTC_CR_ADD1H_Pos (16U) 5222 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 5223 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 5224 #define RTC_CR_TSIE_Pos (15U) 5225 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 5226 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 5227 #define RTC_CR_WUTIE_Pos (14U) 5228 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 5229 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 5230 #define RTC_CR_ALRBIE_Pos (13U) 5231 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 5232 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 5233 #define RTC_CR_ALRAIE_Pos (12U) 5234 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 5235 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 5236 #define RTC_CR_TSE_Pos (11U) 5237 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 5238 #define RTC_CR_TSE RTC_CR_TSE_Msk 5239 #define RTC_CR_WUTE_Pos (10U) 5240 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 5241 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 5242 #define RTC_CR_ALRBE_Pos (9U) 5243 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 5244 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 5245 #define RTC_CR_ALRAE_Pos (8U) 5246 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 5247 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 5248 #define RTC_CR_DCE_Pos (7U) 5249 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */ 5250 #define RTC_CR_DCE RTC_CR_DCE_Msk 5251 #define RTC_CR_FMT_Pos (6U) 5252 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 5253 #define RTC_CR_FMT RTC_CR_FMT_Msk 5254 #define RTC_CR_BYPSHAD_Pos (5U) 5255 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 5256 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 5257 #define RTC_CR_REFCKON_Pos (4U) 5258 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 5259 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 5260 #define RTC_CR_TSEDGE_Pos (3U) 5261 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 5262 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 5263 #define RTC_CR_WUCKSEL_Pos (0U) 5264 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 5265 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 5266 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 5267 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 5268 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 5269 5270 /* Legacy defines */ 5271 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 5272 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 5273 #define RTC_CR_BCK RTC_CR_BKP 5274 5275 /******************** Bits definition for RTC_ISR register ******************/ 5276 #define RTC_ISR_RECALPF_Pos (16U) 5277 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 5278 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 5279 #define RTC_ISR_TAMP3F_Pos (15U) 5280 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 5281 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk 5282 #define RTC_ISR_TAMP2F_Pos (14U) 5283 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 5284 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 5285 #define RTC_ISR_TAMP1F_Pos (13U) 5286 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 5287 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 5288 #define RTC_ISR_TSOVF_Pos (12U) 5289 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 5290 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 5291 #define RTC_ISR_TSF_Pos (11U) 5292 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 5293 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 5294 #define RTC_ISR_WUTF_Pos (10U) 5295 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 5296 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 5297 #define RTC_ISR_ALRBF_Pos (9U) 5298 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 5299 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 5300 #define RTC_ISR_ALRAF_Pos (8U) 5301 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 5302 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 5303 #define RTC_ISR_INIT_Pos (7U) 5304 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 5305 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 5306 #define RTC_ISR_INITF_Pos (6U) 5307 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 5308 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 5309 #define RTC_ISR_RSF_Pos (5U) 5310 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 5311 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 5312 #define RTC_ISR_INITS_Pos (4U) 5313 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 5314 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 5315 #define RTC_ISR_SHPF_Pos (3U) 5316 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 5317 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 5318 #define RTC_ISR_WUTWF_Pos (2U) 5319 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 5320 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 5321 #define RTC_ISR_ALRBWF_Pos (1U) 5322 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 5323 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 5324 #define RTC_ISR_ALRAWF_Pos (0U) 5325 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 5326 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 5327 5328 /******************** Bits definition for RTC_PRER register *****************/ 5329 #define RTC_PRER_PREDIV_A_Pos (16U) 5330 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 5331 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 5332 #define RTC_PRER_PREDIV_S_Pos (0U) 5333 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 5334 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 5335 5336 /******************** Bits definition for RTC_WUTR register *****************/ 5337 #define RTC_WUTR_WUT_Pos (0U) 5338 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 5339 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 5340 5341 /******************** Bits definition for RTC_CALIBR register ***************/ 5342 #define RTC_CALIBR_DCS_Pos (7U) 5343 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ 5344 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk 5345 #define RTC_CALIBR_DC_Pos (0U) 5346 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ 5347 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk 5348 5349 /******************** Bits definition for RTC_ALRMAR register ***************/ 5350 #define RTC_ALRMAR_MSK4_Pos (31U) 5351 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 5352 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 5353 #define RTC_ALRMAR_WDSEL_Pos (30U) 5354 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 5355 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 5356 #define RTC_ALRMAR_DT_Pos (28U) 5357 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 5358 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 5359 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 5360 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 5361 #define RTC_ALRMAR_DU_Pos (24U) 5362 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 5363 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 5364 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 5365 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 5366 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 5367 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 5368 #define RTC_ALRMAR_MSK3_Pos (23U) 5369 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 5370 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 5371 #define RTC_ALRMAR_PM_Pos (22U) 5372 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 5373 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 5374 #define RTC_ALRMAR_HT_Pos (20U) 5375 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 5376 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 5377 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 5378 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 5379 #define RTC_ALRMAR_HU_Pos (16U) 5380 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 5381 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 5382 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 5383 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 5384 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 5385 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 5386 #define RTC_ALRMAR_MSK2_Pos (15U) 5387 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 5388 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 5389 #define RTC_ALRMAR_MNT_Pos (12U) 5390 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 5391 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 5392 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 5393 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 5394 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 5395 #define RTC_ALRMAR_MNU_Pos (8U) 5396 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 5397 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 5398 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 5399 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 5400 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 5401 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 5402 #define RTC_ALRMAR_MSK1_Pos (7U) 5403 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 5404 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 5405 #define RTC_ALRMAR_ST_Pos (4U) 5406 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 5407 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 5408 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 5409 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 5410 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 5411 #define RTC_ALRMAR_SU_Pos (0U) 5412 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 5413 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 5414 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 5415 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 5416 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 5417 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 5418 5419 /******************** Bits definition for RTC_ALRMBR register ***************/ 5420 #define RTC_ALRMBR_MSK4_Pos (31U) 5421 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 5422 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 5423 #define RTC_ALRMBR_WDSEL_Pos (30U) 5424 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 5425 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 5426 #define RTC_ALRMBR_DT_Pos (28U) 5427 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 5428 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 5429 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 5430 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 5431 #define RTC_ALRMBR_DU_Pos (24U) 5432 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 5433 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 5434 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 5435 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 5436 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 5437 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 5438 #define RTC_ALRMBR_MSK3_Pos (23U) 5439 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 5440 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 5441 #define RTC_ALRMBR_PM_Pos (22U) 5442 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 5443 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 5444 #define RTC_ALRMBR_HT_Pos (20U) 5445 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 5446 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 5447 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 5448 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 5449 #define RTC_ALRMBR_HU_Pos (16U) 5450 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 5451 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 5452 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 5453 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 5454 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 5455 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 5456 #define RTC_ALRMBR_MSK2_Pos (15U) 5457 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 5458 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 5459 #define RTC_ALRMBR_MNT_Pos (12U) 5460 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 5461 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 5462 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 5463 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 5464 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 5465 #define RTC_ALRMBR_MNU_Pos (8U) 5466 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 5467 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 5468 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 5469 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 5470 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 5471 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 5472 #define RTC_ALRMBR_MSK1_Pos (7U) 5473 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 5474 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 5475 #define RTC_ALRMBR_ST_Pos (4U) 5476 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 5477 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 5478 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 5479 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 5480 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 5481 #define RTC_ALRMBR_SU_Pos (0U) 5482 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 5483 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 5484 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 5485 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 5486 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 5487 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 5488 5489 /******************** Bits definition for RTC_WPR register ******************/ 5490 #define RTC_WPR_KEY_Pos (0U) 5491 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 5492 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 5493 5494 /******************** Bits definition for RTC_SSR register ******************/ 5495 #define RTC_SSR_SS_Pos (0U) 5496 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 5497 #define RTC_SSR_SS RTC_SSR_SS_Msk 5498 5499 /******************** Bits definition for RTC_SHIFTR register ***************/ 5500 #define RTC_SHIFTR_SUBFS_Pos (0U) 5501 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 5502 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 5503 #define RTC_SHIFTR_ADD1S_Pos (31U) 5504 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 5505 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 5506 5507 /******************** Bits definition for RTC_TSTR register *****************/ 5508 #define RTC_TSTR_PM_Pos (22U) 5509 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 5510 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 5511 #define RTC_TSTR_HT_Pos (20U) 5512 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 5513 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 5514 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 5515 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 5516 #define RTC_TSTR_HU_Pos (16U) 5517 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 5518 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 5519 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 5520 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 5521 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 5522 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 5523 #define RTC_TSTR_MNT_Pos (12U) 5524 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 5525 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 5526 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 5527 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 5528 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 5529 #define RTC_TSTR_MNU_Pos (8U) 5530 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 5531 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 5532 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 5533 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 5534 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 5535 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 5536 #define RTC_TSTR_ST_Pos (4U) 5537 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 5538 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 5539 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 5540 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 5541 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 5542 #define RTC_TSTR_SU_Pos (0U) 5543 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 5544 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 5545 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 5546 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 5547 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 5548 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 5549 5550 /******************** Bits definition for RTC_TSDR register *****************/ 5551 #define RTC_TSDR_WDU_Pos (13U) 5552 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 5553 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 5554 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 5555 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 5556 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 5557 #define RTC_TSDR_MT_Pos (12U) 5558 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 5559 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 5560 #define RTC_TSDR_MU_Pos (8U) 5561 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 5562 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 5563 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 5564 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 5565 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 5566 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 5567 #define RTC_TSDR_DT_Pos (4U) 5568 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 5569 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 5570 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 5571 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 5572 #define RTC_TSDR_DU_Pos (0U) 5573 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 5574 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 5575 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 5576 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 5577 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 5578 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 5579 5580 /******************** Bits definition for RTC_TSSSR register ****************/ 5581 #define RTC_TSSSR_SS_Pos (0U) 5582 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 5583 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 5584 5585 /******************** Bits definition for RTC_CAL register *****************/ 5586 #define RTC_CALR_CALP_Pos (15U) 5587 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 5588 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 5589 #define RTC_CALR_CALW8_Pos (14U) 5590 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 5591 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 5592 #define RTC_CALR_CALW16_Pos (13U) 5593 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 5594 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 5595 #define RTC_CALR_CALM_Pos (0U) 5596 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 5597 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 5598 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 5599 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 5600 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 5601 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 5602 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 5603 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 5604 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 5605 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 5606 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 5607 5608 /******************** Bits definition for RTC_TAFCR register ****************/ 5609 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) 5610 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ 5611 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk 5612 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 5613 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 5614 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 5615 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 5616 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 5617 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 5618 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 5619 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 5620 #define RTC_TAFCR_TAMPFLT_Pos (11U) 5621 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 5622 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 5623 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 5624 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 5625 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 5626 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 5627 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 5628 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 5629 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 5630 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 5631 #define RTC_TAFCR_TAMPTS_Pos (7U) 5632 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 5633 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 5634 #define RTC_TAFCR_TAMP3TRG_Pos (6U) 5635 #define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 5636 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk 5637 #define RTC_TAFCR_TAMP3E_Pos (5U) 5638 #define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ 5639 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk 5640 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 5641 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 5642 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 5643 #define RTC_TAFCR_TAMP2E_Pos (3U) 5644 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 5645 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 5646 #define RTC_TAFCR_TAMPIE_Pos (2U) 5647 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 5648 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 5649 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 5650 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 5651 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 5652 #define RTC_TAFCR_TAMP1E_Pos (0U) 5653 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 5654 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 5655 5656 /******************** Bits definition for RTC_ALRMASSR register *************/ 5657 #define RTC_ALRMASSR_MASKSS_Pos (24U) 5658 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 5659 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 5660 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 5661 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 5662 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 5663 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 5664 #define RTC_ALRMASSR_SS_Pos (0U) 5665 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 5666 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 5667 5668 /******************** Bits definition for RTC_ALRMBSSR register *************/ 5669 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 5670 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 5671 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 5672 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 5673 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 5674 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 5675 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 5676 #define RTC_ALRMBSSR_SS_Pos (0U) 5677 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 5678 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 5679 5680 /******************** Bits definition for RTC_BKP0R register ****************/ 5681 #define RTC_BKP0R_Pos (0U) 5682 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5683 #define RTC_BKP0R RTC_BKP0R_Msk 5684 5685 /******************** Bits definition for RTC_BKP1R register ****************/ 5686 #define RTC_BKP1R_Pos (0U) 5687 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5688 #define RTC_BKP1R RTC_BKP1R_Msk 5689 5690 /******************** Bits definition for RTC_BKP2R register ****************/ 5691 #define RTC_BKP2R_Pos (0U) 5692 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5693 #define RTC_BKP2R RTC_BKP2R_Msk 5694 5695 /******************** Bits definition for RTC_BKP3R register ****************/ 5696 #define RTC_BKP3R_Pos (0U) 5697 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5698 #define RTC_BKP3R RTC_BKP3R_Msk 5699 5700 /******************** Bits definition for RTC_BKP4R register ****************/ 5701 #define RTC_BKP4R_Pos (0U) 5702 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5703 #define RTC_BKP4R RTC_BKP4R_Msk 5704 5705 /******************** Bits definition for RTC_BKP5R register ****************/ 5706 #define RTC_BKP5R_Pos (0U) 5707 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 5708 #define RTC_BKP5R RTC_BKP5R_Msk 5709 5710 /******************** Bits definition for RTC_BKP6R register ****************/ 5711 #define RTC_BKP6R_Pos (0U) 5712 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 5713 #define RTC_BKP6R RTC_BKP6R_Msk 5714 5715 /******************** Bits definition for RTC_BKP7R register ****************/ 5716 #define RTC_BKP7R_Pos (0U) 5717 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 5718 #define RTC_BKP7R RTC_BKP7R_Msk 5719 5720 /******************** Bits definition for RTC_BKP8R register ****************/ 5721 #define RTC_BKP8R_Pos (0U) 5722 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 5723 #define RTC_BKP8R RTC_BKP8R_Msk 5724 5725 /******************** Bits definition for RTC_BKP9R register ****************/ 5726 #define RTC_BKP9R_Pos (0U) 5727 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 5728 #define RTC_BKP9R RTC_BKP9R_Msk 5729 5730 /******************** Bits definition for RTC_BKP10R register ***************/ 5731 #define RTC_BKP10R_Pos (0U) 5732 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 5733 #define RTC_BKP10R RTC_BKP10R_Msk 5734 5735 /******************** Bits definition for RTC_BKP11R register ***************/ 5736 #define RTC_BKP11R_Pos (0U) 5737 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 5738 #define RTC_BKP11R RTC_BKP11R_Msk 5739 5740 /******************** Bits definition for RTC_BKP12R register ***************/ 5741 #define RTC_BKP12R_Pos (0U) 5742 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 5743 #define RTC_BKP12R RTC_BKP12R_Msk 5744 5745 /******************** Bits definition for RTC_BKP13R register ***************/ 5746 #define RTC_BKP13R_Pos (0U) 5747 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 5748 #define RTC_BKP13R RTC_BKP13R_Msk 5749 5750 /******************** Bits definition for RTC_BKP14R register ***************/ 5751 #define RTC_BKP14R_Pos (0U) 5752 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 5753 #define RTC_BKP14R RTC_BKP14R_Msk 5754 5755 /******************** Bits definition for RTC_BKP15R register ***************/ 5756 #define RTC_BKP15R_Pos (0U) 5757 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 5758 #define RTC_BKP15R RTC_BKP15R_Msk 5759 5760 /******************** Bits definition for RTC_BKP16R register ***************/ 5761 #define RTC_BKP16R_Pos (0U) 5762 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 5763 #define RTC_BKP16R RTC_BKP16R_Msk 5764 5765 /******************** Bits definition for RTC_BKP17R register ***************/ 5766 #define RTC_BKP17R_Pos (0U) 5767 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 5768 #define RTC_BKP17R RTC_BKP17R_Msk 5769 5770 /******************** Bits definition for RTC_BKP18R register ***************/ 5771 #define RTC_BKP18R_Pos (0U) 5772 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 5773 #define RTC_BKP18R RTC_BKP18R_Msk 5774 5775 /******************** Bits definition for RTC_BKP19R register ***************/ 5776 #define RTC_BKP19R_Pos (0U) 5777 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 5778 #define RTC_BKP19R RTC_BKP19R_Msk 5779 5780 /******************** Bits definition for RTC_BKP20R register ***************/ 5781 #define RTC_BKP20R_Pos (0U) 5782 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ 5783 #define RTC_BKP20R RTC_BKP20R_Msk 5784 5785 /******************** Bits definition for RTC_BKP21R register ***************/ 5786 #define RTC_BKP21R_Pos (0U) 5787 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ 5788 #define RTC_BKP21R RTC_BKP21R_Msk 5789 5790 /******************** Bits definition for RTC_BKP22R register ***************/ 5791 #define RTC_BKP22R_Pos (0U) 5792 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ 5793 #define RTC_BKP22R RTC_BKP22R_Msk 5794 5795 /******************** Bits definition for RTC_BKP23R register ***************/ 5796 #define RTC_BKP23R_Pos (0U) 5797 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ 5798 #define RTC_BKP23R RTC_BKP23R_Msk 5799 5800 /******************** Bits definition for RTC_BKP24R register ***************/ 5801 #define RTC_BKP24R_Pos (0U) 5802 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ 5803 #define RTC_BKP24R RTC_BKP24R_Msk 5804 5805 /******************** Bits definition for RTC_BKP25R register ***************/ 5806 #define RTC_BKP25R_Pos (0U) 5807 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ 5808 #define RTC_BKP25R RTC_BKP25R_Msk 5809 5810 /******************** Bits definition for RTC_BKP26R register ***************/ 5811 #define RTC_BKP26R_Pos (0U) 5812 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ 5813 #define RTC_BKP26R RTC_BKP26R_Msk 5814 5815 /******************** Bits definition for RTC_BKP27R register ***************/ 5816 #define RTC_BKP27R_Pos (0U) 5817 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ 5818 #define RTC_BKP27R RTC_BKP27R_Msk 5819 5820 /******************** Bits definition for RTC_BKP28R register ***************/ 5821 #define RTC_BKP28R_Pos (0U) 5822 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ 5823 #define RTC_BKP28R RTC_BKP28R_Msk 5824 5825 /******************** Bits definition for RTC_BKP29R register ***************/ 5826 #define RTC_BKP29R_Pos (0U) 5827 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ 5828 #define RTC_BKP29R RTC_BKP29R_Msk 5829 5830 /******************** Bits definition for RTC_BKP30R register ***************/ 5831 #define RTC_BKP30R_Pos (0U) 5832 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ 5833 #define RTC_BKP30R RTC_BKP30R_Msk 5834 5835 /******************** Bits definition for RTC_BKP31R register ***************/ 5836 #define RTC_BKP31R_Pos (0U) 5837 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ 5838 #define RTC_BKP31R RTC_BKP31R_Msk 5839 5840 /******************** Number of backup registers ******************************/ 5841 #define RTC_BKP_NUMBER 32 5842 5843 /******************************************************************************/ 5844 /* */ 5845 /* SD host Interface */ 5846 /* */ 5847 /******************************************************************************/ 5848 5849 /****************** Bit definition for SDIO_POWER register ******************/ 5850 #define SDIO_POWER_PWRCTRL_Pos (0U) 5851 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ 5852 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ 5853 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000001 */ 5854 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000002 */ 5855 5856 /****************** Bit definition for SDIO_CLKCR register ******************/ 5857 #define SDIO_CLKCR_CLKDIV_Pos (0U) 5858 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ 5859 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ 5860 #define SDIO_CLKCR_CLKEN_Pos (8U) 5861 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ 5862 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ 5863 #define SDIO_CLKCR_PWRSAV_Pos (9U) 5864 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ 5865 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ 5866 #define SDIO_CLKCR_BYPASS_Pos (10U) 5867 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ 5868 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ 5869 5870 #define SDIO_CLKCR_WIDBUS_Pos (11U) 5871 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ 5872 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ 5873 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */ 5874 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */ 5875 5876 #define SDIO_CLKCR_NEGEDGE_Pos (13U) 5877 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ 5878 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ 5879 #define SDIO_CLKCR_HWFC_EN_Pos (14U) 5880 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ 5881 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ 5882 5883 /******************* Bit definition for SDIO_ARG register *******************/ 5884 #define SDIO_ARG_CMDARG_Pos (0U) 5885 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ 5886 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ 5887 5888 /******************* Bit definition for SDIO_CMD register *******************/ 5889 #define SDIO_CMD_CMDINDEX_Pos (0U) 5890 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ 5891 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ 5892 5893 #define SDIO_CMD_WAITRESP_Pos (6U) 5894 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ 5895 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ 5896 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000040 */ 5897 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000080 */ 5898 5899 #define SDIO_CMD_WAITINT_Pos (8U) 5900 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ 5901 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ 5902 #define SDIO_CMD_WAITPEND_Pos (9U) 5903 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ 5904 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ 5905 #define SDIO_CMD_CPSMEN_Pos (10U) 5906 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ 5907 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ 5908 #define SDIO_CMD_SDIOSUSPEND_Pos (11U) 5909 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ 5910 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ 5911 #define SDIO_CMD_ENCMDCOMPL_Pos (12U) 5912 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ 5913 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ 5914 #define SDIO_CMD_NIEN_Pos (13U) 5915 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ 5916 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ 5917 #define SDIO_CMD_CEATACMD_Pos (14U) 5918 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ 5919 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ 5920 5921 /***************** Bit definition for SDIO_RESPCMD register *****************/ 5922 #define SDIO_RESPCMD_RESPCMD_Pos (0U) 5923 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ 5924 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ 5925 5926 /****************** Bit definition for SDIO_RESP0 register ******************/ 5927 #define SDIO_RESP0_CARDSTATUS0_Pos (0U) 5928 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ 5929 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ 5930 5931 /****************** Bit definition for SDIO_RESP1 register ******************/ 5932 #define SDIO_RESP1_CARDSTATUS1_Pos (0U) 5933 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ 5934 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ 5935 5936 /****************** Bit definition for SDIO_RESP2 register ******************/ 5937 #define SDIO_RESP2_CARDSTATUS2_Pos (0U) 5938 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ 5939 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ 5940 5941 /****************** Bit definition for SDIO_RESP3 register ******************/ 5942 #define SDIO_RESP3_CARDSTATUS3_Pos (0U) 5943 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ 5944 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ 5945 5946 /****************** Bit definition for SDIO_RESP4 register ******************/ 5947 #define SDIO_RESP4_CARDSTATUS4_Pos (0U) 5948 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ 5949 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ 5950 5951 /****************** Bit definition for SDIO_DTIMER register *****************/ 5952 #define SDIO_DTIMER_DATATIME_Pos (0U) 5953 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ 5954 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ 5955 5956 /****************** Bit definition for SDIO_DLEN register *******************/ 5957 #define SDIO_DLEN_DATALENGTH_Pos (0U) 5958 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ 5959 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ 5960 5961 /****************** Bit definition for SDIO_DCTRL register ******************/ 5962 #define SDIO_DCTRL_DTEN_Pos (0U) 5963 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ 5964 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ 5965 #define SDIO_DCTRL_DTDIR_Pos (1U) 5966 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ 5967 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ 5968 #define SDIO_DCTRL_DTMODE_Pos (2U) 5969 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ 5970 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ 5971 #define SDIO_DCTRL_DMAEN_Pos (3U) 5972 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ 5973 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ 5974 5975 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) 5976 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ 5977 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ 5978 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */ 5979 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */ 5980 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */ 5981 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */ 5982 5983 #define SDIO_DCTRL_RWSTART_Pos (8U) 5984 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ 5985 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ 5986 #define SDIO_DCTRL_RWSTOP_Pos (9U) 5987 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ 5988 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ 5989 #define SDIO_DCTRL_RWMOD_Pos (10U) 5990 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ 5991 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ 5992 #define SDIO_DCTRL_SDIOEN_Pos (11U) 5993 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ 5994 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ 5995 5996 /****************** Bit definition for SDIO_DCOUNT register *****************/ 5997 #define SDIO_DCOUNT_DATACOUNT_Pos (0U) 5998 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ 5999 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ 6000 6001 /****************** Bit definition for SDIO_STA register ********************/ 6002 #define SDIO_STA_CCRCFAIL_Pos (0U) 6003 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ 6004 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ 6005 #define SDIO_STA_DCRCFAIL_Pos (1U) 6006 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ 6007 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ 6008 #define SDIO_STA_CTIMEOUT_Pos (2U) 6009 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ 6010 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ 6011 #define SDIO_STA_DTIMEOUT_Pos (3U) 6012 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ 6013 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ 6014 #define SDIO_STA_TXUNDERR_Pos (4U) 6015 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ 6016 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ 6017 #define SDIO_STA_RXOVERR_Pos (5U) 6018 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ 6019 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ 6020 #define SDIO_STA_CMDREND_Pos (6U) 6021 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ 6022 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ 6023 #define SDIO_STA_CMDSENT_Pos (7U) 6024 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ 6025 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ 6026 #define SDIO_STA_DATAEND_Pos (8U) 6027 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ 6028 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ 6029 #define SDIO_STA_STBITERR_Pos (9U) 6030 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ 6031 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ 6032 #define SDIO_STA_DBCKEND_Pos (10U) 6033 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ 6034 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ 6035 #define SDIO_STA_CMDACT_Pos (11U) 6036 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ 6037 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ 6038 #define SDIO_STA_TXACT_Pos (12U) 6039 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ 6040 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ 6041 #define SDIO_STA_RXACT_Pos (13U) 6042 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ 6043 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ 6044 #define SDIO_STA_TXFIFOHE_Pos (14U) 6045 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ 6046 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ 6047 #define SDIO_STA_RXFIFOHF_Pos (15U) 6048 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ 6049 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ 6050 #define SDIO_STA_TXFIFOF_Pos (16U) 6051 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ 6052 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ 6053 #define SDIO_STA_RXFIFOF_Pos (17U) 6054 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ 6055 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ 6056 #define SDIO_STA_TXFIFOE_Pos (18U) 6057 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ 6058 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ 6059 #define SDIO_STA_RXFIFOE_Pos (19U) 6060 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ 6061 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ 6062 #define SDIO_STA_TXDAVL_Pos (20U) 6063 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ 6064 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ 6065 #define SDIO_STA_RXDAVL_Pos (21U) 6066 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ 6067 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ 6068 #define SDIO_STA_SDIOIT_Pos (22U) 6069 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ 6070 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ 6071 #define SDIO_STA_CEATAEND_Pos (23U) 6072 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ 6073 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ 6074 6075 /******************* Bit definition for SDIO_ICR register *******************/ 6076 #define SDIO_ICR_CCRCFAILC_Pos (0U) 6077 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ 6078 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ 6079 #define SDIO_ICR_DCRCFAILC_Pos (1U) 6080 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ 6081 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ 6082 #define SDIO_ICR_CTIMEOUTC_Pos (2U) 6083 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ 6084 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ 6085 #define SDIO_ICR_DTIMEOUTC_Pos (3U) 6086 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ 6087 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ 6088 #define SDIO_ICR_TXUNDERRC_Pos (4U) 6089 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ 6090 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ 6091 #define SDIO_ICR_RXOVERRC_Pos (5U) 6092 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ 6093 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ 6094 #define SDIO_ICR_CMDRENDC_Pos (6U) 6095 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ 6096 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ 6097 #define SDIO_ICR_CMDSENTC_Pos (7U) 6098 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ 6099 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ 6100 #define SDIO_ICR_DATAENDC_Pos (8U) 6101 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ 6102 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ 6103 #define SDIO_ICR_STBITERRC_Pos (9U) 6104 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ 6105 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ 6106 #define SDIO_ICR_DBCKENDC_Pos (10U) 6107 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ 6108 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ 6109 #define SDIO_ICR_SDIOITC_Pos (22U) 6110 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ 6111 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ 6112 #define SDIO_ICR_CEATAENDC_Pos (23U) 6113 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ 6114 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ 6115 6116 /****************** Bit definition for SDIO_MASK register *******************/ 6117 #define SDIO_MASK_CCRCFAILIE_Pos (0U) 6118 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ 6119 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ 6120 #define SDIO_MASK_DCRCFAILIE_Pos (1U) 6121 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ 6122 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ 6123 #define SDIO_MASK_CTIMEOUTIE_Pos (2U) 6124 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ 6125 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ 6126 #define SDIO_MASK_DTIMEOUTIE_Pos (3U) 6127 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ 6128 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ 6129 #define SDIO_MASK_TXUNDERRIE_Pos (4U) 6130 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ 6131 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ 6132 #define SDIO_MASK_RXOVERRIE_Pos (5U) 6133 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ 6134 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ 6135 #define SDIO_MASK_CMDRENDIE_Pos (6U) 6136 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ 6137 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ 6138 #define SDIO_MASK_CMDSENTIE_Pos (7U) 6139 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ 6140 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ 6141 #define SDIO_MASK_DATAENDIE_Pos (8U) 6142 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ 6143 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ 6144 #define SDIO_MASK_STBITERRIE_Pos (9U) 6145 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ 6146 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ 6147 #define SDIO_MASK_DBCKENDIE_Pos (10U) 6148 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ 6149 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ 6150 #define SDIO_MASK_CMDACTIE_Pos (11U) 6151 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ 6152 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ 6153 #define SDIO_MASK_TXACTIE_Pos (12U) 6154 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ 6155 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ 6156 #define SDIO_MASK_RXACTIE_Pos (13U) 6157 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ 6158 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ 6159 #define SDIO_MASK_TXFIFOHEIE_Pos (14U) 6160 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ 6161 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ 6162 #define SDIO_MASK_RXFIFOHFIE_Pos (15U) 6163 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ 6164 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ 6165 #define SDIO_MASK_TXFIFOFIE_Pos (16U) 6166 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ 6167 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ 6168 #define SDIO_MASK_RXFIFOFIE_Pos (17U) 6169 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ 6170 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ 6171 #define SDIO_MASK_TXFIFOEIE_Pos (18U) 6172 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ 6173 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ 6174 #define SDIO_MASK_RXFIFOEIE_Pos (19U) 6175 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ 6176 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ 6177 #define SDIO_MASK_TXDAVLIE_Pos (20U) 6178 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ 6179 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ 6180 #define SDIO_MASK_RXDAVLIE_Pos (21U) 6181 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ 6182 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ 6183 #define SDIO_MASK_SDIOITIE_Pos (22U) 6184 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ 6185 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ 6186 #define SDIO_MASK_CEATAENDIE_Pos (23U) 6187 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ 6188 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ 6189 6190 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 6191 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) 6192 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ 6193 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ 6194 6195 /****************** Bit definition for SDIO_FIFO register *******************/ 6196 #define SDIO_FIFO_FIFODATA_Pos (0U) 6197 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ 6198 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ 6199 6200 /******************************************************************************/ 6201 /* */ 6202 /* Serial Peripheral Interface (SPI) */ 6203 /* */ 6204 /******************************************************************************/ 6205 6206 /* 6207 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 6208 */ 6209 #define SPI_I2S_SUPPORT 6210 6211 /******************* Bit definition for SPI_CR1 register ********************/ 6212 #define SPI_CR1_CPHA_Pos (0U) 6213 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 6214 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 6215 #define SPI_CR1_CPOL_Pos (1U) 6216 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 6217 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 6218 #define SPI_CR1_MSTR_Pos (2U) 6219 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 6220 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 6221 6222 #define SPI_CR1_BR_Pos (3U) 6223 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 6224 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 6225 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 6226 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 6227 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 6228 6229 #define SPI_CR1_SPE_Pos (6U) 6230 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 6231 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 6232 #define SPI_CR1_LSBFIRST_Pos (7U) 6233 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 6234 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 6235 #define SPI_CR1_SSI_Pos (8U) 6236 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 6237 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 6238 #define SPI_CR1_SSM_Pos (9U) 6239 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 6240 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 6241 #define SPI_CR1_RXONLY_Pos (10U) 6242 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 6243 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 6244 #define SPI_CR1_DFF_Pos (11U) 6245 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 6246 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 6247 #define SPI_CR1_CRCNEXT_Pos (12U) 6248 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 6249 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 6250 #define SPI_CR1_CRCEN_Pos (13U) 6251 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 6252 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 6253 #define SPI_CR1_BIDIOE_Pos (14U) 6254 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 6255 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 6256 #define SPI_CR1_BIDIMODE_Pos (15U) 6257 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 6258 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 6259 6260 /******************* Bit definition for SPI_CR2 register ********************/ 6261 #define SPI_CR2_RXDMAEN_Pos (0U) 6262 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 6263 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 6264 #define SPI_CR2_TXDMAEN_Pos (1U) 6265 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 6266 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 6267 #define SPI_CR2_SSOE_Pos (2U) 6268 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 6269 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 6270 #define SPI_CR2_FRF_Pos (4U) 6271 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 6272 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */ 6273 #define SPI_CR2_ERRIE_Pos (5U) 6274 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 6275 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 6276 #define SPI_CR2_RXNEIE_Pos (6U) 6277 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 6278 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 6279 #define SPI_CR2_TXEIE_Pos (7U) 6280 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 6281 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 6282 6283 /******************** Bit definition for SPI_SR register ********************/ 6284 #define SPI_SR_RXNE_Pos (0U) 6285 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 6286 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 6287 #define SPI_SR_TXE_Pos (1U) 6288 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 6289 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 6290 #define SPI_SR_CHSIDE_Pos (2U) 6291 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 6292 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 6293 #define SPI_SR_UDR_Pos (3U) 6294 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 6295 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 6296 #define SPI_SR_CRCERR_Pos (4U) 6297 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 6298 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 6299 #define SPI_SR_MODF_Pos (5U) 6300 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 6301 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 6302 #define SPI_SR_OVR_Pos (6U) 6303 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 6304 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 6305 #define SPI_SR_BSY_Pos (7U) 6306 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 6307 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 6308 #define SPI_SR_FRE_Pos (8U) 6309 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 6310 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ 6311 6312 /******************** Bit definition for SPI_DR register ********************/ 6313 #define SPI_DR_DR_Pos (0U) 6314 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 6315 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 6316 6317 /******************* Bit definition for SPI_CRCPR register ******************/ 6318 #define SPI_CRCPR_CRCPOLY_Pos (0U) 6319 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 6320 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 6321 6322 /****************** Bit definition for SPI_RXCRCR register ******************/ 6323 #define SPI_RXCRCR_RXCRC_Pos (0U) 6324 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 6325 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 6326 6327 /****************** Bit definition for SPI_TXCRCR register ******************/ 6328 #define SPI_TXCRCR_TXCRC_Pos (0U) 6329 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 6330 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 6331 6332 /****************** Bit definition for SPI_I2SCFGR register *****************/ 6333 #define SPI_I2SCFGR_CHLEN_Pos (0U) 6334 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 6335 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 6336 6337 #define SPI_I2SCFGR_DATLEN_Pos (1U) 6338 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 6339 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 6340 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 6341 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 6342 6343 #define SPI_I2SCFGR_CKPOL_Pos (3U) 6344 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 6345 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 6346 6347 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 6348 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 6349 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 6350 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 6351 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 6352 6353 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 6354 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 6355 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 6356 6357 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 6358 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 6359 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 6360 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 6361 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 6362 6363 #define SPI_I2SCFGR_I2SE_Pos (10U) 6364 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 6365 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 6366 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 6367 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 6368 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 6369 6370 /****************** Bit definition for SPI_I2SPR register *******************/ 6371 #define SPI_I2SPR_I2SDIV_Pos (0U) 6372 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 6373 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 6374 #define SPI_I2SPR_ODD_Pos (8U) 6375 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 6376 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 6377 #define SPI_I2SPR_MCKOE_Pos (9U) 6378 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 6379 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 6380 6381 /******************************************************************************/ 6382 /* */ 6383 /* System Configuration (SYSCFG) */ 6384 /* */ 6385 /******************************************************************************/ 6386 /***************** Bit definition for SYSCFG_MEMRMP register ****************/ 6387 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 6388 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ 6389 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 6390 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 6391 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 6392 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) 6393 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */ 6394 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */ 6395 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */ 6396 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */ 6397 6398 /***************** Bit definition for SYSCFG_PMC register *******************/ 6399 #define SYSCFG_PMC_USB_PU_Pos (0U) 6400 #define SYSCFG_PMC_USB_PU_Msk (0x1UL << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */ 6401 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */ 6402 6403 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 6404 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 6405 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 6406 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 6407 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 6408 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 6409 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 6410 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 6411 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 6412 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 6413 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 6414 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 6415 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 6416 6417 /** 6418 * @brief EXTI0 configuration 6419 */ 6420 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 6421 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 6422 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 6423 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 6424 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 6425 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 6426 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */ 6427 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */ 6428 6429 /** 6430 * @brief EXTI1 configuration 6431 */ 6432 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 6433 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 6434 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 6435 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 6436 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 6437 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 6438 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */ 6439 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */ 6440 6441 /** 6442 * @brief EXTI2 configuration 6443 */ 6444 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 6445 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 6446 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 6447 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 6448 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 6449 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */ 6450 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */ 6451 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */ 6452 6453 /** 6454 * @brief EXTI3 configuration 6455 */ 6456 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 6457 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 6458 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 6459 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 6460 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 6461 #define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ 6462 #define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ 6463 6464 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 6465 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 6466 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 6467 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 6468 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 6469 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 6470 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 6471 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 6472 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 6473 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 6474 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 6475 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 6476 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 6477 6478 /** 6479 * @brief EXTI4 configuration 6480 */ 6481 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 6482 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 6483 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 6484 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 6485 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 6486 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */ 6487 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */ 6488 6489 /** 6490 * @brief EXTI5 configuration 6491 */ 6492 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 6493 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 6494 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 6495 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 6496 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 6497 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */ 6498 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */ 6499 6500 /** 6501 * @brief EXTI6 configuration 6502 */ 6503 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 6504 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 6505 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 6506 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 6507 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 6508 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */ 6509 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */ 6510 6511 /** 6512 * @brief EXTI7 configuration 6513 */ 6514 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 6515 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 6516 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 6517 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 6518 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 6519 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */ 6520 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */ 6521 6522 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 6523 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 6524 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 6525 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 6526 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 6527 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 6528 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 6529 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 6530 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 6531 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 6532 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 6533 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 6534 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 6535 6536 /** 6537 * @brief EXTI8 configuration 6538 */ 6539 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 6540 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 6541 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 6542 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 6543 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 6544 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */ 6545 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */ 6546 6547 /** 6548 * @brief EXTI9 configuration 6549 */ 6550 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 6551 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 6552 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 6553 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 6554 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 6555 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */ 6556 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */ 6557 6558 /** 6559 * @brief EXTI10 configuration 6560 */ 6561 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 6562 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 6563 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 6564 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 6565 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 6566 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */ 6567 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */ 6568 6569 /** 6570 * @brief EXTI11 configuration 6571 */ 6572 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 6573 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 6574 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 6575 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 6576 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 6577 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */ 6578 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */ 6579 6580 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 6581 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 6582 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 6583 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 6584 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 6585 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 6586 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 6587 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 6588 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 6589 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 6590 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 6591 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 6592 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 6593 6594 /** 6595 * @brief EXTI12 configuration 6596 */ 6597 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 6598 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 6599 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 6600 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 6601 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 6602 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */ 6603 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */ 6604 6605 /** 6606 * @brief EXTI13 configuration 6607 */ 6608 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 6609 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 6610 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 6611 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 6612 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 6613 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */ 6614 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */ 6615 6616 /** 6617 * @brief EXTI14 configuration 6618 */ 6619 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 6620 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 6621 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 6622 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 6623 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 6624 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */ 6625 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */ 6626 6627 /** 6628 * @brief EXTI15 configuration 6629 */ 6630 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 6631 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 6632 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 6633 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 6634 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 6635 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ 6636 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ 6637 6638 /******************************************************************************/ 6639 /* */ 6640 /* Routing Interface (RI) */ 6641 /* */ 6642 /******************************************************************************/ 6643 6644 /******************** Bit definition for RI_ICR register ********************/ 6645 #define RI_ICR_IC1OS_Pos (0U) 6646 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */ 6647 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */ 6648 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */ 6649 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */ 6650 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */ 6651 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */ 6652 6653 #define RI_ICR_IC2OS_Pos (4U) 6654 #define RI_ICR_IC2OS_Msk (0xFUL << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */ 6655 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */ 6656 #define RI_ICR_IC2OS_0 (0x1UL << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */ 6657 #define RI_ICR_IC2OS_1 (0x2UL << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */ 6658 #define RI_ICR_IC2OS_2 (0x4UL << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */ 6659 #define RI_ICR_IC2OS_3 (0x8UL << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */ 6660 6661 #define RI_ICR_IC3OS_Pos (8U) 6662 #define RI_ICR_IC3OS_Msk (0xFUL << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */ 6663 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */ 6664 #define RI_ICR_IC3OS_0 (0x1UL << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */ 6665 #define RI_ICR_IC3OS_1 (0x2UL << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */ 6666 #define RI_ICR_IC3OS_2 (0x4UL << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */ 6667 #define RI_ICR_IC3OS_3 (0x8UL << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */ 6668 6669 #define RI_ICR_IC4OS_Pos (12U) 6670 #define RI_ICR_IC4OS_Msk (0xFUL << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */ 6671 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */ 6672 #define RI_ICR_IC4OS_0 (0x1UL << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */ 6673 #define RI_ICR_IC4OS_1 (0x2UL << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */ 6674 #define RI_ICR_IC4OS_2 (0x4UL << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */ 6675 #define RI_ICR_IC4OS_3 (0x8UL << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */ 6676 6677 #define RI_ICR_TIM_Pos (16U) 6678 #define RI_ICR_TIM_Msk (0x3UL << RI_ICR_TIM_Pos) /*!< 0x00030000 */ 6679 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */ 6680 #define RI_ICR_TIM_0 (0x1UL << RI_ICR_TIM_Pos) /*!< 0x00010000 */ 6681 #define RI_ICR_TIM_1 (0x2UL << RI_ICR_TIM_Pos) /*!< 0x00020000 */ 6682 6683 #define RI_ICR_IC1_Pos (18U) 6684 #define RI_ICR_IC1_Msk (0x1UL << RI_ICR_IC1_Pos) /*!< 0x00040000 */ 6685 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */ 6686 #define RI_ICR_IC2_Pos (19U) 6687 #define RI_ICR_IC2_Msk (0x1UL << RI_ICR_IC2_Pos) /*!< 0x00080000 */ 6688 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */ 6689 #define RI_ICR_IC3_Pos (20U) 6690 #define RI_ICR_IC3_Msk (0x1UL << RI_ICR_IC3_Pos) /*!< 0x00100000 */ 6691 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */ 6692 #define RI_ICR_IC4_Pos (21U) 6693 #define RI_ICR_IC4_Msk (0x1UL << RI_ICR_IC4_Pos) /*!< 0x00200000 */ 6694 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */ 6695 6696 /******************** Bit definition for RI_ASCR1 register ********************/ 6697 #define RI_ASCR1_CH_Pos (0U) 6698 #define RI_ASCR1_CH_Msk (0x7BFDFFFFUL << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */ 6699 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */ 6700 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */ 6701 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */ 6702 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */ 6703 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */ 6704 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */ 6705 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */ 6706 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */ 6707 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */ 6708 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */ 6709 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */ 6710 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */ 6711 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */ 6712 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */ 6713 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */ 6714 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */ 6715 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */ 6716 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */ 6717 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */ 6718 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */ 6719 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */ 6720 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */ 6721 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */ 6722 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */ 6723 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */ 6724 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */ 6725 #define RI_ASCR1_VCOMP_Pos (26U) 6726 #define RI_ASCR1_VCOMP_Msk (0x1UL << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */ 6727 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */ 6728 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */ 6729 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */ 6730 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */ 6731 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */ 6732 #define RI_ASCR1_SCM_Pos (31U) 6733 #define RI_ASCR1_SCM_Msk (0x1UL << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */ 6734 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */ 6735 6736 /******************** Bit definition for RI_ASCR2 register ********************/ 6737 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */ 6738 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */ 6739 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */ 6740 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */ 6741 #define RI_ASCR2_GR6_Pos (4U) 6742 #define RI_ASCR2_GR6_Msk (0x1800003UL << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */ 6743 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */ 6744 #define RI_ASCR2_GR6_1 (0x0000001UL << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */ 6745 #define RI_ASCR2_GR6_2 (0x0000002UL << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */ 6746 #define RI_ASCR2_GR6_3 (0x0800000UL << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */ 6747 #define RI_ASCR2_GR6_4 (0x1000000UL << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */ 6748 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */ 6749 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */ 6750 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */ 6751 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */ 6752 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */ 6753 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */ 6754 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */ 6755 #define RI_ASCR2_CH0b_Pos (16U) 6756 #define RI_ASCR2_CH0b_Msk (0x1UL << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */ 6757 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */ 6758 #define RI_ASCR2_CH1b_Pos (17U) 6759 #define RI_ASCR2_CH1b_Msk (0x1UL << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */ 6760 #define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */ 6761 #define RI_ASCR2_CH2b_Pos (18U) 6762 #define RI_ASCR2_CH2b_Msk (0x1UL << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */ 6763 #define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */ 6764 #define RI_ASCR2_CH3b_Pos (19U) 6765 #define RI_ASCR2_CH3b_Msk (0x1UL << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */ 6766 #define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */ 6767 #define RI_ASCR2_CH6b_Pos (20U) 6768 #define RI_ASCR2_CH6b_Msk (0x1UL << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */ 6769 #define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */ 6770 #define RI_ASCR2_CH7b_Pos (21U) 6771 #define RI_ASCR2_CH7b_Msk (0x1UL << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */ 6772 #define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */ 6773 #define RI_ASCR2_CH8b_Pos (22U) 6774 #define RI_ASCR2_CH8b_Msk (0x1UL << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */ 6775 #define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */ 6776 #define RI_ASCR2_CH9b_Pos (23U) 6777 #define RI_ASCR2_CH9b_Msk (0x1UL << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */ 6778 #define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */ 6779 #define RI_ASCR2_CH10b_Pos (24U) 6780 #define RI_ASCR2_CH10b_Msk (0x1UL << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */ 6781 #define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */ 6782 #define RI_ASCR2_CH11b_Pos (25U) 6783 #define RI_ASCR2_CH11b_Msk (0x1UL << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */ 6784 #define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */ 6785 #define RI_ASCR2_CH12b_Pos (26U) 6786 #define RI_ASCR2_CH12b_Msk (0x1UL << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */ 6787 #define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */ 6788 6789 /******************** Bit definition for RI_HYSCR1 register ********************/ 6790 #define RI_HYSCR1_PA_Pos (0U) 6791 #define RI_HYSCR1_PA_Msk (0xFFFFUL << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */ 6792 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */ 6793 #define RI_HYSCR1_PA_0 (0x0001UL << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */ 6794 #define RI_HYSCR1_PA_1 (0x0002UL << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */ 6795 #define RI_HYSCR1_PA_2 (0x0004UL << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */ 6796 #define RI_HYSCR1_PA_3 (0x0008UL << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */ 6797 #define RI_HYSCR1_PA_4 (0x0010UL << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */ 6798 #define RI_HYSCR1_PA_5 (0x0020UL << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */ 6799 #define RI_HYSCR1_PA_6 (0x0040UL << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */ 6800 #define RI_HYSCR1_PA_7 (0x0080UL << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */ 6801 #define RI_HYSCR1_PA_8 (0x0100UL << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */ 6802 #define RI_HYSCR1_PA_9 (0x0200UL << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */ 6803 #define RI_HYSCR1_PA_10 (0x0400UL << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */ 6804 #define RI_HYSCR1_PA_11 (0x0800UL << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */ 6805 #define RI_HYSCR1_PA_12 (0x1000UL << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */ 6806 #define RI_HYSCR1_PA_13 (0x2000UL << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */ 6807 #define RI_HYSCR1_PA_14 (0x4000UL << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */ 6808 #define RI_HYSCR1_PA_15 (0x8000UL << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */ 6809 6810 #define RI_HYSCR1_PB_Pos (16U) 6811 #define RI_HYSCR1_PB_Msk (0xFFFFUL << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */ 6812 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */ 6813 #define RI_HYSCR1_PB_0 (0x0001UL << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */ 6814 #define RI_HYSCR1_PB_1 (0x0002UL << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */ 6815 #define RI_HYSCR1_PB_2 (0x0004UL << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */ 6816 #define RI_HYSCR1_PB_3 (0x0008UL << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */ 6817 #define RI_HYSCR1_PB_4 (0x0010UL << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */ 6818 #define RI_HYSCR1_PB_5 (0x0020UL << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */ 6819 #define RI_HYSCR1_PB_6 (0x0040UL << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */ 6820 #define RI_HYSCR1_PB_7 (0x0080UL << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */ 6821 #define RI_HYSCR1_PB_8 (0x0100UL << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */ 6822 #define RI_HYSCR1_PB_9 (0x0200UL << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */ 6823 #define RI_HYSCR1_PB_10 (0x0400UL << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */ 6824 #define RI_HYSCR1_PB_11 (0x0800UL << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */ 6825 #define RI_HYSCR1_PB_12 (0x1000UL << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */ 6826 #define RI_HYSCR1_PB_13 (0x2000UL << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */ 6827 #define RI_HYSCR1_PB_14 (0x4000UL << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */ 6828 #define RI_HYSCR1_PB_15 (0x8000UL << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */ 6829 6830 /******************** Bit definition for RI_HYSCR2 register ********************/ 6831 #define RI_HYSCR2_PC_Pos (0U) 6832 #define RI_HYSCR2_PC_Msk (0xFFFFUL << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */ 6833 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */ 6834 #define RI_HYSCR2_PC_0 (0x0001UL << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */ 6835 #define RI_HYSCR2_PC_1 (0x0002UL << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */ 6836 #define RI_HYSCR2_PC_2 (0x0004UL << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */ 6837 #define RI_HYSCR2_PC_3 (0x0008UL << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */ 6838 #define RI_HYSCR2_PC_4 (0x0010UL << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */ 6839 #define RI_HYSCR2_PC_5 (0x0020UL << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */ 6840 #define RI_HYSCR2_PC_6 (0x0040UL << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */ 6841 #define RI_HYSCR2_PC_7 (0x0080UL << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */ 6842 #define RI_HYSCR2_PC_8 (0x0100UL << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */ 6843 #define RI_HYSCR2_PC_9 (0x0200UL << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */ 6844 #define RI_HYSCR2_PC_10 (0x0400UL << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */ 6845 #define RI_HYSCR2_PC_11 (0x0800UL << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */ 6846 #define RI_HYSCR2_PC_12 (0x1000UL << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */ 6847 #define RI_HYSCR2_PC_13 (0x2000UL << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */ 6848 #define RI_HYSCR2_PC_14 (0x4000UL << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */ 6849 #define RI_HYSCR2_PC_15 (0x8000UL << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */ 6850 6851 #define RI_HYSCR2_PD_Pos (16U) 6852 #define RI_HYSCR2_PD_Msk (0xFFFFUL << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */ 6853 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */ 6854 #define RI_HYSCR2_PD_0 (0x0001UL << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */ 6855 #define RI_HYSCR2_PD_1 (0x0002UL << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */ 6856 #define RI_HYSCR2_PD_2 (0x0004UL << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */ 6857 #define RI_HYSCR2_PD_3 (0x0008UL << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */ 6858 #define RI_HYSCR2_PD_4 (0x0010UL << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */ 6859 #define RI_HYSCR2_PD_5 (0x0020UL << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */ 6860 #define RI_HYSCR2_PD_6 (0x0040UL << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */ 6861 #define RI_HYSCR2_PD_7 (0x0080UL << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */ 6862 #define RI_HYSCR2_PD_8 (0x0100UL << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */ 6863 #define RI_HYSCR2_PD_9 (0x0200UL << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */ 6864 #define RI_HYSCR2_PD_10 (0x0400UL << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */ 6865 #define RI_HYSCR2_PD_11 (0x0800UL << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */ 6866 #define RI_HYSCR2_PD_12 (0x1000UL << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */ 6867 #define RI_HYSCR2_PD_13 (0x2000UL << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */ 6868 #define RI_HYSCR2_PD_14 (0x4000UL << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ 6869 #define RI_HYSCR2_PD_15 (0x8000UL << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ 6870 6871 /******************** Bit definition for RI_HYSCR3 register ********************/ 6872 #define RI_HYSCR3_PE_Pos (0U) 6873 #define RI_HYSCR3_PE_Msk (0xFFFFUL << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ 6874 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ 6875 #define RI_HYSCR3_PE_0 (0x0001UL << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ 6876 #define RI_HYSCR3_PE_1 (0x0002UL << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ 6877 #define RI_HYSCR3_PE_2 (0x0004UL << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ 6878 #define RI_HYSCR3_PE_3 (0x0008UL << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ 6879 #define RI_HYSCR3_PE_4 (0x0010UL << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ 6880 #define RI_HYSCR3_PE_5 (0x0020UL << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ 6881 #define RI_HYSCR3_PE_6 (0x0040UL << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ 6882 #define RI_HYSCR3_PE_7 (0x0080UL << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ 6883 #define RI_HYSCR3_PE_8 (0x0100UL << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ 6884 #define RI_HYSCR3_PE_9 (0x0200UL << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ 6885 #define RI_HYSCR3_PE_10 (0x0400UL << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ 6886 #define RI_HYSCR3_PE_11 (0x0800UL << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ 6887 #define RI_HYSCR3_PE_12 (0x1000UL << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ 6888 #define RI_HYSCR3_PE_13 (0x2000UL << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ 6889 #define RI_HYSCR3_PE_14 (0x4000UL << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ 6890 #define RI_HYSCR3_PE_15 (0x8000UL << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ 6891 #define RI_HYSCR3_PF_Pos (16U) 6892 #define RI_HYSCR3_PF_Msk (0xFFFFUL << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ 6893 #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ 6894 #define RI_HYSCR3_PF_0 (0x0001UL << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ 6895 #define RI_HYSCR3_PF_1 (0x0002UL << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ 6896 #define RI_HYSCR3_PF_2 (0x0004UL << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ 6897 #define RI_HYSCR3_PF_3 (0x0008UL << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ 6898 #define RI_HYSCR3_PF_4 (0x0010UL << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ 6899 #define RI_HYSCR3_PF_5 (0x0020UL << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ 6900 #define RI_HYSCR3_PF_6 (0x0040UL << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ 6901 #define RI_HYSCR3_PF_7 (0x0080UL << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ 6902 #define RI_HYSCR3_PF_8 (0x0100UL << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ 6903 #define RI_HYSCR3_PF_9 (0x0200UL << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ 6904 #define RI_HYSCR3_PF_10 (0x0400UL << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ 6905 #define RI_HYSCR3_PF_11 (0x0800UL << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ 6906 #define RI_HYSCR3_PF_12 (0x1000UL << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ 6907 #define RI_HYSCR3_PF_13 (0x2000UL << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ 6908 #define RI_HYSCR3_PF_14 (0x4000UL << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ 6909 #define RI_HYSCR3_PF_15 (0x8000UL << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ 6910 /******************** Bit definition for RI_HYSCR4 register ********************/ 6911 #define RI_HYSCR4_PG_Pos (0U) 6912 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ 6913 #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ 6914 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ 6915 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ 6916 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ 6917 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ 6918 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ 6919 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ 6920 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ 6921 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ 6922 #define RI_HYSCR4_PG_8 (0x0100UL << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ 6923 #define RI_HYSCR4_PG_9 (0x0200UL << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ 6924 #define RI_HYSCR4_PG_10 (0x0400UL << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ 6925 #define RI_HYSCR4_PG_11 (0x0800UL << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ 6926 #define RI_HYSCR4_PG_12 (0x1000UL << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ 6927 #define RI_HYSCR4_PG_13 (0x2000UL << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ 6928 #define RI_HYSCR4_PG_14 (0x4000UL << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ 6929 #define RI_HYSCR4_PG_15 (0x8000UL << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ 6930 6931 /******************** Bit definition for RI_ASMR1 register ********************/ 6932 #define RI_ASMR1_PA_Pos (0U) 6933 #define RI_ASMR1_PA_Msk (0xFFFFUL << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */ 6934 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6935 #define RI_ASMR1_PA_0 (0x0001UL << RI_ASMR1_PA_Pos) /*!< 0x00000001 */ 6936 #define RI_ASMR1_PA_1 (0x0002UL << RI_ASMR1_PA_Pos) /*!< 0x00000002 */ 6937 #define RI_ASMR1_PA_2 (0x0004UL << RI_ASMR1_PA_Pos) /*!< 0x00000004 */ 6938 #define RI_ASMR1_PA_3 (0x0008UL << RI_ASMR1_PA_Pos) /*!< 0x00000008 */ 6939 #define RI_ASMR1_PA_4 (0x0010UL << RI_ASMR1_PA_Pos) /*!< 0x00000010 */ 6940 #define RI_ASMR1_PA_5 (0x0020UL << RI_ASMR1_PA_Pos) /*!< 0x00000020 */ 6941 #define RI_ASMR1_PA_6 (0x0040UL << RI_ASMR1_PA_Pos) /*!< 0x00000040 */ 6942 #define RI_ASMR1_PA_7 (0x0080UL << RI_ASMR1_PA_Pos) /*!< 0x00000080 */ 6943 #define RI_ASMR1_PA_8 (0x0100UL << RI_ASMR1_PA_Pos) /*!< 0x00000100 */ 6944 #define RI_ASMR1_PA_9 (0x0200UL << RI_ASMR1_PA_Pos) /*!< 0x00000200 */ 6945 #define RI_ASMR1_PA_10 (0x0400UL << RI_ASMR1_PA_Pos) /*!< 0x00000400 */ 6946 #define RI_ASMR1_PA_11 (0x0800UL << RI_ASMR1_PA_Pos) /*!< 0x00000800 */ 6947 #define RI_ASMR1_PA_12 (0x1000UL << RI_ASMR1_PA_Pos) /*!< 0x00001000 */ 6948 #define RI_ASMR1_PA_13 (0x2000UL << RI_ASMR1_PA_Pos) /*!< 0x00002000 */ 6949 #define RI_ASMR1_PA_14 (0x4000UL << RI_ASMR1_PA_Pos) /*!< 0x00004000 */ 6950 #define RI_ASMR1_PA_15 (0x8000UL << RI_ASMR1_PA_Pos) /*!< 0x00008000 */ 6951 6952 /******************** Bit definition for RI_CMR1 register ********************/ 6953 #define RI_CMR1_PA_Pos (0U) 6954 #define RI_CMR1_PA_Msk (0xFFFFUL << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */ 6955 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6956 #define RI_CMR1_PA_0 (0x0001UL << RI_CMR1_PA_Pos) /*!< 0x00000001 */ 6957 #define RI_CMR1_PA_1 (0x0002UL << RI_CMR1_PA_Pos) /*!< 0x00000002 */ 6958 #define RI_CMR1_PA_2 (0x0004UL << RI_CMR1_PA_Pos) /*!< 0x00000004 */ 6959 #define RI_CMR1_PA_3 (0x0008UL << RI_CMR1_PA_Pos) /*!< 0x00000008 */ 6960 #define RI_CMR1_PA_4 (0x0010UL << RI_CMR1_PA_Pos) /*!< 0x00000010 */ 6961 #define RI_CMR1_PA_5 (0x0020UL << RI_CMR1_PA_Pos) /*!< 0x00000020 */ 6962 #define RI_CMR1_PA_6 (0x0040UL << RI_CMR1_PA_Pos) /*!< 0x00000040 */ 6963 #define RI_CMR1_PA_7 (0x0080UL << RI_CMR1_PA_Pos) /*!< 0x00000080 */ 6964 #define RI_CMR1_PA_8 (0x0100UL << RI_CMR1_PA_Pos) /*!< 0x00000100 */ 6965 #define RI_CMR1_PA_9 (0x0200UL << RI_CMR1_PA_Pos) /*!< 0x00000200 */ 6966 #define RI_CMR1_PA_10 (0x0400UL << RI_CMR1_PA_Pos) /*!< 0x00000400 */ 6967 #define RI_CMR1_PA_11 (0x0800UL << RI_CMR1_PA_Pos) /*!< 0x00000800 */ 6968 #define RI_CMR1_PA_12 (0x1000UL << RI_CMR1_PA_Pos) /*!< 0x00001000 */ 6969 #define RI_CMR1_PA_13 (0x2000UL << RI_CMR1_PA_Pos) /*!< 0x00002000 */ 6970 #define RI_CMR1_PA_14 (0x4000UL << RI_CMR1_PA_Pos) /*!< 0x00004000 */ 6971 #define RI_CMR1_PA_15 (0x8000UL << RI_CMR1_PA_Pos) /*!< 0x00008000 */ 6972 6973 /******************** Bit definition for RI_CICR1 register ********************/ 6974 #define RI_CICR1_PA_Pos (0U) 6975 #define RI_CICR1_PA_Msk (0xFFFFUL << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */ 6976 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6977 #define RI_CICR1_PA_0 (0x0001UL << RI_CICR1_PA_Pos) /*!< 0x00000001 */ 6978 #define RI_CICR1_PA_1 (0x0002UL << RI_CICR1_PA_Pos) /*!< 0x00000002 */ 6979 #define RI_CICR1_PA_2 (0x0004UL << RI_CICR1_PA_Pos) /*!< 0x00000004 */ 6980 #define RI_CICR1_PA_3 (0x0008UL << RI_CICR1_PA_Pos) /*!< 0x00000008 */ 6981 #define RI_CICR1_PA_4 (0x0010UL << RI_CICR1_PA_Pos) /*!< 0x00000010 */ 6982 #define RI_CICR1_PA_5 (0x0020UL << RI_CICR1_PA_Pos) /*!< 0x00000020 */ 6983 #define RI_CICR1_PA_6 (0x0040UL << RI_CICR1_PA_Pos) /*!< 0x00000040 */ 6984 #define RI_CICR1_PA_7 (0x0080UL << RI_CICR1_PA_Pos) /*!< 0x00000080 */ 6985 #define RI_CICR1_PA_8 (0x0100UL << RI_CICR1_PA_Pos) /*!< 0x00000100 */ 6986 #define RI_CICR1_PA_9 (0x0200UL << RI_CICR1_PA_Pos) /*!< 0x00000200 */ 6987 #define RI_CICR1_PA_10 (0x0400UL << RI_CICR1_PA_Pos) /*!< 0x00000400 */ 6988 #define RI_CICR1_PA_11 (0x0800UL << RI_CICR1_PA_Pos) /*!< 0x00000800 */ 6989 #define RI_CICR1_PA_12 (0x1000UL << RI_CICR1_PA_Pos) /*!< 0x00001000 */ 6990 #define RI_CICR1_PA_13 (0x2000UL << RI_CICR1_PA_Pos) /*!< 0x00002000 */ 6991 #define RI_CICR1_PA_14 (0x4000UL << RI_CICR1_PA_Pos) /*!< 0x00004000 */ 6992 #define RI_CICR1_PA_15 (0x8000UL << RI_CICR1_PA_Pos) /*!< 0x00008000 */ 6993 6994 /******************** Bit definition for RI_ASMR2 register ********************/ 6995 #define RI_ASMR2_PB_Pos (0U) 6996 #define RI_ASMR2_PB_Msk (0xFFFFUL << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */ 6997 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */ 6998 #define RI_ASMR2_PB_0 (0x0001UL << RI_ASMR2_PB_Pos) /*!< 0x00000001 */ 6999 #define RI_ASMR2_PB_1 (0x0002UL << RI_ASMR2_PB_Pos) /*!< 0x00000002 */ 7000 #define RI_ASMR2_PB_2 (0x0004UL << RI_ASMR2_PB_Pos) /*!< 0x00000004 */ 7001 #define RI_ASMR2_PB_3 (0x0008UL << RI_ASMR2_PB_Pos) /*!< 0x00000008 */ 7002 #define RI_ASMR2_PB_4 (0x0010UL << RI_ASMR2_PB_Pos) /*!< 0x00000010 */ 7003 #define RI_ASMR2_PB_5 (0x0020UL << RI_ASMR2_PB_Pos) /*!< 0x00000020 */ 7004 #define RI_ASMR2_PB_6 (0x0040UL << RI_ASMR2_PB_Pos) /*!< 0x00000040 */ 7005 #define RI_ASMR2_PB_7 (0x0080UL << RI_ASMR2_PB_Pos) /*!< 0x00000080 */ 7006 #define RI_ASMR2_PB_8 (0x0100UL << RI_ASMR2_PB_Pos) /*!< 0x00000100 */ 7007 #define RI_ASMR2_PB_9 (0x0200UL << RI_ASMR2_PB_Pos) /*!< 0x00000200 */ 7008 #define RI_ASMR2_PB_10 (0x0400UL << RI_ASMR2_PB_Pos) /*!< 0x00000400 */ 7009 #define RI_ASMR2_PB_11 (0x0800UL << RI_ASMR2_PB_Pos) /*!< 0x00000800 */ 7010 #define RI_ASMR2_PB_12 (0x1000UL << RI_ASMR2_PB_Pos) /*!< 0x00001000 */ 7011 #define RI_ASMR2_PB_13 (0x2000UL << RI_ASMR2_PB_Pos) /*!< 0x00002000 */ 7012 #define RI_ASMR2_PB_14 (0x4000UL << RI_ASMR2_PB_Pos) /*!< 0x00004000 */ 7013 #define RI_ASMR2_PB_15 (0x8000UL << RI_ASMR2_PB_Pos) /*!< 0x00008000 */ 7014 7015 /******************** Bit definition for RI_CMR2 register ********************/ 7016 #define RI_CMR2_PB_Pos (0U) 7017 #define RI_CMR2_PB_Msk (0xFFFFUL << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */ 7018 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */ 7019 #define RI_CMR2_PB_0 (0x0001UL << RI_CMR2_PB_Pos) /*!< 0x00000001 */ 7020 #define RI_CMR2_PB_1 (0x0002UL << RI_CMR2_PB_Pos) /*!< 0x00000002 */ 7021 #define RI_CMR2_PB_2 (0x0004UL << RI_CMR2_PB_Pos) /*!< 0x00000004 */ 7022 #define RI_CMR2_PB_3 (0x0008UL << RI_CMR2_PB_Pos) /*!< 0x00000008 */ 7023 #define RI_CMR2_PB_4 (0x0010UL << RI_CMR2_PB_Pos) /*!< 0x00000010 */ 7024 #define RI_CMR2_PB_5 (0x0020UL << RI_CMR2_PB_Pos) /*!< 0x00000020 */ 7025 #define RI_CMR2_PB_6 (0x0040UL << RI_CMR2_PB_Pos) /*!< 0x00000040 */ 7026 #define RI_CMR2_PB_7 (0x0080UL << RI_CMR2_PB_Pos) /*!< 0x00000080 */ 7027 #define RI_CMR2_PB_8 (0x0100UL << RI_CMR2_PB_Pos) /*!< 0x00000100 */ 7028 #define RI_CMR2_PB_9 (0x0200UL << RI_CMR2_PB_Pos) /*!< 0x00000200 */ 7029 #define RI_CMR2_PB_10 (0x0400UL << RI_CMR2_PB_Pos) /*!< 0x00000400 */ 7030 #define RI_CMR2_PB_11 (0x0800UL << RI_CMR2_PB_Pos) /*!< 0x00000800 */ 7031 #define RI_CMR2_PB_12 (0x1000UL << RI_CMR2_PB_Pos) /*!< 0x00001000 */ 7032 #define RI_CMR2_PB_13 (0x2000UL << RI_CMR2_PB_Pos) /*!< 0x00002000 */ 7033 #define RI_CMR2_PB_14 (0x4000UL << RI_CMR2_PB_Pos) /*!< 0x00004000 */ 7034 #define RI_CMR2_PB_15 (0x8000UL << RI_CMR2_PB_Pos) /*!< 0x00008000 */ 7035 7036 /******************** Bit definition for RI_CICR2 register ********************/ 7037 #define RI_CICR2_PB_Pos (0U) 7038 #define RI_CICR2_PB_Msk (0xFFFFUL << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */ 7039 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */ 7040 #define RI_CICR2_PB_0 (0x0001UL << RI_CICR2_PB_Pos) /*!< 0x00000001 */ 7041 #define RI_CICR2_PB_1 (0x0002UL << RI_CICR2_PB_Pos) /*!< 0x00000002 */ 7042 #define RI_CICR2_PB_2 (0x0004UL << RI_CICR2_PB_Pos) /*!< 0x00000004 */ 7043 #define RI_CICR2_PB_3 (0x0008UL << RI_CICR2_PB_Pos) /*!< 0x00000008 */ 7044 #define RI_CICR2_PB_4 (0x0010UL << RI_CICR2_PB_Pos) /*!< 0x00000010 */ 7045 #define RI_CICR2_PB_5 (0x0020UL << RI_CICR2_PB_Pos) /*!< 0x00000020 */ 7046 #define RI_CICR2_PB_6 (0x0040UL << RI_CICR2_PB_Pos) /*!< 0x00000040 */ 7047 #define RI_CICR2_PB_7 (0x0080UL << RI_CICR2_PB_Pos) /*!< 0x00000080 */ 7048 #define RI_CICR2_PB_8 (0x0100UL << RI_CICR2_PB_Pos) /*!< 0x00000100 */ 7049 #define RI_CICR2_PB_9 (0x0200UL << RI_CICR2_PB_Pos) /*!< 0x00000200 */ 7050 #define RI_CICR2_PB_10 (0x0400UL << RI_CICR2_PB_Pos) /*!< 0x00000400 */ 7051 #define RI_CICR2_PB_11 (0x0800UL << RI_CICR2_PB_Pos) /*!< 0x00000800 */ 7052 #define RI_CICR2_PB_12 (0x1000UL << RI_CICR2_PB_Pos) /*!< 0x00001000 */ 7053 #define RI_CICR2_PB_13 (0x2000UL << RI_CICR2_PB_Pos) /*!< 0x00002000 */ 7054 #define RI_CICR2_PB_14 (0x4000UL << RI_CICR2_PB_Pos) /*!< 0x00004000 */ 7055 #define RI_CICR2_PB_15 (0x8000UL << RI_CICR2_PB_Pos) /*!< 0x00008000 */ 7056 7057 /******************** Bit definition for RI_ASMR3 register ********************/ 7058 #define RI_ASMR3_PC_Pos (0U) 7059 #define RI_ASMR3_PC_Msk (0xFFFFUL << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */ 7060 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */ 7061 #define RI_ASMR3_PC_0 (0x0001UL << RI_ASMR3_PC_Pos) /*!< 0x00000001 */ 7062 #define RI_ASMR3_PC_1 (0x0002UL << RI_ASMR3_PC_Pos) /*!< 0x00000002 */ 7063 #define RI_ASMR3_PC_2 (0x0004UL << RI_ASMR3_PC_Pos) /*!< 0x00000004 */ 7064 #define RI_ASMR3_PC_3 (0x0008UL << RI_ASMR3_PC_Pos) /*!< 0x00000008 */ 7065 #define RI_ASMR3_PC_4 (0x0010UL << RI_ASMR3_PC_Pos) /*!< 0x00000010 */ 7066 #define RI_ASMR3_PC_5 (0x0020UL << RI_ASMR3_PC_Pos) /*!< 0x00000020 */ 7067 #define RI_ASMR3_PC_6 (0x0040UL << RI_ASMR3_PC_Pos) /*!< 0x00000040 */ 7068 #define RI_ASMR3_PC_7 (0x0080UL << RI_ASMR3_PC_Pos) /*!< 0x00000080 */ 7069 #define RI_ASMR3_PC_8 (0x0100UL << RI_ASMR3_PC_Pos) /*!< 0x00000100 */ 7070 #define RI_ASMR3_PC_9 (0x0200UL << RI_ASMR3_PC_Pos) /*!< 0x00000200 */ 7071 #define RI_ASMR3_PC_10 (0x0400UL << RI_ASMR3_PC_Pos) /*!< 0x00000400 */ 7072 #define RI_ASMR3_PC_11 (0x0800UL << RI_ASMR3_PC_Pos) /*!< 0x00000800 */ 7073 #define RI_ASMR3_PC_12 (0x1000UL << RI_ASMR3_PC_Pos) /*!< 0x00001000 */ 7074 #define RI_ASMR3_PC_13 (0x2000UL << RI_ASMR3_PC_Pos) /*!< 0x00002000 */ 7075 #define RI_ASMR3_PC_14 (0x4000UL << RI_ASMR3_PC_Pos) /*!< 0x00004000 */ 7076 #define RI_ASMR3_PC_15 (0x8000UL << RI_ASMR3_PC_Pos) /*!< 0x00008000 */ 7077 7078 /******************** Bit definition for RI_CMR3 register ********************/ 7079 #define RI_CMR3_PC_Pos (0U) 7080 #define RI_CMR3_PC_Msk (0xFFFFUL << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */ 7081 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */ 7082 #define RI_CMR3_PC_0 (0x0001UL << RI_CMR3_PC_Pos) /*!< 0x00000001 */ 7083 #define RI_CMR3_PC_1 (0x0002UL << RI_CMR3_PC_Pos) /*!< 0x00000002 */ 7084 #define RI_CMR3_PC_2 (0x0004UL << RI_CMR3_PC_Pos) /*!< 0x00000004 */ 7085 #define RI_CMR3_PC_3 (0x0008UL << RI_CMR3_PC_Pos) /*!< 0x00000008 */ 7086 #define RI_CMR3_PC_4 (0x0010UL << RI_CMR3_PC_Pos) /*!< 0x00000010 */ 7087 #define RI_CMR3_PC_5 (0x0020UL << RI_CMR3_PC_Pos) /*!< 0x00000020 */ 7088 #define RI_CMR3_PC_6 (0x0040UL << RI_CMR3_PC_Pos) /*!< 0x00000040 */ 7089 #define RI_CMR3_PC_7 (0x0080UL << RI_CMR3_PC_Pos) /*!< 0x00000080 */ 7090 #define RI_CMR3_PC_8 (0x0100UL << RI_CMR3_PC_Pos) /*!< 0x00000100 */ 7091 #define RI_CMR3_PC_9 (0x0200UL << RI_CMR3_PC_Pos) /*!< 0x00000200 */ 7092 #define RI_CMR3_PC_10 (0x0400UL << RI_CMR3_PC_Pos) /*!< 0x00000400 */ 7093 #define RI_CMR3_PC_11 (0x0800UL << RI_CMR3_PC_Pos) /*!< 0x00000800 */ 7094 #define RI_CMR3_PC_12 (0x1000UL << RI_CMR3_PC_Pos) /*!< 0x00001000 */ 7095 #define RI_CMR3_PC_13 (0x2000UL << RI_CMR3_PC_Pos) /*!< 0x00002000 */ 7096 #define RI_CMR3_PC_14 (0x4000UL << RI_CMR3_PC_Pos) /*!< 0x00004000 */ 7097 #define RI_CMR3_PC_15 (0x8000UL << RI_CMR3_PC_Pos) /*!< 0x00008000 */ 7098 7099 /******************** Bit definition for RI_CICR3 register ********************/ 7100 #define RI_CICR3_PC_Pos (0U) 7101 #define RI_CICR3_PC_Msk (0xFFFFUL << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */ 7102 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */ 7103 #define RI_CICR3_PC_0 (0x0001UL << RI_CICR3_PC_Pos) /*!< 0x00000001 */ 7104 #define RI_CICR3_PC_1 (0x0002UL << RI_CICR3_PC_Pos) /*!< 0x00000002 */ 7105 #define RI_CICR3_PC_2 (0x0004UL << RI_CICR3_PC_Pos) /*!< 0x00000004 */ 7106 #define RI_CICR3_PC_3 (0x0008UL << RI_CICR3_PC_Pos) /*!< 0x00000008 */ 7107 #define RI_CICR3_PC_4 (0x0010UL << RI_CICR3_PC_Pos) /*!< 0x00000010 */ 7108 #define RI_CICR3_PC_5 (0x0020UL << RI_CICR3_PC_Pos) /*!< 0x00000020 */ 7109 #define RI_CICR3_PC_6 (0x0040UL << RI_CICR3_PC_Pos) /*!< 0x00000040 */ 7110 #define RI_CICR3_PC_7 (0x0080UL << RI_CICR3_PC_Pos) /*!< 0x00000080 */ 7111 #define RI_CICR3_PC_8 (0x0100UL << RI_CICR3_PC_Pos) /*!< 0x00000100 */ 7112 #define RI_CICR3_PC_9 (0x0200UL << RI_CICR3_PC_Pos) /*!< 0x00000200 */ 7113 #define RI_CICR3_PC_10 (0x0400UL << RI_CICR3_PC_Pos) /*!< 0x00000400 */ 7114 #define RI_CICR3_PC_11 (0x0800UL << RI_CICR3_PC_Pos) /*!< 0x00000800 */ 7115 #define RI_CICR3_PC_12 (0x1000UL << RI_CICR3_PC_Pos) /*!< 0x00001000 */ 7116 #define RI_CICR3_PC_13 (0x2000UL << RI_CICR3_PC_Pos) /*!< 0x00002000 */ 7117 #define RI_CICR3_PC_14 (0x4000UL << RI_CICR3_PC_Pos) /*!< 0x00004000 */ 7118 #define RI_CICR3_PC_15 (0x8000UL << RI_CICR3_PC_Pos) /*!< 0x00008000 */ 7119 7120 /******************** Bit definition for RI_ASMR4 register ********************/ 7121 #define RI_ASMR4_PF_Pos (0U) 7122 #define RI_ASMR4_PF_Msk (0xFFFFUL << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ 7123 #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ 7124 #define RI_ASMR4_PF_0 (0x0001UL << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ 7125 #define RI_ASMR4_PF_1 (0x0002UL << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ 7126 #define RI_ASMR4_PF_2 (0x0004UL << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ 7127 #define RI_ASMR4_PF_3 (0x0008UL << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ 7128 #define RI_ASMR4_PF_4 (0x0010UL << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ 7129 #define RI_ASMR4_PF_5 (0x0020UL << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ 7130 #define RI_ASMR4_PF_6 (0x0040UL << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ 7131 #define RI_ASMR4_PF_7 (0x0080UL << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ 7132 #define RI_ASMR4_PF_8 (0x0100UL << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ 7133 #define RI_ASMR4_PF_9 (0x0200UL << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ 7134 #define RI_ASMR4_PF_10 (0x0400UL << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ 7135 #define RI_ASMR4_PF_11 (0x0800UL << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ 7136 #define RI_ASMR4_PF_12 (0x1000UL << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ 7137 #define RI_ASMR4_PF_13 (0x2000UL << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ 7138 #define RI_ASMR4_PF_14 (0x4000UL << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ 7139 #define RI_ASMR4_PF_15 (0x8000UL << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ 7140 7141 /******************** Bit definition for RI_CMR4 register ********************/ 7142 #define RI_CMR4_PF_Pos (0U) 7143 #define RI_CMR4_PF_Msk (0xFFFFUL << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ 7144 #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ 7145 #define RI_CMR4_PF_0 (0x0001UL << RI_CMR4_PF_Pos) /*!< 0x00000001 */ 7146 #define RI_CMR4_PF_1 (0x0002UL << RI_CMR4_PF_Pos) /*!< 0x00000002 */ 7147 #define RI_CMR4_PF_2 (0x0004UL << RI_CMR4_PF_Pos) /*!< 0x00000004 */ 7148 #define RI_CMR4_PF_3 (0x0008UL << RI_CMR4_PF_Pos) /*!< 0x00000008 */ 7149 #define RI_CMR4_PF_4 (0x0010UL << RI_CMR4_PF_Pos) /*!< 0x00000010 */ 7150 #define RI_CMR4_PF_5 (0x0020UL << RI_CMR4_PF_Pos) /*!< 0x00000020 */ 7151 #define RI_CMR4_PF_6 (0x0040UL << RI_CMR4_PF_Pos) /*!< 0x00000040 */ 7152 #define RI_CMR4_PF_7 (0x0080UL << RI_CMR4_PF_Pos) /*!< 0x00000080 */ 7153 #define RI_CMR4_PF_8 (0x0100UL << RI_CMR4_PF_Pos) /*!< 0x00000100 */ 7154 #define RI_CMR4_PF_9 (0x0200UL << RI_CMR4_PF_Pos) /*!< 0x00000200 */ 7155 #define RI_CMR4_PF_10 (0x0400UL << RI_CMR4_PF_Pos) /*!< 0x00000400 */ 7156 #define RI_CMR4_PF_11 (0x0800UL << RI_CMR4_PF_Pos) /*!< 0x00000800 */ 7157 #define RI_CMR4_PF_12 (0x1000UL << RI_CMR4_PF_Pos) /*!< 0x00001000 */ 7158 #define RI_CMR4_PF_13 (0x2000UL << RI_CMR4_PF_Pos) /*!< 0x00002000 */ 7159 #define RI_CMR4_PF_14 (0x4000UL << RI_CMR4_PF_Pos) /*!< 0x00004000 */ 7160 #define RI_CMR4_PF_15 (0x8000UL << RI_CMR4_PF_Pos) /*!< 0x00008000 */ 7161 7162 /******************** Bit definition for RI_CICR4 register ********************/ 7163 #define RI_CICR4_PF_Pos (0U) 7164 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ 7165 #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ 7166 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */ 7167 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */ 7168 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */ 7169 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */ 7170 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */ 7171 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */ 7172 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */ 7173 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */ 7174 #define RI_CICR4_PF_8 (0x0100UL << RI_CICR4_PF_Pos) /*!< 0x00000100 */ 7175 #define RI_CICR4_PF_9 (0x0200UL << RI_CICR4_PF_Pos) /*!< 0x00000200 */ 7176 #define RI_CICR4_PF_10 (0x0400UL << RI_CICR4_PF_Pos) /*!< 0x00000400 */ 7177 #define RI_CICR4_PF_11 (0x0800UL << RI_CICR4_PF_Pos) /*!< 0x00000800 */ 7178 #define RI_CICR4_PF_12 (0x1000UL << RI_CICR4_PF_Pos) /*!< 0x00001000 */ 7179 #define RI_CICR4_PF_13 (0x2000UL << RI_CICR4_PF_Pos) /*!< 0x00002000 */ 7180 #define RI_CICR4_PF_14 (0x4000UL << RI_CICR4_PF_Pos) /*!< 0x00004000 */ 7181 #define RI_CICR4_PF_15 (0x8000UL << RI_CICR4_PF_Pos) /*!< 0x00008000 */ 7182 7183 /******************** Bit definition for RI_ASMR5 register ********************/ 7184 #define RI_ASMR5_PG_Pos (0U) 7185 #define RI_ASMR5_PG_Msk (0xFFFFUL << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ 7186 #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ 7187 #define RI_ASMR5_PG_0 (0x0001UL << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ 7188 #define RI_ASMR5_PG_1 (0x0002UL << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ 7189 #define RI_ASMR5_PG_2 (0x0004UL << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ 7190 #define RI_ASMR5_PG_3 (0x0008UL << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ 7191 #define RI_ASMR5_PG_4 (0x0010UL << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ 7192 #define RI_ASMR5_PG_5 (0x0020UL << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ 7193 #define RI_ASMR5_PG_6 (0x0040UL << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ 7194 #define RI_ASMR5_PG_7 (0x0080UL << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ 7195 #define RI_ASMR5_PG_8 (0x0100UL << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ 7196 #define RI_ASMR5_PG_9 (0x0200UL << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ 7197 #define RI_ASMR5_PG_10 (0x0400UL << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ 7198 #define RI_ASMR5_PG_11 (0x0800UL << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ 7199 #define RI_ASMR5_PG_12 (0x1000UL << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ 7200 #define RI_ASMR5_PG_13 (0x2000UL << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ 7201 #define RI_ASMR5_PG_14 (0x4000UL << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ 7202 #define RI_ASMR5_PG_15 (0x8000UL << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ 7203 7204 /******************** Bit definition for RI_CMR5 register ********************/ 7205 #define RI_CMR5_PG_Pos (0U) 7206 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ 7207 #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ 7208 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */ 7209 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */ 7210 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */ 7211 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */ 7212 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */ 7213 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */ 7214 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */ 7215 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */ 7216 #define RI_CMR5_PG_8 (0x0100UL << RI_CMR5_PG_Pos) /*!< 0x00000100 */ 7217 #define RI_CMR5_PG_9 (0x0200UL << RI_CMR5_PG_Pos) /*!< 0x00000200 */ 7218 #define RI_CMR5_PG_10 (0x0400UL << RI_CMR5_PG_Pos) /*!< 0x00000400 */ 7219 #define RI_CMR5_PG_11 (0x0800UL << RI_CMR5_PG_Pos) /*!< 0x00000800 */ 7220 #define RI_CMR5_PG_12 (0x1000UL << RI_CMR5_PG_Pos) /*!< 0x00001000 */ 7221 #define RI_CMR5_PG_13 (0x2000UL << RI_CMR5_PG_Pos) /*!< 0x00002000 */ 7222 #define RI_CMR5_PG_14 (0x4000UL << RI_CMR5_PG_Pos) /*!< 0x00004000 */ 7223 #define RI_CMR5_PG_15 (0x8000UL << RI_CMR5_PG_Pos) /*!< 0x00008000 */ 7224 7225 /******************** Bit definition for RI_CICR5 register ********************/ 7226 #define RI_CICR5_PG_Pos (0U) 7227 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ 7228 #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ 7229 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */ 7230 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */ 7231 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */ 7232 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */ 7233 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */ 7234 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */ 7235 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */ 7236 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */ 7237 #define RI_CICR5_PG_8 (0x0100UL << RI_CICR5_PG_Pos) /*!< 0x00000100 */ 7238 #define RI_CICR5_PG_9 (0x0200UL << RI_CICR5_PG_Pos) /*!< 0x00000200 */ 7239 #define RI_CICR5_PG_10 (0x0400UL << RI_CICR5_PG_Pos) /*!< 0x00000400 */ 7240 #define RI_CICR5_PG_11 (0x0800UL << RI_CICR5_PG_Pos) /*!< 0x00000800 */ 7241 #define RI_CICR5_PG_12 (0x1000UL << RI_CICR5_PG_Pos) /*!< 0x00001000 */ 7242 #define RI_CICR5_PG_13 (0x2000UL << RI_CICR5_PG_Pos) /*!< 0x00002000 */ 7243 #define RI_CICR5_PG_14 (0x4000UL << RI_CICR5_PG_Pos) /*!< 0x00004000 */ 7244 #define RI_CICR5_PG_15 (0x8000UL << RI_CICR5_PG_Pos) /*!< 0x00008000 */ 7245 7246 /******************************************************************************/ 7247 /* */ 7248 /* Timers (TIM) */ 7249 /* */ 7250 /******************************************************************************/ 7251 7252 /******************* Bit definition for TIM_CR1 register ********************/ 7253 #define TIM_CR1_CEN_Pos (0U) 7254 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 7255 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 7256 #define TIM_CR1_UDIS_Pos (1U) 7257 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 7258 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 7259 #define TIM_CR1_URS_Pos (2U) 7260 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 7261 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 7262 #define TIM_CR1_OPM_Pos (3U) 7263 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 7264 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 7265 #define TIM_CR1_DIR_Pos (4U) 7266 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 7267 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 7268 7269 #define TIM_CR1_CMS_Pos (5U) 7270 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 7271 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 7272 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 7273 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 7274 7275 #define TIM_CR1_ARPE_Pos (7U) 7276 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 7277 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 7278 7279 #define TIM_CR1_CKD_Pos (8U) 7280 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 7281 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 7282 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 7283 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 7284 7285 /******************* Bit definition for TIM_CR2 register ********************/ 7286 #define TIM_CR2_CCDS_Pos (3U) 7287 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 7288 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 7289 7290 #define TIM_CR2_MMS_Pos (4U) 7291 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 7292 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 7293 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 7294 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 7295 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 7296 7297 #define TIM_CR2_TI1S_Pos (7U) 7298 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 7299 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 7300 7301 /******************* Bit definition for TIM_SMCR register *******************/ 7302 #define TIM_SMCR_SMS_Pos (0U) 7303 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 7304 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 7305 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 7306 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 7307 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 7308 7309 #define TIM_SMCR_OCCS_Pos (3U) 7310 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 7311 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 7312 7313 #define TIM_SMCR_TS_Pos (4U) 7314 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 7315 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 7316 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 7317 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 7318 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 7319 7320 #define TIM_SMCR_MSM_Pos (7U) 7321 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 7322 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 7323 7324 #define TIM_SMCR_ETF_Pos (8U) 7325 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 7326 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 7327 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 7328 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 7329 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 7330 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 7331 7332 #define TIM_SMCR_ETPS_Pos (12U) 7333 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 7334 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 7335 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 7336 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 7337 7338 #define TIM_SMCR_ECE_Pos (14U) 7339 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 7340 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 7341 #define TIM_SMCR_ETP_Pos (15U) 7342 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 7343 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 7344 7345 /******************* Bit definition for TIM_DIER register *******************/ 7346 #define TIM_DIER_UIE_Pos (0U) 7347 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 7348 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 7349 #define TIM_DIER_CC1IE_Pos (1U) 7350 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 7351 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 7352 #define TIM_DIER_CC2IE_Pos (2U) 7353 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 7354 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 7355 #define TIM_DIER_CC3IE_Pos (3U) 7356 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 7357 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 7358 #define TIM_DIER_CC4IE_Pos (4U) 7359 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 7360 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 7361 #define TIM_DIER_TIE_Pos (6U) 7362 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 7363 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 7364 #define TIM_DIER_UDE_Pos (8U) 7365 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 7366 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 7367 #define TIM_DIER_CC1DE_Pos (9U) 7368 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 7369 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 7370 #define TIM_DIER_CC2DE_Pos (10U) 7371 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 7372 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 7373 #define TIM_DIER_CC3DE_Pos (11U) 7374 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 7375 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 7376 #define TIM_DIER_CC4DE_Pos (12U) 7377 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 7378 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 7379 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */ 7380 #define TIM_DIER_TDE_Pos (14U) 7381 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 7382 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 7383 7384 /******************** Bit definition for TIM_SR register ********************/ 7385 #define TIM_SR_UIF_Pos (0U) 7386 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 7387 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 7388 #define TIM_SR_CC1IF_Pos (1U) 7389 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 7390 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 7391 #define TIM_SR_CC2IF_Pos (2U) 7392 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 7393 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 7394 #define TIM_SR_CC3IF_Pos (3U) 7395 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 7396 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 7397 #define TIM_SR_CC4IF_Pos (4U) 7398 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 7399 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 7400 #define TIM_SR_TIF_Pos (6U) 7401 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 7402 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 7403 #define TIM_SR_CC1OF_Pos (9U) 7404 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 7405 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 7406 #define TIM_SR_CC2OF_Pos (10U) 7407 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 7408 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 7409 #define TIM_SR_CC3OF_Pos (11U) 7410 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 7411 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 7412 #define TIM_SR_CC4OF_Pos (12U) 7413 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 7414 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 7415 7416 /******************* Bit definition for TIM_EGR register ********************/ 7417 #define TIM_EGR_UG_Pos (0U) 7418 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 7419 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 7420 #define TIM_EGR_CC1G_Pos (1U) 7421 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 7422 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 7423 #define TIM_EGR_CC2G_Pos (2U) 7424 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 7425 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 7426 #define TIM_EGR_CC3G_Pos (3U) 7427 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 7428 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 7429 #define TIM_EGR_CC4G_Pos (4U) 7430 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 7431 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 7432 #define TIM_EGR_TG_Pos (6U) 7433 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 7434 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 7435 7436 /****************** Bit definition for TIM_CCMR1 register *******************/ 7437 #define TIM_CCMR1_CC1S_Pos (0U) 7438 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 7439 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 7440 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 7441 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 7442 7443 #define TIM_CCMR1_OC1FE_Pos (2U) 7444 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 7445 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 7446 #define TIM_CCMR1_OC1PE_Pos (3U) 7447 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 7448 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 7449 7450 #define TIM_CCMR1_OC1M_Pos (4U) 7451 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 7452 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 7453 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 7454 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 7455 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 7456 7457 #define TIM_CCMR1_OC1CE_Pos (7U) 7458 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 7459 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 7460 7461 #define TIM_CCMR1_CC2S_Pos (8U) 7462 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 7463 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 7464 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 7465 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 7466 7467 #define TIM_CCMR1_OC2FE_Pos (10U) 7468 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 7469 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 7470 #define TIM_CCMR1_OC2PE_Pos (11U) 7471 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 7472 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 7473 7474 #define TIM_CCMR1_OC2M_Pos (12U) 7475 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 7476 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 7477 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 7478 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 7479 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 7480 7481 #define TIM_CCMR1_OC2CE_Pos (15U) 7482 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 7483 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 7484 7485 /*----------------------------------------------------------------------------*/ 7486 7487 #define TIM_CCMR1_IC1PSC_Pos (2U) 7488 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 7489 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 7490 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 7491 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 7492 7493 #define TIM_CCMR1_IC1F_Pos (4U) 7494 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 7495 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 7496 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 7497 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 7498 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 7499 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 7500 7501 #define TIM_CCMR1_IC2PSC_Pos (10U) 7502 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 7503 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 7504 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 7505 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 7506 7507 #define TIM_CCMR1_IC2F_Pos (12U) 7508 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 7509 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 7510 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 7511 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 7512 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 7513 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 7514 7515 /****************** Bit definition for TIM_CCMR2 register *******************/ 7516 #define TIM_CCMR2_CC3S_Pos (0U) 7517 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 7518 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 7519 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 7520 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 7521 7522 #define TIM_CCMR2_OC3FE_Pos (2U) 7523 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 7524 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 7525 #define TIM_CCMR2_OC3PE_Pos (3U) 7526 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 7527 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 7528 7529 #define TIM_CCMR2_OC3M_Pos (4U) 7530 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 7531 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 7532 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 7533 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 7534 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 7535 7536 #define TIM_CCMR2_OC3CE_Pos (7U) 7537 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 7538 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 7539 7540 #define TIM_CCMR2_CC4S_Pos (8U) 7541 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 7542 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 7543 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 7544 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 7545 7546 #define TIM_CCMR2_OC4FE_Pos (10U) 7547 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 7548 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 7549 #define TIM_CCMR2_OC4PE_Pos (11U) 7550 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 7551 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 7552 7553 #define TIM_CCMR2_OC4M_Pos (12U) 7554 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 7555 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 7556 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 7557 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 7558 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 7559 7560 #define TIM_CCMR2_OC4CE_Pos (15U) 7561 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 7562 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 7563 7564 /*----------------------------------------------------------------------------*/ 7565 7566 #define TIM_CCMR2_IC3PSC_Pos (2U) 7567 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 7568 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 7569 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 7570 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 7571 7572 #define TIM_CCMR2_IC3F_Pos (4U) 7573 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 7574 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 7575 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 7576 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 7577 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 7578 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 7579 7580 #define TIM_CCMR2_IC4PSC_Pos (10U) 7581 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 7582 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 7583 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 7584 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 7585 7586 #define TIM_CCMR2_IC4F_Pos (12U) 7587 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 7588 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 7589 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 7590 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 7591 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 7592 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 7593 7594 /******************* Bit definition for TIM_CCER register *******************/ 7595 #define TIM_CCER_CC1E_Pos (0U) 7596 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 7597 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 7598 #define TIM_CCER_CC1P_Pos (1U) 7599 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 7600 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 7601 #define TIM_CCER_CC1NP_Pos (3U) 7602 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 7603 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 7604 #define TIM_CCER_CC2E_Pos (4U) 7605 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 7606 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 7607 #define TIM_CCER_CC2P_Pos (5U) 7608 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 7609 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 7610 #define TIM_CCER_CC2NP_Pos (7U) 7611 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 7612 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 7613 #define TIM_CCER_CC3E_Pos (8U) 7614 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 7615 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 7616 #define TIM_CCER_CC3P_Pos (9U) 7617 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 7618 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 7619 #define TIM_CCER_CC3NP_Pos (11U) 7620 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 7621 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 7622 #define TIM_CCER_CC4E_Pos (12U) 7623 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 7624 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 7625 #define TIM_CCER_CC4P_Pos (13U) 7626 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 7627 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 7628 #define TIM_CCER_CC4NP_Pos (15U) 7629 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 7630 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 7631 7632 /******************* Bit definition for TIM_CNT register ********************/ 7633 #define TIM_CNT_CNT_Pos (0U) 7634 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 7635 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 7636 7637 /******************* Bit definition for TIM_PSC register ********************/ 7638 #define TIM_PSC_PSC_Pos (0U) 7639 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 7640 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 7641 7642 /******************* Bit definition for TIM_ARR register ********************/ 7643 #define TIM_ARR_ARR_Pos (0U) 7644 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 7645 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 7646 7647 /******************* Bit definition for TIM_CCR1 register *******************/ 7648 #define TIM_CCR1_CCR1_Pos (0U) 7649 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 7650 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 7651 7652 /******************* Bit definition for TIM_CCR2 register *******************/ 7653 #define TIM_CCR2_CCR2_Pos (0U) 7654 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 7655 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 7656 7657 /******************* Bit definition for TIM_CCR3 register *******************/ 7658 #define TIM_CCR3_CCR3_Pos (0U) 7659 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 7660 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 7661 7662 /******************* Bit definition for TIM_CCR4 register *******************/ 7663 #define TIM_CCR4_CCR4_Pos (0U) 7664 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 7665 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 7666 7667 /******************* Bit definition for TIM_DCR register ********************/ 7668 #define TIM_DCR_DBA_Pos (0U) 7669 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 7670 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 7671 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 7672 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 7673 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 7674 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 7675 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 7676 7677 #define TIM_DCR_DBL_Pos (8U) 7678 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 7679 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 7680 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 7681 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 7682 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 7683 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 7684 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 7685 7686 /******************* Bit definition for TIM_DMAR register *******************/ 7687 #define TIM_DMAR_DMAB_Pos (0U) 7688 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 7689 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 7690 7691 /******************* Bit definition for TIM_OR register *********************/ 7692 #define TIM_OR_TI1RMP_Pos (0U) 7693 #define TIM_OR_TI1RMP_Msk (0x3UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */ 7694 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */ 7695 #define TIM_OR_TI1RMP_0 (0x1UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */ 7696 #define TIM_OR_TI1RMP_1 (0x2UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */ 7697 7698 #define TIM_OR_ETR_RMP_Pos (2U) 7699 #define TIM_OR_ETR_RMP_Msk (0x1UL << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 7700 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/ 7701 #define TIM_OR_TI1_RMP_RI_Pos (3U) 7702 #define TIM_OR_TI1_RMP_RI_Msk (0x1UL << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */ 7703 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */ 7704 7705 /*----------------------------------------------------------------------------*/ 7706 #define TIM9_OR_ITR1_RMP_Pos (2U) 7707 #define TIM9_OR_ITR1_RMP_Msk (0x1UL << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */ 7708 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */ 7709 7710 /*----------------------------------------------------------------------------*/ 7711 #define TIM2_OR_ITR1_RMP_Pos (0U) 7712 #define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ 7713 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */ 7714 7715 /*----------------------------------------------------------------------------*/ 7716 #define TIM3_OR_ITR2_RMP_Pos (0U) 7717 #define TIM3_OR_ITR2_RMP_Msk (0x1UL << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */ 7718 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */ 7719 7720 /*----------------------------------------------------------------------------*/ 7721 7722 /******************************************************************************/ 7723 /* */ 7724 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 7725 /* */ 7726 /******************************************************************************/ 7727 7728 /******************* Bit definition for USART_SR register *******************/ 7729 #define USART_SR_PE_Pos (0U) 7730 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 7731 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 7732 #define USART_SR_FE_Pos (1U) 7733 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 7734 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 7735 #define USART_SR_NE_Pos (2U) 7736 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 7737 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 7738 #define USART_SR_ORE_Pos (3U) 7739 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 7740 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 7741 #define USART_SR_IDLE_Pos (4U) 7742 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 7743 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 7744 #define USART_SR_RXNE_Pos (5U) 7745 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 7746 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 7747 #define USART_SR_TC_Pos (6U) 7748 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 7749 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 7750 #define USART_SR_TXE_Pos (7U) 7751 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 7752 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 7753 #define USART_SR_LBD_Pos (8U) 7754 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 7755 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 7756 #define USART_SR_CTS_Pos (9U) 7757 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 7758 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 7759 7760 /******************* Bit definition for USART_DR register *******************/ 7761 #define USART_DR_DR_Pos (0U) 7762 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 7763 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 7764 7765 /****************** Bit definition for USART_BRR register *******************/ 7766 #define USART_BRR_DIV_Fraction_Pos (0U) 7767 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 7768 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */ 7769 #define USART_BRR_DIV_Mantissa_Pos (4U) 7770 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 7771 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */ 7772 7773 /* Legacy aliases */ 7774 #define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos 7775 #define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk 7776 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction 7777 7778 #define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos 7779 #define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk 7780 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa 7781 7782 /****************** Bit definition for USART_CR1 register *******************/ 7783 #define USART_CR1_SBK_Pos (0U) 7784 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 7785 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 7786 #define USART_CR1_RWU_Pos (1U) 7787 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 7788 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 7789 #define USART_CR1_RE_Pos (2U) 7790 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 7791 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 7792 #define USART_CR1_TE_Pos (3U) 7793 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 7794 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 7795 #define USART_CR1_IDLEIE_Pos (4U) 7796 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 7797 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 7798 #define USART_CR1_RXNEIE_Pos (5U) 7799 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 7800 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 7801 #define USART_CR1_TCIE_Pos (6U) 7802 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 7803 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 7804 #define USART_CR1_TXEIE_Pos (7U) 7805 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 7806 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 7807 #define USART_CR1_PEIE_Pos (8U) 7808 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 7809 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 7810 #define USART_CR1_PS_Pos (9U) 7811 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 7812 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 7813 #define USART_CR1_PCE_Pos (10U) 7814 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 7815 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 7816 #define USART_CR1_WAKE_Pos (11U) 7817 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 7818 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 7819 #define USART_CR1_M_Pos (12U) 7820 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 7821 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 7822 #define USART_CR1_UE_Pos (13U) 7823 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 7824 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 7825 #define USART_CR1_OVER8_Pos (15U) 7826 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 7827 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */ 7828 7829 /****************** Bit definition for USART_CR2 register *******************/ 7830 #define USART_CR2_ADD_Pos (0U) 7831 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 7832 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 7833 #define USART_CR2_LBDL_Pos (5U) 7834 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 7835 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 7836 #define USART_CR2_LBDIE_Pos (6U) 7837 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 7838 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 7839 #define USART_CR2_LBCL_Pos (8U) 7840 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 7841 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 7842 #define USART_CR2_CPHA_Pos (9U) 7843 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 7844 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 7845 #define USART_CR2_CPOL_Pos (10U) 7846 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 7847 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 7848 #define USART_CR2_CLKEN_Pos (11U) 7849 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 7850 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 7851 7852 #define USART_CR2_STOP_Pos (12U) 7853 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 7854 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 7855 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 7856 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 7857 7858 #define USART_CR2_LINEN_Pos (14U) 7859 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 7860 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 7861 7862 /****************** Bit definition for USART_CR3 register *******************/ 7863 #define USART_CR3_EIE_Pos (0U) 7864 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 7865 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 7866 #define USART_CR3_IREN_Pos (1U) 7867 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 7868 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 7869 #define USART_CR3_IRLP_Pos (2U) 7870 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 7871 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 7872 #define USART_CR3_HDSEL_Pos (3U) 7873 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 7874 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 7875 #define USART_CR3_NACK_Pos (4U) 7876 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 7877 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 7878 #define USART_CR3_SCEN_Pos (5U) 7879 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 7880 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 7881 #define USART_CR3_DMAR_Pos (6U) 7882 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 7883 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 7884 #define USART_CR3_DMAT_Pos (7U) 7885 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 7886 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 7887 #define USART_CR3_RTSE_Pos (8U) 7888 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 7889 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 7890 #define USART_CR3_CTSE_Pos (9U) 7891 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 7892 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 7893 #define USART_CR3_CTSIE_Pos (10U) 7894 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 7895 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 7896 #define USART_CR3_ONEBIT_Pos (11U) 7897 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 7898 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 7899 7900 /****************** Bit definition for USART_GTPR register ******************/ 7901 #define USART_GTPR_PSC_Pos (0U) 7902 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 7903 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 7904 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 7905 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 7906 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 7907 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 7908 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 7909 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 7910 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 7911 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 7912 7913 #define USART_GTPR_GT_Pos (8U) 7914 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 7915 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 7916 7917 /******************************************************************************/ 7918 /* */ 7919 /* Universal Serial Bus (USB) */ 7920 /* */ 7921 /******************************************************************************/ 7922 7923 /*!<Endpoint-specific registers */ 7924 7925 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 7926 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */ 7927 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */ 7928 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */ 7929 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */ 7930 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */ 7931 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */ 7932 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */ 7933 7934 /* bit positions */ 7935 #define USB_EP_CTR_RX_Pos (15U) 7936 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 7937 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 7938 #define USB_EP_DTOG_RX_Pos (14U) 7939 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 7940 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 7941 #define USB_EPRX_STAT_Pos (12U) 7942 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 7943 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 7944 #define USB_EP_SETUP_Pos (11U) 7945 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 7946 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 7947 #define USB_EP_T_FIELD_Pos (9U) 7948 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 7949 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 7950 #define USB_EP_KIND_Pos (8U) 7951 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ 7952 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 7953 #define USB_EP_CTR_TX_Pos (7U) 7954 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 7955 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 7956 #define USB_EP_DTOG_TX_Pos (6U) 7957 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 7958 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 7959 #define USB_EPTX_STAT_Pos (4U) 7960 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 7961 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 7962 #define USB_EPADDR_FIELD_Pos (0U) 7963 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 7964 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 7965 7966 /* EndPoint REGister MASK (no toggle fields) */ 7967 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 7968 /*!< EP_TYPE[1:0] EndPoint TYPE */ 7969 #define USB_EP_TYPE_MASK_Pos (9U) 7970 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 7971 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 7972 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */ 7973 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */ 7974 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */ 7975 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */ 7976 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 7977 7978 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 7979 /*!< STAT_TX[1:0] STATus for TX transfer */ 7980 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */ 7981 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */ 7982 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */ 7983 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */ 7984 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */ 7985 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */ 7986 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 7987 /*!< STAT_RX[1:0] STATus for RX transfer */ 7988 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */ 7989 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */ 7990 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */ 7991 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */ 7992 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */ 7993 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */ 7994 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 7995 7996 /******************* Bit definition for USB_EP0R register *******************/ 7997 #define USB_EP0R_EA_Pos (0U) 7998 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 7999 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */ 8000 8001 #define USB_EP0R_STAT_TX_Pos (4U) 8002 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 8003 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8004 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 8005 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 8006 8007 #define USB_EP0R_DTOG_TX_Pos (6U) 8008 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 8009 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8010 #define USB_EP0R_CTR_TX_Pos (7U) 8011 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 8012 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8013 #define USB_EP0R_EP_KIND_Pos (8U) 8014 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 8015 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */ 8016 8017 #define USB_EP0R_EP_TYPE_Pos (9U) 8018 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 8019 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8020 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 8021 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 8022 8023 #define USB_EP0R_SETUP_Pos (11U) 8024 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 8025 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */ 8026 8027 #define USB_EP0R_STAT_RX_Pos (12U) 8028 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 8029 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8030 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 8031 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 8032 8033 #define USB_EP0R_DTOG_RX_Pos (14U) 8034 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 8035 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8036 #define USB_EP0R_CTR_RX_Pos (15U) 8037 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 8038 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8039 8040 /******************* Bit definition for USB_EP1R register *******************/ 8041 #define USB_EP1R_EA_Pos (0U) 8042 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 8043 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */ 8044 8045 #define USB_EP1R_STAT_TX_Pos (4U) 8046 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 8047 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8048 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 8049 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 8050 8051 #define USB_EP1R_DTOG_TX_Pos (6U) 8052 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 8053 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8054 #define USB_EP1R_CTR_TX_Pos (7U) 8055 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 8056 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8057 #define USB_EP1R_EP_KIND_Pos (8U) 8058 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 8059 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */ 8060 8061 #define USB_EP1R_EP_TYPE_Pos (9U) 8062 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 8063 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8064 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 8065 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 8066 8067 #define USB_EP1R_SETUP_Pos (11U) 8068 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 8069 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */ 8070 8071 #define USB_EP1R_STAT_RX_Pos (12U) 8072 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 8073 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8074 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 8075 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 8076 8077 #define USB_EP1R_DTOG_RX_Pos (14U) 8078 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 8079 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8080 #define USB_EP1R_CTR_RX_Pos (15U) 8081 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 8082 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8083 8084 /******************* Bit definition for USB_EP2R register *******************/ 8085 #define USB_EP2R_EA_Pos (0U) 8086 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 8087 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */ 8088 8089 #define USB_EP2R_STAT_TX_Pos (4U) 8090 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 8091 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8092 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 8093 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 8094 8095 #define USB_EP2R_DTOG_TX_Pos (6U) 8096 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 8097 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8098 #define USB_EP2R_CTR_TX_Pos (7U) 8099 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 8100 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8101 #define USB_EP2R_EP_KIND_Pos (8U) 8102 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 8103 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */ 8104 8105 #define USB_EP2R_EP_TYPE_Pos (9U) 8106 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 8107 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8108 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 8109 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 8110 8111 #define USB_EP2R_SETUP_Pos (11U) 8112 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 8113 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */ 8114 8115 #define USB_EP2R_STAT_RX_Pos (12U) 8116 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 8117 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8118 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 8119 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 8120 8121 #define USB_EP2R_DTOG_RX_Pos (14U) 8122 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 8123 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8124 #define USB_EP2R_CTR_RX_Pos (15U) 8125 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 8126 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8127 8128 /******************* Bit definition for USB_EP3R register *******************/ 8129 #define USB_EP3R_EA_Pos (0U) 8130 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 8131 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */ 8132 8133 #define USB_EP3R_STAT_TX_Pos (4U) 8134 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 8135 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8136 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 8137 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 8138 8139 #define USB_EP3R_DTOG_TX_Pos (6U) 8140 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 8141 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8142 #define USB_EP3R_CTR_TX_Pos (7U) 8143 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 8144 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8145 #define USB_EP3R_EP_KIND_Pos (8U) 8146 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 8147 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */ 8148 8149 #define USB_EP3R_EP_TYPE_Pos (9U) 8150 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 8151 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8152 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 8153 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 8154 8155 #define USB_EP3R_SETUP_Pos (11U) 8156 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 8157 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */ 8158 8159 #define USB_EP3R_STAT_RX_Pos (12U) 8160 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 8161 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8162 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 8163 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 8164 8165 #define USB_EP3R_DTOG_RX_Pos (14U) 8166 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 8167 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8168 #define USB_EP3R_CTR_RX_Pos (15U) 8169 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 8170 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8171 8172 /******************* Bit definition for USB_EP4R register *******************/ 8173 #define USB_EP4R_EA_Pos (0U) 8174 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 8175 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */ 8176 8177 #define USB_EP4R_STAT_TX_Pos (4U) 8178 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 8179 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8180 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 8181 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 8182 8183 #define USB_EP4R_DTOG_TX_Pos (6U) 8184 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 8185 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8186 #define USB_EP4R_CTR_TX_Pos (7U) 8187 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 8188 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8189 #define USB_EP4R_EP_KIND_Pos (8U) 8190 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 8191 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */ 8192 8193 #define USB_EP4R_EP_TYPE_Pos (9U) 8194 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 8195 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8196 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 8197 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 8198 8199 #define USB_EP4R_SETUP_Pos (11U) 8200 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 8201 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */ 8202 8203 #define USB_EP4R_STAT_RX_Pos (12U) 8204 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 8205 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8206 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 8207 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 8208 8209 #define USB_EP4R_DTOG_RX_Pos (14U) 8210 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 8211 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8212 #define USB_EP4R_CTR_RX_Pos (15U) 8213 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 8214 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8215 8216 /******************* Bit definition for USB_EP5R register *******************/ 8217 #define USB_EP5R_EA_Pos (0U) 8218 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 8219 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */ 8220 8221 #define USB_EP5R_STAT_TX_Pos (4U) 8222 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 8223 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8224 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 8225 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 8226 8227 #define USB_EP5R_DTOG_TX_Pos (6U) 8228 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 8229 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8230 #define USB_EP5R_CTR_TX_Pos (7U) 8231 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 8232 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8233 #define USB_EP5R_EP_KIND_Pos (8U) 8234 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 8235 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */ 8236 8237 #define USB_EP5R_EP_TYPE_Pos (9U) 8238 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 8239 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8240 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 8241 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 8242 8243 #define USB_EP5R_SETUP_Pos (11U) 8244 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 8245 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */ 8246 8247 #define USB_EP5R_STAT_RX_Pos (12U) 8248 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 8249 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8250 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 8251 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 8252 8253 #define USB_EP5R_DTOG_RX_Pos (14U) 8254 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 8255 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8256 #define USB_EP5R_CTR_RX_Pos (15U) 8257 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 8258 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8259 8260 /******************* Bit definition for USB_EP6R register *******************/ 8261 #define USB_EP6R_EA_Pos (0U) 8262 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 8263 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */ 8264 8265 #define USB_EP6R_STAT_TX_Pos (4U) 8266 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 8267 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8268 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 8269 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 8270 8271 #define USB_EP6R_DTOG_TX_Pos (6U) 8272 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 8273 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8274 #define USB_EP6R_CTR_TX_Pos (7U) 8275 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 8276 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8277 #define USB_EP6R_EP_KIND_Pos (8U) 8278 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 8279 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */ 8280 8281 #define USB_EP6R_EP_TYPE_Pos (9U) 8282 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 8283 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8284 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 8285 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 8286 8287 #define USB_EP6R_SETUP_Pos (11U) 8288 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 8289 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */ 8290 8291 #define USB_EP6R_STAT_RX_Pos (12U) 8292 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 8293 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8294 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 8295 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 8296 8297 #define USB_EP6R_DTOG_RX_Pos (14U) 8298 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 8299 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8300 #define USB_EP6R_CTR_RX_Pos (15U) 8301 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 8302 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8303 8304 /******************* Bit definition for USB_EP7R register *******************/ 8305 #define USB_EP7R_EA_Pos (0U) 8306 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 8307 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */ 8308 8309 #define USB_EP7R_STAT_TX_Pos (4U) 8310 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 8311 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8312 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 8313 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 8314 8315 #define USB_EP7R_DTOG_TX_Pos (6U) 8316 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 8317 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8318 #define USB_EP7R_CTR_TX_Pos (7U) 8319 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 8320 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8321 #define USB_EP7R_EP_KIND_Pos (8U) 8322 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 8323 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */ 8324 8325 #define USB_EP7R_EP_TYPE_Pos (9U) 8326 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 8327 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8328 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 8329 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 8330 8331 #define USB_EP7R_SETUP_Pos (11U) 8332 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 8333 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */ 8334 8335 #define USB_EP7R_STAT_RX_Pos (12U) 8336 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 8337 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8338 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 8339 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 8340 8341 #define USB_EP7R_DTOG_RX_Pos (14U) 8342 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 8343 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8344 #define USB_EP7R_CTR_RX_Pos (15U) 8345 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 8346 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8347 8348 /*!<Common registers */ 8349 8350 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ 8351 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ 8352 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ 8353 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ 8354 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ 8355 8356 8357 8358 /******************* Bit definition for USB_CNTR register *******************/ 8359 #define USB_CNTR_FRES_Pos (0U) 8360 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 8361 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */ 8362 #define USB_CNTR_PDWN_Pos (1U) 8363 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 8364 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */ 8365 #define USB_CNTR_LPMODE_Pos (2U) 8366 #define USB_CNTR_LPMODE_Msk (0x1UL << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */ 8367 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */ 8368 #define USB_CNTR_FSUSP_Pos (3U) 8369 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 8370 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */ 8371 #define USB_CNTR_RESUME_Pos (4U) 8372 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 8373 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */ 8374 #define USB_CNTR_ESOFM_Pos (8U) 8375 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 8376 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */ 8377 #define USB_CNTR_SOFM_Pos (9U) 8378 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 8379 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */ 8380 #define USB_CNTR_RESETM_Pos (10U) 8381 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 8382 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */ 8383 #define USB_CNTR_SUSPM_Pos (11U) 8384 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 8385 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */ 8386 #define USB_CNTR_WKUPM_Pos (12U) 8387 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 8388 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */ 8389 #define USB_CNTR_ERRM_Pos (13U) 8390 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 8391 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */ 8392 #define USB_CNTR_PMAOVRM_Pos (14U) 8393 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 8394 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */ 8395 #define USB_CNTR_CTRM_Pos (15U) 8396 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 8397 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */ 8398 8399 /******************* Bit definition for USB_ISTR register *******************/ 8400 #define USB_ISTR_EP_ID_Pos (0U) 8401 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 8402 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */ 8403 #define USB_ISTR_DIR_Pos (4U) 8404 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 8405 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */ 8406 #define USB_ISTR_ESOF_Pos (8U) 8407 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 8408 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */ 8409 #define USB_ISTR_SOF_Pos (9U) 8410 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 8411 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */ 8412 #define USB_ISTR_RESET_Pos (10U) 8413 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 8414 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */ 8415 #define USB_ISTR_SUSP_Pos (11U) 8416 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 8417 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */ 8418 #define USB_ISTR_WKUP_Pos (12U) 8419 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 8420 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */ 8421 #define USB_ISTR_ERR_Pos (13U) 8422 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 8423 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */ 8424 #define USB_ISTR_PMAOVR_Pos (14U) 8425 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 8426 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */ 8427 #define USB_ISTR_CTR_Pos (15U) 8428 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 8429 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */ 8430 8431 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 8432 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 8433 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 8434 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 8435 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 8436 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 8437 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 8438 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 8439 8440 8441 /******************* Bit definition for USB_FNR register ********************/ 8442 #define USB_FNR_FN_Pos (0U) 8443 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ 8444 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */ 8445 #define USB_FNR_LSOF_Pos (11U) 8446 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 8447 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */ 8448 #define USB_FNR_LCK_Pos (13U) 8449 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 8450 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */ 8451 #define USB_FNR_RXDM_Pos (14U) 8452 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 8453 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */ 8454 #define USB_FNR_RXDP_Pos (15U) 8455 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 8456 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */ 8457 8458 /****************** Bit definition for USB_DADDR register *******************/ 8459 #define USB_DADDR_ADD_Pos (0U) 8460 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 8461 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */ 8462 #define USB_DADDR_ADD0_Pos (0U) 8463 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 8464 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */ 8465 #define USB_DADDR_ADD1_Pos (1U) 8466 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 8467 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */ 8468 #define USB_DADDR_ADD2_Pos (2U) 8469 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 8470 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */ 8471 #define USB_DADDR_ADD3_Pos (3U) 8472 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 8473 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */ 8474 #define USB_DADDR_ADD4_Pos (4U) 8475 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 8476 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */ 8477 #define USB_DADDR_ADD5_Pos (5U) 8478 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 8479 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */ 8480 #define USB_DADDR_ADD6_Pos (6U) 8481 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 8482 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */ 8483 8484 #define USB_DADDR_EF_Pos (7U) 8485 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 8486 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */ 8487 8488 /****************** Bit definition for USB_BTABLE register ******************/ 8489 #define USB_BTABLE_BTABLE_Pos (3U) 8490 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 8491 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */ 8492 8493 /*!< Buffer descriptor table */ 8494 /***************** Bit definition for USB_ADDR0_TX register *****************/ 8495 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 8496 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 8497 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 8498 8499 /***************** Bit definition for USB_ADDR1_TX register *****************/ 8500 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 8501 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 8502 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 8503 8504 /***************** Bit definition for USB_ADDR2_TX register *****************/ 8505 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 8506 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 8507 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 8508 8509 /***************** Bit definition for USB_ADDR3_TX register *****************/ 8510 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 8511 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 8512 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 8513 8514 /***************** Bit definition for USB_ADDR4_TX register *****************/ 8515 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 8516 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 8517 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 8518 8519 /***************** Bit definition for USB_ADDR5_TX register *****************/ 8520 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 8521 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 8522 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 8523 8524 /***************** Bit definition for USB_ADDR6_TX register *****************/ 8525 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 8526 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 8527 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 8528 8529 /***************** Bit definition for USB_ADDR7_TX register *****************/ 8530 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 8531 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 8532 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 8533 8534 /*----------------------------------------------------------------------------*/ 8535 8536 /***************** Bit definition for USB_COUNT0_TX register ****************/ 8537 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 8538 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 8539 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 8540 8541 /***************** Bit definition for USB_COUNT1_TX register ****************/ 8542 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 8543 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 8544 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 8545 8546 /***************** Bit definition for USB_COUNT2_TX register ****************/ 8547 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 8548 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 8549 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 8550 8551 /***************** Bit definition for USB_COUNT3_TX register ****************/ 8552 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 8553 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 8554 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 8555 8556 /***************** Bit definition for USB_COUNT4_TX register ****************/ 8557 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 8558 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 8559 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 8560 8561 /***************** Bit definition for USB_COUNT5_TX register ****************/ 8562 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 8563 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 8564 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 8565 8566 /***************** Bit definition for USB_COUNT6_TX register ****************/ 8567 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 8568 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 8569 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 8570 8571 /***************** Bit definition for USB_COUNT7_TX register ****************/ 8572 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 8573 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 8574 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 8575 8576 /*----------------------------------------------------------------------------*/ 8577 8578 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 8579 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ 8580 8581 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 8582 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ 8583 8584 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 8585 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ 8586 8587 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 8588 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ 8589 8590 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 8591 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ 8592 8593 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 8594 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ 8595 8596 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 8597 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */ 8598 8599 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 8600 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */ 8601 8602 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 8603 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ 8604 8605 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 8606 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ 8607 8608 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 8609 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ 8610 8611 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 8612 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ 8613 8614 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 8615 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ 8616 8617 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 8618 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ 8619 8620 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 8621 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ 8622 8623 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 8624 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ 8625 8626 /*----------------------------------------------------------------------------*/ 8627 8628 /***************** Bit definition for USB_ADDR0_RX register *****************/ 8629 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 8630 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 8631 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 8632 8633 /***************** Bit definition for USB_ADDR1_RX register *****************/ 8634 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 8635 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 8636 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 8637 8638 /***************** Bit definition for USB_ADDR2_RX register *****************/ 8639 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 8640 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 8641 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 8642 8643 /***************** Bit definition for USB_ADDR3_RX register *****************/ 8644 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 8645 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 8646 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 8647 8648 /***************** Bit definition for USB_ADDR4_RX register *****************/ 8649 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 8650 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 8651 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 8652 8653 /***************** Bit definition for USB_ADDR5_RX register *****************/ 8654 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 8655 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 8656 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 8657 8658 /***************** Bit definition for USB_ADDR6_RX register *****************/ 8659 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 8660 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 8661 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 8662 8663 /***************** Bit definition for USB_ADDR7_RX register *****************/ 8664 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 8665 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 8666 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 8667 8668 /*----------------------------------------------------------------------------*/ 8669 8670 /***************** Bit definition for USB_COUNT0_RX register ****************/ 8671 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 8672 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 8673 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 8674 8675 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 8676 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8677 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8678 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8679 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8680 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8681 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8682 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8683 8684 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 8685 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8686 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 8687 8688 /***************** Bit definition for USB_COUNT1_RX register ****************/ 8689 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 8690 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 8691 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 8692 8693 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 8694 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8695 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8696 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8697 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8698 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8699 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8700 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8701 8702 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 8703 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8704 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 8705 8706 /***************** Bit definition for USB_COUNT2_RX register ****************/ 8707 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 8708 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 8709 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 8710 8711 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 8712 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8713 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8714 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8715 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8716 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8717 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8718 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8719 8720 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 8721 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8722 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 8723 8724 /***************** Bit definition for USB_COUNT3_RX register ****************/ 8725 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 8726 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 8727 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 8728 8729 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 8730 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8731 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8732 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8733 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8734 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8735 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8736 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8737 8738 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 8739 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8740 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 8741 8742 /***************** Bit definition for USB_COUNT4_RX register ****************/ 8743 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 8744 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 8745 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 8746 8747 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 8748 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8749 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8750 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8751 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8752 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8753 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8754 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8755 8756 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 8757 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8758 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 8759 8760 /***************** Bit definition for USB_COUNT5_RX register ****************/ 8761 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 8762 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 8763 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 8764 8765 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 8766 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8767 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8768 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8769 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8770 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8771 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8772 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8773 8774 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 8775 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8776 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 8777 8778 /***************** Bit definition for USB_COUNT6_RX register ****************/ 8779 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 8780 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 8781 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 8782 8783 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 8784 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8785 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8786 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8787 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8788 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8789 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8790 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8791 8792 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 8793 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8794 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 8795 8796 /***************** Bit definition for USB_COUNT7_RX register ****************/ 8797 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 8798 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 8799 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 8800 8801 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 8802 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8803 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8804 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8805 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8806 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8807 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8808 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8809 8810 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 8811 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8812 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 8813 8814 /*----------------------------------------------------------------------------*/ 8815 8816 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 8817 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8818 8819 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8820 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8821 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8822 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8823 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8824 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8825 8826 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8827 8828 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 8829 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8830 8831 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8832 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ 8833 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8834 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8835 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8836 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8837 8838 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8839 8840 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 8841 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8842 8843 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8844 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8845 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8846 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8847 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8848 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8849 8850 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8851 8852 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 8853 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8854 8855 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8856 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8857 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8858 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8859 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8860 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8861 8862 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8863 8864 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 8865 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8866 8867 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8868 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8869 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8870 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8871 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8872 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8873 8874 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8875 8876 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 8877 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8878 8879 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8880 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8881 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8882 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8883 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8884 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8885 8886 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8887 8888 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 8889 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8890 8891 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8892 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8893 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8894 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8895 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8896 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8897 8898 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8899 8900 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 8901 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8902 8903 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8904 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8905 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8906 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8907 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8908 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8909 8910 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8911 8912 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 8913 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8914 8915 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8916 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8917 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8918 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8919 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8920 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8921 8922 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8923 8924 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 8925 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8926 8927 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8928 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8929 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8930 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8931 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8932 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8933 8934 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8935 8936 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 8937 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8938 8939 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8940 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8941 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8942 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8943 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8944 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8945 8946 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8947 8948 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 8949 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8950 8951 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8952 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8953 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8954 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8955 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8956 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8957 8958 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8959 8960 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 8961 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8962 8963 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8964 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8965 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8966 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8967 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8968 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8969 8970 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8971 8972 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 8973 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8974 8975 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8976 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8977 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8978 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8979 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8980 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8981 8982 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8983 8984 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 8985 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8986 8987 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8988 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8989 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8990 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8991 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8992 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8993 8994 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8995 8996 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 8997 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8998 8999 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9000 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9001 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9002 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9003 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9004 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9005 9006 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9007 9008 /******************************************************************************/ 9009 /* */ 9010 /* Window WATCHDOG (WWDG) */ 9011 /* */ 9012 /******************************************************************************/ 9013 9014 /******************* Bit definition for WWDG_CR register ********************/ 9015 #define WWDG_CR_T_Pos (0U) 9016 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 9017 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 9018 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 9019 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 9020 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 9021 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 9022 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 9023 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 9024 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 9025 9026 /* Legacy defines */ 9027 #define WWDG_CR_T0 WWDG_CR_T_0 9028 #define WWDG_CR_T1 WWDG_CR_T_1 9029 #define WWDG_CR_T2 WWDG_CR_T_2 9030 #define WWDG_CR_T3 WWDG_CR_T_3 9031 #define WWDG_CR_T4 WWDG_CR_T_4 9032 #define WWDG_CR_T5 WWDG_CR_T_5 9033 #define WWDG_CR_T6 WWDG_CR_T_6 9034 9035 #define WWDG_CR_WDGA_Pos (7U) 9036 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 9037 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 9038 9039 /******************* Bit definition for WWDG_CFR register *******************/ 9040 #define WWDG_CFR_W_Pos (0U) 9041 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 9042 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 9043 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 9044 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 9045 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 9046 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 9047 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 9048 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 9049 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 9050 9051 /* Legacy defines */ 9052 #define WWDG_CFR_W0 WWDG_CFR_W_0 9053 #define WWDG_CFR_W1 WWDG_CFR_W_1 9054 #define WWDG_CFR_W2 WWDG_CFR_W_2 9055 #define WWDG_CFR_W3 WWDG_CFR_W_3 9056 #define WWDG_CFR_W4 WWDG_CFR_W_4 9057 #define WWDG_CFR_W5 WWDG_CFR_W_5 9058 #define WWDG_CFR_W6 WWDG_CFR_W_6 9059 9060 #define WWDG_CFR_WDGTB_Pos (7U) 9061 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 9062 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 9063 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 9064 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 9065 9066 /* Legacy defines */ 9067 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 9068 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 9069 9070 #define WWDG_CFR_EWI_Pos (9U) 9071 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 9072 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 9073 9074 /******************* Bit definition for WWDG_SR register ********************/ 9075 #define WWDG_SR_EWIF_Pos (0U) 9076 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 9077 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 9078 9079 /** 9080 * @} 9081 */ 9082 /** @addtogroup Exported_macro 9083 * @{ 9084 */ 9085 9086 /****************************** ADC Instances *********************************/ 9087 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 9088 9089 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 9090 9091 /******************************** COMP Instances ******************************/ 9092 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 9093 ((INSTANCE) == COMP2)) 9094 9095 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 9096 9097 /****************************** CRC Instances *********************************/ 9098 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 9099 9100 /****************************** DAC Instances *********************************/ 9101 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) 9102 9103 /****************************** DMA Instances *********************************/ 9104 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 9105 ((INSTANCE) == DMA1_Channel2) || \ 9106 ((INSTANCE) == DMA1_Channel3) || \ 9107 ((INSTANCE) == DMA1_Channel4) || \ 9108 ((INSTANCE) == DMA1_Channel5) || \ 9109 ((INSTANCE) == DMA1_Channel6) || \ 9110 ((INSTANCE) == DMA1_Channel7) || \ 9111 ((INSTANCE) == DMA2_Channel1) || \ 9112 ((INSTANCE) == DMA2_Channel2) || \ 9113 ((INSTANCE) == DMA2_Channel3) || \ 9114 ((INSTANCE) == DMA2_Channel4) || \ 9115 ((INSTANCE) == DMA2_Channel5)) 9116 9117 /******************************* GPIO Instances *******************************/ 9118 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 9119 ((INSTANCE) == GPIOB) || \ 9120 ((INSTANCE) == GPIOC) || \ 9121 ((INSTANCE) == GPIOD) || \ 9122 ((INSTANCE) == GPIOE) || \ 9123 ((INSTANCE) == GPIOF) || \ 9124 ((INSTANCE) == GPIOG) || \ 9125 ((INSTANCE) == GPIOH)) 9126 9127 /**************************** GPIO Alternate Function Instances ***************/ 9128 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9129 9130 /**************************** GPIO Lock Instances *****************************/ 9131 /* On L1, all GPIO Bank support the Lock mechanism */ 9132 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9133 9134 /******************************** I2C Instances *******************************/ 9135 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 9136 ((INSTANCE) == I2C2)) 9137 9138 /****************************** SMBUS Instances *******************************/ 9139 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 9140 9141 /******************************** I2S Instances *******************************/ 9142 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 9143 ((INSTANCE) == SPI3)) 9144 /****************************** IWDG Instances ********************************/ 9145 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 9146 9147 /****************************** OPAMP Instances *******************************/ 9148 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ 9149 ((INSTANCE) == OPAMP2) || \ 9150 ((INSTANCE) == OPAMP3)) 9151 9152 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON) 9153 9154 /****************************** RTC Instances *********************************/ 9155 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 9156 9157 /****************************** SDIO Instances *********************************/ 9158 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) 9159 9160 /******************************** SPI Instances *******************************/ 9161 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 9162 ((INSTANCE) == SPI2) || \ 9163 ((INSTANCE) == SPI3)) 9164 9165 /****************************** TIM Instances *********************************/ 9166 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9167 ((INSTANCE) == TIM3) || \ 9168 ((INSTANCE) == TIM4) || \ 9169 ((INSTANCE) == TIM5) || \ 9170 ((INSTANCE) == TIM6) || \ 9171 ((INSTANCE) == TIM7) || \ 9172 ((INSTANCE) == TIM9) || \ 9173 ((INSTANCE) == TIM10) || \ 9174 ((INSTANCE) == TIM11)) 9175 9176 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9177 ((INSTANCE) == TIM3) || \ 9178 ((INSTANCE) == TIM4) || \ 9179 ((INSTANCE) == TIM5) || \ 9180 ((INSTANCE) == TIM9) || \ 9181 ((INSTANCE) == TIM10) || \ 9182 ((INSTANCE) == TIM11)) 9183 9184 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9185 ((INSTANCE) == TIM3) || \ 9186 ((INSTANCE) == TIM4) || \ 9187 ((INSTANCE) == TIM5) || \ 9188 ((INSTANCE) == TIM9)) 9189 9190 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9191 ((INSTANCE) == TIM3) || \ 9192 ((INSTANCE) == TIM4) || \ 9193 ((INSTANCE) == TIM5)) 9194 9195 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9196 ((INSTANCE) == TIM3) || \ 9197 ((INSTANCE) == TIM4) || \ 9198 ((INSTANCE) == TIM5)) 9199 9200 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9201 ((INSTANCE) == TIM3) || \ 9202 ((INSTANCE) == TIM4) || \ 9203 ((INSTANCE) == TIM5) || \ 9204 ((INSTANCE) == TIM9)) 9205 9206 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9207 ((INSTANCE) == TIM3) || \ 9208 ((INSTANCE) == TIM4) || \ 9209 ((INSTANCE) == TIM5) || \ 9210 ((INSTANCE) == TIM9) || \ 9211 ((INSTANCE) == TIM10) || \ 9212 ((INSTANCE) == TIM11)) 9213 9214 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9215 ((INSTANCE) == TIM3) || \ 9216 ((INSTANCE) == TIM4) || \ 9217 ((INSTANCE) == TIM5) || \ 9218 ((INSTANCE) == TIM9)) 9219 9220 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9221 ((INSTANCE) == TIM3) || \ 9222 ((INSTANCE) == TIM4) || \ 9223 ((INSTANCE) == TIM5) || \ 9224 ((INSTANCE) == TIM9)) 9225 9226 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9227 ((INSTANCE) == TIM3) || \ 9228 ((INSTANCE) == TIM4)) 9229 9230 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9231 ((INSTANCE) == TIM3) || \ 9232 ((INSTANCE) == TIM4) || \ 9233 ((INSTANCE) == TIM5)) 9234 9235 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9236 ((INSTANCE) == TIM3) || \ 9237 ((INSTANCE) == TIM4) || \ 9238 ((INSTANCE) == TIM5) || \ 9239 ((INSTANCE) == TIM9)) 9240 9241 9242 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9243 ((INSTANCE) == TIM3) || \ 9244 ((INSTANCE) == TIM4) || \ 9245 ((INSTANCE) == TIM5) || \ 9246 ((INSTANCE) == TIM6) || \ 9247 ((INSTANCE) == TIM7) || \ 9248 ((INSTANCE) == TIM9)) 9249 9250 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9251 ((INSTANCE) == TIM3) || \ 9252 ((INSTANCE) == TIM4) || \ 9253 ((INSTANCE) == TIM9)) 9254 9255 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5) 9256 9257 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9258 ((INSTANCE) == TIM3) || \ 9259 ((INSTANCE) == TIM4) || \ 9260 ((INSTANCE) == TIM5)) 9261 9262 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 9263 ((((INSTANCE) == TIM2) && \ 9264 (((CHANNEL) == TIM_CHANNEL_1) || \ 9265 ((CHANNEL) == TIM_CHANNEL_2) || \ 9266 ((CHANNEL) == TIM_CHANNEL_3) || \ 9267 ((CHANNEL) == TIM_CHANNEL_4))) \ 9268 || \ 9269 (((INSTANCE) == TIM3) && \ 9270 (((CHANNEL) == TIM_CHANNEL_1) || \ 9271 ((CHANNEL) == TIM_CHANNEL_2) || \ 9272 ((CHANNEL) == TIM_CHANNEL_3) || \ 9273 ((CHANNEL) == TIM_CHANNEL_4))) \ 9274 || \ 9275 (((INSTANCE) == TIM4) && \ 9276 (((CHANNEL) == TIM_CHANNEL_1) || \ 9277 ((CHANNEL) == TIM_CHANNEL_2) || \ 9278 ((CHANNEL) == TIM_CHANNEL_3) || \ 9279 ((CHANNEL) == TIM_CHANNEL_4))) \ 9280 || \ 9281 (((INSTANCE) == TIM5) && \ 9282 (((CHANNEL) == TIM_CHANNEL_1) || \ 9283 ((CHANNEL) == TIM_CHANNEL_2) || \ 9284 ((CHANNEL) == TIM_CHANNEL_3) || \ 9285 ((CHANNEL) == TIM_CHANNEL_4))) \ 9286 || \ 9287 (((INSTANCE) == TIM9) && \ 9288 (((CHANNEL) == TIM_CHANNEL_1) || \ 9289 ((CHANNEL) == TIM_CHANNEL_2))) \ 9290 || \ 9291 (((INSTANCE) == TIM10) && \ 9292 (((CHANNEL) == TIM_CHANNEL_1))) \ 9293 || \ 9294 (((INSTANCE) == TIM11) && \ 9295 (((CHANNEL) == TIM_CHANNEL_1)))) 9296 9297 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9298 ((INSTANCE) == TIM3) || \ 9299 ((INSTANCE) == TIM4) || \ 9300 ((INSTANCE) == TIM5) || \ 9301 ((INSTANCE) == TIM9) || \ 9302 ((INSTANCE) == TIM10) || \ 9303 ((INSTANCE) == TIM11)) 9304 9305 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9306 ((INSTANCE) == TIM3) || \ 9307 ((INSTANCE) == TIM4) || \ 9308 ((INSTANCE) == TIM5) || \ 9309 ((INSTANCE) == TIM6) || \ 9310 ((INSTANCE) == TIM7)) 9311 9312 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9313 ((INSTANCE) == TIM3) || \ 9314 ((INSTANCE) == TIM4) || \ 9315 ((INSTANCE) == TIM5)) 9316 9317 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9318 ((INSTANCE) == TIM3) || \ 9319 ((INSTANCE) == TIM4) || \ 9320 ((INSTANCE) == TIM5) || \ 9321 ((INSTANCE) == TIM9)) 9322 9323 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9324 ((INSTANCE) == TIM3) || \ 9325 ((INSTANCE) == TIM4) || \ 9326 ((INSTANCE) == TIM5) || \ 9327 ((INSTANCE) == TIM9)) 9328 9329 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9330 ((INSTANCE) == TIM3) || \ 9331 ((INSTANCE) == TIM9) || \ 9332 ((INSTANCE) == TIM10) || \ 9333 ((INSTANCE) == TIM11)) 9334 9335 /******************** USART Instances : Synchronous mode **********************/ 9336 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9337 ((INSTANCE) == USART2) || \ 9338 ((INSTANCE) == USART3)) 9339 9340 /******************** UART Instances : Asynchronous mode **********************/ 9341 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9342 ((INSTANCE) == USART2) || \ 9343 ((INSTANCE) == USART3) || \ 9344 ((INSTANCE) == UART4) || \ 9345 ((INSTANCE) == UART5)) 9346 9347 /******************** UART Instances : Half-Duplex mode **********************/ 9348 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9349 ((INSTANCE) == USART2) || \ 9350 ((INSTANCE) == USART3) || \ 9351 ((INSTANCE) == UART4) || \ 9352 ((INSTANCE) == UART5)) 9353 9354 /******************** UART Instances : LIN mode **********************/ 9355 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9356 ((INSTANCE) == USART2) || \ 9357 ((INSTANCE) == USART3) || \ 9358 ((INSTANCE) == UART4) || \ 9359 ((INSTANCE) == UART5)) 9360 9361 /****************** UART Instances : Hardware Flow control ********************/ 9362 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9363 ((INSTANCE) == USART2) || \ 9364 ((INSTANCE) == USART3)) 9365 9366 /********************* UART Instances : Smard card mode ***********************/ 9367 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9368 ((INSTANCE) == USART2) || \ 9369 ((INSTANCE) == USART3)) 9370 9371 /*********************** UART Instances : IRDA mode ***************************/ 9372 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9373 ((INSTANCE) == USART2) || \ 9374 ((INSTANCE) == USART3) || \ 9375 ((INSTANCE) == UART4) || \ 9376 ((INSTANCE) == UART5)) 9377 9378 /***************** UART Instances : Multi-Processor mode **********************/ 9379 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9380 ((INSTANCE) == USART2) || \ 9381 ((INSTANCE) == USART3) || \ 9382 ((INSTANCE) == UART4) || \ 9383 ((INSTANCE) == UART5)) 9384 9385 /****************************** WWDG Instances ********************************/ 9386 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 9387 9388 /****************************** USB Instances ********************************/ 9389 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 9390 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE 9391 9392 /** 9393 * @} 9394 */ 9395 9396 /******************************************************************************/ 9397 /* For a painless codes migration between the STM32L1xx device product */ 9398 /* lines, the aliases defined below are put in place to overcome the */ 9399 /* differences in the interrupt handlers and IRQn definitions. */ 9400 /* No need to update developed interrupt code when moving across */ 9401 /* product lines within the same STM32L1 Family */ 9402 /******************************************************************************/ 9403 9404 /* Aliases for __IRQn */ 9405 9406 /* Aliases for __IRQHandler */ 9407 9408 /** 9409 * @} 9410 */ 9411 9412 /** 9413 * @} 9414 */ 9415 9416 #ifdef __cplusplus 9417 } 9418 #endif /* __cplusplus */ 9419 9420 #endif /* __STM32L151xD_H */ 9421 9422 9423 9424
