1 /**
2 ******************************************************************************
3 * @file system_stm32l1xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l1xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 ******************************************************************************
22 * @attention
23 *
24 * Copyright (c) 2017-2021 STMicroelectronics.
25 * All rights reserved.
26 *
27 * This software is licensed under terms that can be found in the LICENSE file
28 * in the root directory of this software component.
29 * If no LICENSE file comes with this software, it is provided AS-IS.
30 *
31 ******************************************************************************
32 */
33
34 /** @addtogroup CMSIS
35 * @{
36 */
37
38 /** @addtogroup stm32l1xx_system
39 * @{
40 */
41
42 /** @addtogroup STM32L1xx_System_Private_Includes
43 * @{
44 */
45
46 #include "stm32l1xx.h"
47
48 /**
49 * @}
50 */
51
52 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
53 * @{
54 */
55
56 /**
57 * @}
58 */
59
60 /** @addtogroup STM32L1xx_System_Private_Defines
61 * @{
62 */
63 #if !defined (HSE_VALUE)
64 #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
65 This value can be provided and adapted by the user application. */
66 #endif /* HSE_VALUE */
67
68 #if !defined (HSI_VALUE)
69 #define HSI_VALUE ((uint32_t)16000000U) /*!< Default value of the Internal oscillator in Hz.
70 This value can be provided and adapted by the user application. */
71 #endif /* HSI_VALUE */
72
73 /*!< Uncomment the following line if you need to use external SRAM mounted
74 on STM32L152D_EVAL board as data memory */
75 /* #define DATA_IN_ExtSRAM */
76
77 /* Note: Following vector table addresses must be defined in line with linker
78 configuration. */
79 /*!< Uncomment the following line if you need to relocate the vector table
80 anywhere in Flash or Sram, else the vector table is kept at the automatic
81 remap of boot address selected */
82 /* #define USER_VECT_TAB_ADDRESS */
83
84 #if defined(USER_VECT_TAB_ADDRESS)
85 /*!< Uncomment the following line if you need to relocate your vector Table
86 in Sram else user remap will be done in Flash. */
87 /* #define VECT_TAB_SRAM */
88 #if defined(VECT_TAB_SRAM)
89 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
90 This value must be a multiple of 0x200. */
91 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
92 This value must be a multiple of 0x200. */
93 #else
94 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
95 This value must be a multiple of 0x200. */
96 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
97 This value must be a multiple of 0x200. */
98 #endif /* VECT_TAB_SRAM */
99 #endif /* USER_VECT_TAB_ADDRESS */
100
101 /******************************************************************************/
102 /**
103 * @}
104 */
105
106 /** @addtogroup STM32L1xx_System_Private_Macros
107 * @{
108 */
109
110 /**
111 * @}
112 */
113
114 /** @addtogroup STM32L1xx_System_Private_Variables
115 * @{
116 */
117 /* This variable is updated in three ways:
118 1) by calling CMSIS function SystemCoreClockUpdate()
119 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
120 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
121 Note: If you use this function to configure the system clock; then there
122 is no need to call the 2 first functions listed above, since SystemCoreClock
123 variable is updated automatically.
124 */
125 uint32_t SystemCoreClock = 2097000U;
126 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
127 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
128 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
129
130 /**
131 * @}
132 */
133
134 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
135 * @{
136 */
137
138 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
139 #ifdef DATA_IN_ExtSRAM
140 static void SystemInit_ExtMemCtl(void);
141 #endif /* DATA_IN_ExtSRAM */
142 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
143
144 /**
145 * @}
146 */
147
148 /** @addtogroup STM32L1xx_System_Private_Functions
149 * @{
150 */
151
152 /**
153 * @brief Setup the microcontroller system.
154 * Initialize the Embedded Flash Interface, the PLL and update the
155 * SystemCoreClock variable.
156 * @param None
157 * @retval None
158 */
SystemInit(void)159 void SystemInit (void)
160 {
161 #ifdef DATA_IN_ExtSRAM
162 SystemInit_ExtMemCtl();
163 #endif /* DATA_IN_ExtSRAM */
164
165 /* Configure the Vector Table location -------------------------------------*/
166 #if defined(USER_VECT_TAB_ADDRESS)
167 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
168 #endif /* USER_VECT_TAB_ADDRESS */
169 }
170
171 /**
172 * @brief Update SystemCoreClock according to Clock Register Values
173 * The SystemCoreClock variable contains the core clock (HCLK), it can
174 * be used by the user application to setup the SysTick timer or configure
175 * other parameters.
176 *
177 * @note Each time the core clock (HCLK) changes, this function must be called
178 * to update SystemCoreClock variable value. Otherwise, any configuration
179 * based on this variable will be incorrect.
180 *
181 * @note - The system frequency computed by this function is not the real
182 * frequency in the chip. It is calculated based on the predefined
183 * constant and the selected clock source:
184 *
185 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
186 * value as defined by the MSI range.
187 *
188 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
189 *
190 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
191 *
192 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
193 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
194 *
195 * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
196 * 16 MHz) but the real value may vary depending on the variations
197 * in voltage and temperature.
198 *
199 * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
200 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
201 * frequency of the crystal used. Otherwise, this function may
202 * have wrong result.
203 *
204 * - The result of this function could be not correct when using fractional
205 * value for HSE crystal.
206 * @param None
207 * @retval None
208 */
SystemCoreClockUpdate(void)209 void SystemCoreClockUpdate (void)
210 {
211 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
212
213 /* Get SYSCLK source -------------------------------------------------------*/
214 tmp = RCC->CFGR & RCC_CFGR_SWS;
215
216 switch (tmp)
217 {
218 case 0x00: /* MSI used as system clock */
219 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
220 SystemCoreClock = (32768 * (1 << (msirange + 1)));
221 break;
222 case 0x04: /* HSI used as system clock */
223 SystemCoreClock = HSI_VALUE;
224 break;
225 case 0x08: /* HSE used as system clock */
226 SystemCoreClock = HSE_VALUE;
227 break;
228 case 0x0C: /* PLL used as system clock */
229 /* Get PLL clock source and multiplication factor ----------------------*/
230 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
231 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
232 pllmul = PLLMulTable[(pllmul >> 18)];
233 plldiv = (plldiv >> 22) + 1;
234
235 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
236
237 if (pllsource == 0x00)
238 {
239 /* HSI oscillator clock selected as PLL clock entry */
240 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
241 }
242 else
243 {
244 /* HSE selected as PLL clock entry */
245 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
246 }
247 break;
248 default: /* MSI used as system clock */
249 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
250 SystemCoreClock = (32768 * (1 << (msirange + 1)));
251 break;
252 }
253 /* Compute HCLK clock frequency --------------------------------------------*/
254 /* Get HCLK prescaler */
255 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
256 /* HCLK clock frequency */
257 SystemCoreClock >>= tmp;
258 }
259
260 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
261 #ifdef DATA_IN_ExtSRAM
262 /**
263 * @brief Setup the external memory controller.
264 * Called in SystemInit() function before jump to main.
265 * This function configures the external SRAM mounted on STM32L152D_EVAL board
266 * This SRAM will be used as program data memory (including heap and stack).
267 * @param None
268 * @retval None
269 */
SystemInit_ExtMemCtl(void)270 void SystemInit_ExtMemCtl(void)
271 {
272 __IO uint32_t tmpreg = 0;
273
274 /* Flash 1 wait state */
275 FLASH->ACR |= FLASH_ACR_LATENCY;
276
277 /* Power enable */
278 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
279
280 /* Delay after an RCC peripheral clock enabling */
281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
282
283 /* Select the Voltage Range 1 (1.8 V) */
284 PWR->CR = PWR_CR_VOS_0;
285
286 /* Wait Until the Voltage Regulator is ready */
287 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
288 {
289 }
290
291 /*-- GPIOs Configuration -----------------------------------------------------*/
292 /*
293 +-------------------+--------------------+------------------+------------------+
294 + SRAM pins assignment +
295 +-------------------+--------------------+------------------+------------------+
296 | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
297 | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
298 | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
299 | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
300 | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
301 | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
302 | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
303 | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
304 | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
305 | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
306 | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
307 | PD15 <-> FSMC_D1 |--------------------+
308 +-------------------+
309 */
310
311 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
312 RCC->AHBENR = 0x000080D8;
313
314 /* Delay after an RCC peripheral clock enabling */
315 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
316
317 /* Connect PDx pins to FSMC Alternate function */
318 GPIOD->AFR[0] = 0x00CC00CC;
319 GPIOD->AFR[1] = 0xCCCCCCCC;
320 /* Configure PDx pins in Alternate function mode */
321 GPIOD->MODER = 0xAAAA0A0A;
322 /* Configure PDx pins speed to 40 MHz */
323 GPIOD->OSPEEDR = 0xFFFF0F0F;
324 /* Configure PDx pins Output type to push-pull */
325 GPIOD->OTYPER = 0x00000000;
326 /* No pull-up, pull-down for PDx pins */
327 GPIOD->PUPDR = 0x00000000;
328
329 /* Connect PEx pins to FSMC Alternate function */
330 GPIOE->AFR[0] = 0xC00000CC;
331 GPIOE->AFR[1] = 0xCCCCCCCC;
332 /* Configure PEx pins in Alternate function mode */
333 GPIOE->MODER = 0xAAAA800A;
334 /* Configure PEx pins speed to 40 MHz */
335 GPIOE->OSPEEDR = 0xFFFFC00F;
336 /* Configure PEx pins Output type to push-pull */
337 GPIOE->OTYPER = 0x00000000;
338 /* No pull-up, pull-down for PEx pins */
339 GPIOE->PUPDR = 0x00000000;
340
341 /* Connect PFx pins to FSMC Alternate function */
342 GPIOF->AFR[0] = 0x00CCCCCC;
343 GPIOF->AFR[1] = 0xCCCC0000;
344 /* Configure PFx pins in Alternate function mode */
345 GPIOF->MODER = 0xAA000AAA;
346 /* Configure PFx pins speed to 40 MHz */
347 GPIOF->OSPEEDR = 0xFF000FFF;
348 /* Configure PFx pins Output type to push-pull */
349 GPIOF->OTYPER = 0x00000000;
350 /* No pull-up, pull-down for PFx pins */
351 GPIOF->PUPDR = 0x00000000;
352
353 /* Connect PGx pins to FSMC Alternate function */
354 GPIOG->AFR[0] = 0x00CCCCCC;
355 GPIOG->AFR[1] = 0x00000C00;
356 /* Configure PGx pins in Alternate function mode */
357 GPIOG->MODER = 0x00200AAA;
358 /* Configure PGx pins speed to 40 MHz */
359 GPIOG->OSPEEDR = 0x00300FFF;
360 /* Configure PGx pins Output type to push-pull */
361 GPIOG->OTYPER = 0x00000000;
362 /* No pull-up, pull-down for PGx pins */
363 GPIOG->PUPDR = 0x00000000;
364
365 /*-- FSMC Configuration ------------------------------------------------------*/
366 /* Enable the FSMC interface clock */
367 RCC->AHBENR = 0x400080D8;
368
369 /* Delay after an RCC peripheral clock enabling */
370 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
371
372 (void)(tmpreg);
373
374 /* Configure and enable Bank1_SRAM3 */
375 FSMC_Bank1->BTCR[4] = 0x00001011;
376 FSMC_Bank1->BTCR[5] = 0x00000300;
377 FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
378 /*
379 Bank1_SRAM3 is configured as follow:
380
381 p.FSMC_AddressSetupTime = 0;
382 p.FSMC_AddressHoldTime = 0;
383 p.FSMC_DataSetupTime = 3;
384 p.FSMC_BusTurnAroundDuration = 0;
385 p.FSMC_CLKDivision = 0;
386 p.FSMC_DataLatency = 0;
387 p.FSMC_AccessMode = FSMC_AccessMode_A;
388
389 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
390 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
391 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
392 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
393 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
394 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
395 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
396 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
397 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
398 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
399 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
400 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
401 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
402 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
403 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
404
405 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
406
407 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
408 */
409
410 }
411 #endif /* DATA_IN_ExtSRAM */
412 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
413
414 /**
415 * @}
416 */
417
418 /**
419 * @}
420 */
421
422 /**
423 * @}
424 */
425
426
