1 /**
2   ******************************************************************************
3   * @file    stm32l162xd.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32L1xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2017-2021 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS
28   * @{
29   */
30 
31 /** @addtogroup stm32l162xd
32   * @{
33   */
34 
35 #ifndef __STM32L162xD_H
36 #define __STM32L162xD_H
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
42 
43   /** @addtogroup Configuration_section_for_CMSIS
44   * @{
45   */
46 /**
47   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
48  */
49 #define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
50 #define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
51 #define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
52 #define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32L1xx Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 
67  /*!< Interrupt Number Definition */
68 typedef enum
69 {
70 /******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
71   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
72   HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
73   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
74   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
75   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
76   SVCall_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
77   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
78   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
79   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
80 
81 /******  STM32L specific Interrupt Numbers ***********************************************************/
82   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
83   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
84   TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
85   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
86   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
87   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
88   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
89   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
90   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
91   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
92   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
93   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
94   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
95   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
96   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
97   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
98   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
99   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
100   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
101   USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
102   USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
103   DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
104   COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
105   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
106   LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
107   TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
108   TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
109   TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
110   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
111   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
112   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
113   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
114   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
115   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
116   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
117   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
118   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
119   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
120   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
121   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
122   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
123   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
124   USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
125   TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
126   TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
127   SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
128   TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
129   SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
130   UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
131   UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
132   DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
133   DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
134   DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
135   DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
136   DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
137   AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
138   COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
139 } IRQn_Type;
140 
141 /**
142   * @}
143   */
144 
145 #include "core_cm3.h"
146 #include "system_stm32l1xx.h"
147 #include <stdint.h>
148 
149 /** @addtogroup Peripheral_registers_structures
150   * @{
151   */
152 
153 /**
154   * @brief Analog to Digital Converter
155   */
156 
157 typedef struct
158 {
159   __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
160   __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
161   __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
162   __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
163   __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
164   __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
165   __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
166   __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
167   __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
168   __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
169   __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
170   __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
171   __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
172   __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
173   __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
174   __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
175   __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
176   __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
177   __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
178   __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
179   __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
180   __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
181   __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
182   __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
183 } ADC_TypeDef;
184 
185 typedef struct
186 {
187   __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
188   __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
189 } ADC_Common_TypeDef;
190 
191 /**
192   * @brief AES hardware accelerator
193   */
194 
195 typedef struct
196 {
197   __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
198   __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
199   __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
200   __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
201   __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
202   __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
203   __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
204   __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
205   __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
206   __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
207   __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
208   __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
209 } AES_TypeDef;
210 
211 /**
212   * @brief Comparator
213   */
214 
215 typedef struct
216 {
217   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
218 } COMP_TypeDef;
219 
220 typedef struct
221 {
222   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
223 } COMP_Common_TypeDef;
224 
225 /**
226   * @brief CRC calculation unit
227   */
228 
229 typedef struct
230 {
231   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
232   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
233   uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
234   uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
235   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
236 } CRC_TypeDef;
237 
238 /**
239   * @brief Digital to Analog Converter
240   */
241 
242 typedef struct
243 {
244   __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
245   __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
246   __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
247   __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
248   __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
249   __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
250   __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
251   __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
252   __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
253   __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
254   __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
255   __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
256   __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
257   __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
258 } DAC_TypeDef;
259 
260 /**
261   * @brief Debug MCU
262   */
263 
264 typedef struct
265 {
266   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
267   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
268   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
269   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
270 }DBGMCU_TypeDef;
271 
272 /**
273   * @brief DMA Controller
274   */
275 
276 typedef struct
277 {
278   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
279   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
280   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
281   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
282 } DMA_Channel_TypeDef;
283 
284 typedef struct
285 {
286   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
287   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
288 } DMA_TypeDef;
289 
290 /**
291   * @brief External Interrupt/Event Controller
292   */
293 
294 typedef struct
295 {
296   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
297   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
298   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
299   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
300   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
301   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
302 } EXTI_TypeDef;
303 
304 /**
305   * @brief FLASH Registers
306   */
307 typedef struct
308 {
309   __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
310   __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
311   __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
312   __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
313   __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
314   __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
315   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
316   __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
317   __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
318   uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
319   __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
320   __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
321 } FLASH_TypeDef;
322 
323 /**
324   * @brief Option Bytes Registers
325   */
326 typedef struct
327 {
328   __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
329   __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
330   __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
331   __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
332   __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
333   __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
334   __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
335   __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
336 } OB_TypeDef;
337 
338 /**
339   * @brief Operational Amplifier (OPAMP)
340   */
341 typedef struct
342 {
343   __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
344   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
345   __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
346 } OPAMP_TypeDef;
347 
348 typedef struct
349 {
350   __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
351   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
352 } OPAMP_Common_TypeDef;
353 
354 /**
355   * @brief Flexible Static Memory Controller
356   */
357 
358 typedef struct
359 {
360   __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
361 } FSMC_Bank1_TypeDef;
362 
363 /**
364   * @brief Flexible Static Memory Controller Bank1E
365   */
366 
367 typedef struct
368 {
369   __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
370 } FSMC_Bank1E_TypeDef;
371 
372 /**
373   * @brief General Purpose IO
374   */
375 
376 typedef struct
377 {
378   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
379   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
380   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
381   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
382   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
383   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
384   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
385   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
386   __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
387   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
388 } GPIO_TypeDef;
389 
390 /**
391   * @brief SysTem Configuration
392   */
393 
394 typedef struct
395 {
396   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
397   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
398   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
399 } SYSCFG_TypeDef;
400 
401 /**
402   * @brief Inter-integrated Circuit Interface
403   */
404 
405 typedef struct
406 {
407   __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
408   __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
409   __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
410   __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
411   __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
412   __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
413   __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
414   __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
415   __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
416 } I2C_TypeDef;
417 
418 /**
419   * @brief Independent WATCHDOG
420   */
421 
422 typedef struct
423 {
424   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
425   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
426   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
427   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
428 } IWDG_TypeDef;
429 
430 /**
431   * @brief LCD
432   */
433 
434 typedef struct
435 {
436   __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
437   __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
438   __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
439   __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
440   uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
441   __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
442 } LCD_TypeDef;
443 
444 /**
445   * @brief Power Control
446   */
447 
448 typedef struct
449 {
450   __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
451   __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
452 } PWR_TypeDef;
453 
454 /**
455   * @brief Reset and Clock Control
456   */
457 
458 typedef struct
459 {
460   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
461   __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
462   __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
463   __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
464   __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
465   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
466   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
467   __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
468   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
469   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
470   __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
471   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
472   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
473   __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
474 } RCC_TypeDef;
475 
476 /**
477   * @brief Routing Interface
478   */
479 
480 typedef struct
481 {
482   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
483   __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
484   __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
485   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
486   __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
487   __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
488   __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
489   __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
490   __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
491   __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
492   __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
493   __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
494   __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
495   __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
496   __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
497   __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
498   __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
499   __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
500   __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
501   __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
502   __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
503   __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
504 } RI_TypeDef;
505 
506 /**
507   * @brief Real-Time Clock
508   */
509 typedef struct
510 {
511   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
512   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
513   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
514   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
515   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
516   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
517   __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
518   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
519   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
520   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
521   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
522   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
523   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
524   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
525   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
526   __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
527   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
528   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
529   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
530   uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
531   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
532   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
533   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
534   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
535   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
536   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
537   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
538   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
539   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
540   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
541   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
542   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
543   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
544   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
545   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
546   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
547   __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
548   __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
549   __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
550   __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
551   __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
552   __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
553   __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
554   __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
555   __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
556   __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
557   __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
558   __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
559   __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
560   __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
561   __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
562   __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
563 } RTC_TypeDef;
564 
565 /**
566   * @brief SD host Interface
567   */
568 
569 typedef struct
570 {
571   __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
572   __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
573   __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
574   __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
575   __I uint32_t  RESPCMD;  /*!< SDIO command response register, Address offset: 0x10 */
576   __I uint32_t  RESP1;    /*!< SDIO response 1 register,       Address offset: 0x14 */
577   __I uint32_t  RESP2;    /*!< SDIO response 2 register,       Address offset: 0x18 */
578   __I uint32_t  RESP3;    /*!< SDIO response 3 register,       Address offset: 0x1C */
579   __I uint32_t  RESP4;    /*!< SDIO response 4 register,       Address offset: 0x20 */
580   __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
581   __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
582   __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
583   __I uint32_t  DCOUNT;   /*!< SDIO data counter register,     Address offset: 0x30 */
584   __I uint32_t  STA;      /*!< SDIO status register,           Address offset: 0x34 */
585   __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
586   __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
587   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
588   __I uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */
589   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
590   __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
591 } SDIO_TypeDef;
592 
593 /**
594   * @brief Serial Peripheral Interface
595   */
596 
597 typedef struct
598 {
599   __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
600   __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
601   __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
602   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
603   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
604   __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
605   __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
606   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
607   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
608 } SPI_TypeDef;
609 
610 /**
611   * @brief TIM
612   */
613 typedef struct
614 {
615   __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
616   __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
617   __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
618   __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
619   __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
620   __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
621   __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
622   __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
623   __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
624   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
625   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
626   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
627   uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
628   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
629   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
630   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
631   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
632   uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
633   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
634   __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
635   __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
636 } TIM_TypeDef;
637 /**
638   * @brief Universal Synchronous Asynchronous Receiver Transmitter
639   */
640 
641 typedef struct
642 {
643   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
644   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
645   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
646   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
647   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
648   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
649   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
650 } USART_TypeDef;
651 
652 /**
653   * @brief Universal Serial Bus Full Speed Device
654   */
655 
656 typedef struct
657 {
658   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
659   __IO uint16_t RESERVED0;       /*!< Reserved */
660   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
661   __IO uint16_t RESERVED1;       /*!< Reserved */
662   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
663   __IO uint16_t RESERVED2;       /*!< Reserved */
664   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
665   __IO uint16_t RESERVED3;       /*!< Reserved */
666   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
667   __IO uint16_t RESERVED4;       /*!< Reserved */
668   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
669   __IO uint16_t RESERVED5;       /*!< Reserved */
670   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
671   __IO uint16_t RESERVED6;       /*!< Reserved */
672   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
673   __IO uint16_t RESERVED7[17];   /*!< Reserved */
674   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
675   __IO uint16_t RESERVED8;       /*!< Reserved */
676   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
677   __IO uint16_t RESERVED9;       /*!< Reserved */
678   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
679   __IO uint16_t RESERVEDA;       /*!< Reserved */
680   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
681   __IO uint16_t RESERVEDB;       /*!< Reserved */
682   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
683   __IO uint16_t RESERVEDC;       /*!< Reserved */
684 } USB_TypeDef;
685 
686 /**
687   * @brief Window WATCHDOG
688   */
689 typedef struct
690 {
691   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
692   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
693   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
694 } WWDG_TypeDef;
695 
696 /**
697   * @brief Universal Serial Bus Full Speed Device
698   */
699 /**
700   * @}
701   */
702 
703 /** @addtogroup Peripheral_memory_map
704   * @{
705   */
706 
707 #define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
708 #define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
709 #define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
710 #define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
711 #define FSMC_BASE             (0x60000000UL)              /*!< FSMC base address */
712 #define FSMC_R_BASE           (0xA0000000UL)              /*!< FSMC registers base address */
713 #define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
714 #define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
715 #define FLASH_END             (0x0805FFFFUL)              /*!< Program end FLASH address for Cat4 */
716 #define FLASH_BANK2_BASE      (0x08030000UL)              /*!< FLASH BANK2 base address in the alias region */
717 #define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address */
718 #define FLASH_BANK2_END       (0x0805FFFFUL)              /*!< Program end FLASH BANK2 address */
719 #define FLASH_EEPROM_END      (0x08082FFFUL)              /*!< FLASH EEPROM end address  (12KB) */
720 
721 /*!< Peripheral memory map */
722 #define APB1PERIPH_BASE       PERIPH_BASE
723 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
724 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
725 
726 /*!< APB1 peripherals */
727 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
728 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
729 #define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
730 #define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
731 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
732 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
733 #define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
734 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
735 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
736 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
737 #define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
738 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
739 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
740 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
741 #define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
742 #define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
743 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
744 #define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
745 
746 /* USB device FS */
747 #define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
748 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
749 
750 /* USB device FS SRAM */
751 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
752 #define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
753 #define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
754 #define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
755 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
756 
757 /*!< APB2 peripherals */
758 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
759 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
760 #define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
761 #define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
762 #define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
763 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
764 #define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
765 #define SDIO_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
766 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
767 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
768 
769 /*!< AHB peripherals */
770 #define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
771 #define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
772 #define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
773 #define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
774 #define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
775 #define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
776 #define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
777 #define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
778 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
779 #define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
780 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
781 #define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
782 #define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
783 #define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
784 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
785 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
786 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
787 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
788 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
789 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
790 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
791 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
792 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
793 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
794 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
795 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
796 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
797 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
798 #define AES_BASE              (0x50060000UL)
799 #define FSMC_BANK1            (FSMC_BASE)                 /*!< FSMC Bank1 base address */
800 #define FSMC_BANK1_1          (FSMC_BANK1)                /*!< FSMC Bank1_1 base address */
801 #define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
802 #define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
803 #define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
804 #define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000UL)    /*!< FSMC Bank1 registers base address */
805 #define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104UL)    /*!< FSMC Bank1E registers base address */
806 #define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
807 
808 /**
809   * @}
810   */
811 
812 /** @addtogroup Peripheral_declaration
813   * @{
814   */
815 
816 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
817 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
818 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
819 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
820 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
821 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
822 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
823 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
824 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
825 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
826 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
827 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
828 #define USART2              ((USART_TypeDef *) USART2_BASE)
829 #define USART3              ((USART_TypeDef *) USART3_BASE)
830 #define UART4               ((USART_TypeDef *) UART4_BASE)
831 #define UART5               ((USART_TypeDef *) UART5_BASE)
832 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
833 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
834 /* USB device FS */
835 #define USB                   ((USB_TypeDef *) USB_BASE)
836 /* USB device FS SRAM */
837 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
838 
839 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
840 /* Legacy define */
841 #define DAC                 DAC1
842 
843 #define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
844 #define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
845 #define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
846 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
847 
848 #define RI                  ((RI_TypeDef *) RI_BASE)
849 
850 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
851 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
852 #define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
853 #define OPAMP3              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U))
854 #define OPAMP123_COMMON     ((OPAMP_Common_TypeDef *) OPAMP_BASE)
855 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
856 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
857 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
858 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
859 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
860 
861 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
862 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
863 /* Legacy defines */
864 #define ADC                 ADC1_COMMON
865 
866 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
867 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
868 #define USART1              ((USART_TypeDef *) USART1_BASE)
869 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
870 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
871 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
872 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
873 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
874 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
875 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
876 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
877 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
878 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
879 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
880 #define OB                  ((OB_TypeDef *) OB_BASE)
881 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
882 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
883 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
884 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
885 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
886 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
887 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
888 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
889 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
890 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
891 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
892 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
893 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
894 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
895 #define AES                 ((AES_TypeDef *) AES_BASE)
896 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
897 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
898 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
899 
900  /**
901   * @}
902   */
903 
904 /** @addtogroup Exported_constants
905   * @{
906   */
907 
908   /** @addtogroup Hardware_Constant_Definition
909     * @{
910     */
911 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
912 
913   /**
914     * @}
915     */
916 
917 /** @addtogroup Peripheral_Registers_Bits_Definition
918   * @{
919   */
920 
921 /******************************************************************************/
922 /*                         Peripheral Registers Bits Definition               */
923 /******************************************************************************/
924 /******************************************************************************/
925 /*                                                                            */
926 /*                      Analog to Digital Converter (ADC)                     */
927 /*                                                                            */
928 /******************************************************************************/
929 #define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
930 #define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
931 #define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
932 
933 /********************  Bit definition for ADC_SR register  ********************/
934 #define ADC_SR_AWD_Pos                       (0U)
935 #define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
936 #define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
937 #define ADC_SR_EOCS_Pos                      (1U)
938 #define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
939 #define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
940 #define ADC_SR_JEOS_Pos                      (2U)
941 #define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
942 #define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
943 #define ADC_SR_JSTRT_Pos                     (3U)
944 #define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
945 #define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
946 #define ADC_SR_STRT_Pos                      (4U)
947 #define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
948 #define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
949 #define ADC_SR_OVR_Pos                       (5U)
950 #define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
951 #define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
952 #define ADC_SR_ADONS_Pos                     (6U)
953 #define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
954 #define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
955 #define ADC_SR_RCNR_Pos                      (8U)
956 #define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
957 #define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
958 #define ADC_SR_JCNR_Pos                      (9U)
959 #define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
960 #define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
961 
962 /* Legacy defines */
963 #define  ADC_SR_EOC                          (ADC_SR_EOCS)
964 #define  ADC_SR_JEOC                         (ADC_SR_JEOS)
965 
966 /*******************  Bit definition for ADC_CR1 register  ********************/
967 #define ADC_CR1_AWDCH_Pos                    (0U)
968 #define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
969 #define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
970 #define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
971 #define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
972 #define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
973 #define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
974 #define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
975 
976 #define ADC_CR1_EOCSIE_Pos                   (5U)
977 #define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
978 #define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
979 #define ADC_CR1_AWDIE_Pos                    (6U)
980 #define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
981 #define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
982 #define ADC_CR1_JEOSIE_Pos                   (7U)
983 #define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
984 #define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
985 #define ADC_CR1_SCAN_Pos                     (8U)
986 #define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
987 #define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
988 #define ADC_CR1_AWDSGL_Pos                   (9U)
989 #define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
990 #define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
991 #define ADC_CR1_JAUTO_Pos                    (10U)
992 #define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
993 #define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
994 #define ADC_CR1_DISCEN_Pos                   (11U)
995 #define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
996 #define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
997 #define ADC_CR1_JDISCEN_Pos                  (12U)
998 #define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
999 #define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
1000 
1001 #define ADC_CR1_DISCNUM_Pos                  (13U)
1002 #define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
1003 #define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
1004 #define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
1005 #define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
1006 #define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
1007 
1008 #define ADC_CR1_PDD_Pos                      (16U)
1009 #define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
1010 #define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
1011 #define ADC_CR1_PDI_Pos                      (17U)
1012 #define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
1013 #define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
1014 
1015 #define ADC_CR1_JAWDEN_Pos                   (22U)
1016 #define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
1017 #define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1018 #define ADC_CR1_AWDEN_Pos                    (23U)
1019 #define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
1020 #define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1021 
1022 #define ADC_CR1_RES_Pos                      (24U)
1023 #define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
1024 #define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
1025 #define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
1026 #define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
1027 
1028 #define ADC_CR1_OVRIE_Pos                    (26U)
1029 #define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
1030 #define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
1031 
1032 /* Legacy defines */
1033 #define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
1034 #define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
1035 
1036 /*******************  Bit definition for ADC_CR2 register  ********************/
1037 #define ADC_CR2_ADON_Pos                     (0U)
1038 #define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
1039 #define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
1040 #define ADC_CR2_CONT_Pos                     (1U)
1041 #define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
1042 #define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
1043 #define ADC_CR2_CFG_Pos                      (2U)
1044 #define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
1045 #define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
1046 
1047 #define ADC_CR2_DELS_Pos                     (4U)
1048 #define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
1049 #define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
1050 #define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
1051 #define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
1052 #define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
1053 
1054 #define ADC_CR2_DMA_Pos                      (8U)
1055 #define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
1056 #define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
1057 #define ADC_CR2_DDS_Pos                      (9U)
1058 #define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
1059 #define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
1060 #define ADC_CR2_EOCS_Pos                     (10U)
1061 #define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
1062 #define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
1063 #define ADC_CR2_ALIGN_Pos                    (11U)
1064 #define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
1065 #define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignment */
1066 
1067 #define ADC_CR2_JEXTSEL_Pos                  (16U)
1068 #define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
1069 #define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
1070 #define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
1071 #define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
1072 #define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
1073 #define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
1074 
1075 #define ADC_CR2_JEXTEN_Pos                   (20U)
1076 #define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
1077 #define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
1078 #define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
1079 #define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
1080 
1081 #define ADC_CR2_JSWSTART_Pos                 (22U)
1082 #define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
1083 #define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
1084 
1085 #define ADC_CR2_EXTSEL_Pos                   (24U)
1086 #define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
1087 #define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
1088 #define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
1089 #define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
1090 #define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
1091 #define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
1092 
1093 #define ADC_CR2_EXTEN_Pos                    (28U)
1094 #define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
1095 #define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
1096 #define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
1097 #define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
1098 
1099 #define ADC_CR2_SWSTART_Pos                  (30U)
1100 #define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
1101 #define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
1102 
1103 /******************  Bit definition for ADC_SMPR1 register  *******************/
1104 #define ADC_SMPR1_SMP20_Pos                  (0U)
1105 #define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
1106 #define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
1107 #define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
1108 #define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
1109 #define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
1110 
1111 #define ADC_SMPR1_SMP21_Pos                  (3U)
1112 #define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
1113 #define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
1114 #define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
1115 #define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
1116 #define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
1117 
1118 #define ADC_SMPR1_SMP22_Pos                  (6U)
1119 #define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
1120 #define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
1121 #define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
1122 #define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
1123 #define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
1124 
1125 #define ADC_SMPR1_SMP23_Pos                  (9U)
1126 #define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
1127 #define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
1128 #define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
1129 #define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
1130 #define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
1131 
1132 #define ADC_SMPR1_SMP24_Pos                  (12U)
1133 #define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
1134 #define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
1135 #define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
1136 #define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
1137 #define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
1138 
1139 #define ADC_SMPR1_SMP25_Pos                  (15U)
1140 #define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
1141 #define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
1142 #define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
1143 #define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
1144 #define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
1145 
1146 #define ADC_SMPR1_SMP26_Pos                  (18U)
1147 #define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
1148 #define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
1149 #define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
1150 #define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
1151 #define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
1152 
1153 #define ADC_SMPR1_SMP27_Pos                  (21U)
1154 #define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
1155 #define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
1156 #define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
1157 #define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
1158 #define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
1159 
1160 #define ADC_SMPR1_SMP28_Pos                  (24U)
1161 #define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
1162 #define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
1163 #define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
1164 #define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
1165 #define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
1166 
1167 #define ADC_SMPR1_SMP29_Pos                  (27U)
1168 #define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
1169 #define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
1170 #define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
1171 #define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
1172 #define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
1173 
1174 /******************  Bit definition for ADC_SMPR2 register  *******************/
1175 #define ADC_SMPR2_SMP10_Pos                  (0U)
1176 #define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
1177 #define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
1178 #define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
1179 #define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
1180 #define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
1181 
1182 #define ADC_SMPR2_SMP11_Pos                  (3U)
1183 #define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
1184 #define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
1185 #define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
1186 #define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
1187 #define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
1188 
1189 #define ADC_SMPR2_SMP12_Pos                  (6U)
1190 #define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
1191 #define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
1192 #define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
1193 #define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
1194 #define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
1195 
1196 #define ADC_SMPR2_SMP13_Pos                  (9U)
1197 #define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
1198 #define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
1199 #define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
1200 #define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
1201 #define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
1202 
1203 #define ADC_SMPR2_SMP14_Pos                  (12U)
1204 #define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
1205 #define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
1206 #define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
1207 #define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
1208 #define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
1209 
1210 #define ADC_SMPR2_SMP15_Pos                  (15U)
1211 #define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
1212 #define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
1213 #define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
1214 #define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
1215 #define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
1216 
1217 #define ADC_SMPR2_SMP16_Pos                  (18U)
1218 #define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
1219 #define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
1220 #define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
1221 #define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
1222 #define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
1223 
1224 #define ADC_SMPR2_SMP17_Pos                  (21U)
1225 #define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
1226 #define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
1227 #define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
1228 #define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
1229 #define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
1230 
1231 #define ADC_SMPR2_SMP18_Pos                  (24U)
1232 #define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
1233 #define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
1234 #define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
1235 #define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
1236 #define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
1237 
1238 #define ADC_SMPR2_SMP19_Pos                  (27U)
1239 #define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
1240 #define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
1241 #define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
1242 #define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
1243 #define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
1244 
1245 /******************  Bit definition for ADC_SMPR3 register  *******************/
1246 #define ADC_SMPR3_SMP0_Pos                   (0U)
1247 #define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
1248 #define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
1249 #define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
1250 #define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
1251 #define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
1252 
1253 #define ADC_SMPR3_SMP1_Pos                   (3U)
1254 #define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
1255 #define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
1256 #define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
1257 #define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
1258 #define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
1259 
1260 #define ADC_SMPR3_SMP2_Pos                   (6U)
1261 #define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
1262 #define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
1263 #define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
1264 #define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
1265 #define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
1266 
1267 #define ADC_SMPR3_SMP3_Pos                   (9U)
1268 #define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
1269 #define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
1270 #define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
1271 #define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
1272 #define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
1273 
1274 #define ADC_SMPR3_SMP4_Pos                   (12U)
1275 #define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
1276 #define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
1277 #define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
1278 #define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
1279 #define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
1280 
1281 #define ADC_SMPR3_SMP5_Pos                   (15U)
1282 #define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
1283 #define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
1284 #define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
1285 #define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
1286 #define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
1287 
1288 #define ADC_SMPR3_SMP6_Pos                   (18U)
1289 #define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
1290 #define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
1291 #define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
1292 #define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
1293 #define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
1294 
1295 #define ADC_SMPR3_SMP7_Pos                   (21U)
1296 #define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
1297 #define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
1298 #define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
1299 #define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
1300 #define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
1301 
1302 #define ADC_SMPR3_SMP8_Pos                   (24U)
1303 #define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
1304 #define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
1305 #define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
1306 #define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
1307 #define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
1308 
1309 #define ADC_SMPR3_SMP9_Pos                   (27U)
1310 #define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
1311 #define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
1312 #define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
1313 #define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
1314 #define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
1315 
1316 /******************  Bit definition for ADC_JOFR1 register  *******************/
1317 #define ADC_JOFR1_JOFFSET1_Pos               (0U)
1318 #define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1319 #define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
1320 
1321 /******************  Bit definition for ADC_JOFR2 register  *******************/
1322 #define ADC_JOFR2_JOFFSET2_Pos               (0U)
1323 #define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1324 #define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
1325 
1326 /******************  Bit definition for ADC_JOFR3 register  *******************/
1327 #define ADC_JOFR3_JOFFSET3_Pos               (0U)
1328 #define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1329 #define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
1330 
1331 /******************  Bit definition for ADC_JOFR4 register  *******************/
1332 #define ADC_JOFR4_JOFFSET4_Pos               (0U)
1333 #define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1334 #define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
1335 
1336 /*******************  Bit definition for ADC_HTR register  ********************/
1337 #define ADC_HTR_HT_Pos                       (0U)
1338 #define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
1339 #define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
1340 
1341 /*******************  Bit definition for ADC_LTR register  ********************/
1342 #define ADC_LTR_LT_Pos                       (0U)
1343 #define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
1344 #define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
1345 
1346 /*******************  Bit definition for ADC_SQR1 register  *******************/
1347 #define ADC_SQR1_L_Pos                       (20U)
1348 #define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
1349 #define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
1350 #define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
1351 #define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
1352 #define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
1353 #define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
1354 #define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
1355 
1356 #define ADC_SQR1_SQ28_Pos                    (15U)
1357 #define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
1358 #define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
1359 #define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
1360 #define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
1361 #define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
1362 #define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
1363 #define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
1364 
1365 #define ADC_SQR1_SQ27_Pos                    (10U)
1366 #define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
1367 #define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
1368 #define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
1369 #define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
1370 #define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
1371 #define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
1372 #define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
1373 
1374 #define ADC_SQR1_SQ26_Pos                    (5U)
1375 #define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
1376 #define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
1377 #define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
1378 #define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
1379 #define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
1380 #define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
1381 #define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
1382 
1383 #define ADC_SQR1_SQ25_Pos                    (0U)
1384 #define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
1385 #define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
1386 #define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
1387 #define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
1388 #define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
1389 #define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
1390 #define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
1391 
1392 /*******************  Bit definition for ADC_SQR2 register  *******************/
1393 #define ADC_SQR2_SQ19_Pos                    (0U)
1394 #define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
1395 #define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
1396 #define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
1397 #define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
1398 #define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
1399 #define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
1400 #define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
1401 
1402 #define ADC_SQR2_SQ20_Pos                    (5U)
1403 #define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
1404 #define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
1405 #define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
1406 #define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
1407 #define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
1408 #define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
1409 #define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
1410 
1411 #define ADC_SQR2_SQ21_Pos                    (10U)
1412 #define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
1413 #define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
1414 #define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
1415 #define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
1416 #define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
1417 #define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
1418 #define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
1419 
1420 #define ADC_SQR2_SQ22_Pos                    (15U)
1421 #define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
1422 #define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
1423 #define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
1424 #define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
1425 #define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
1426 #define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
1427 #define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
1428 
1429 #define ADC_SQR2_SQ23_Pos                    (20U)
1430 #define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
1431 #define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
1432 #define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
1433 #define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
1434 #define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
1435 #define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
1436 #define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
1437 
1438 #define ADC_SQR2_SQ24_Pos                    (25U)
1439 #define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
1440 #define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
1441 #define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
1442 #define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
1443 #define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
1444 #define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
1445 #define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
1446 
1447 /*******************  Bit definition for ADC_SQR3 register  *******************/
1448 #define ADC_SQR3_SQ13_Pos                    (0U)
1449 #define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
1450 #define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
1451 #define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
1452 #define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
1453 #define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
1454 #define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
1455 #define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
1456 
1457 #define ADC_SQR3_SQ14_Pos                    (5U)
1458 #define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
1459 #define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
1460 #define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
1461 #define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
1462 #define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
1463 #define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
1464 #define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
1465 
1466 #define ADC_SQR3_SQ15_Pos                    (10U)
1467 #define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
1468 #define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
1469 #define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
1470 #define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
1471 #define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
1472 #define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
1473 #define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
1474 
1475 #define ADC_SQR3_SQ16_Pos                    (15U)
1476 #define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
1477 #define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
1478 #define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
1479 #define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
1480 #define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
1481 #define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
1482 #define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
1483 
1484 #define ADC_SQR3_SQ17_Pos                    (20U)
1485 #define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
1486 #define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
1487 #define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
1488 #define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
1489 #define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
1490 #define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
1491 #define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
1492 
1493 #define ADC_SQR3_SQ18_Pos                    (25U)
1494 #define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
1495 #define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
1496 #define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
1497 #define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
1498 #define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
1499 #define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
1500 #define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
1501 
1502 /*******************  Bit definition for ADC_SQR4 register  *******************/
1503 #define ADC_SQR4_SQ7_Pos                     (0U)
1504 #define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
1505 #define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
1506 #define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
1507 #define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
1508 #define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
1509 #define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
1510 #define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
1511 
1512 #define ADC_SQR4_SQ8_Pos                     (5U)
1513 #define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
1514 #define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
1515 #define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
1516 #define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
1517 #define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
1518 #define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
1519 #define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
1520 
1521 #define ADC_SQR4_SQ9_Pos                     (10U)
1522 #define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
1523 #define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
1524 #define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
1525 #define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
1526 #define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
1527 #define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
1528 #define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
1529 
1530 #define ADC_SQR4_SQ10_Pos                    (15U)
1531 #define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
1532 #define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
1533 #define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
1534 #define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
1535 #define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
1536 #define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
1537 #define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
1538 
1539 #define ADC_SQR4_SQ11_Pos                    (20U)
1540 #define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
1541 #define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
1542 #define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
1543 #define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
1544 #define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
1545 #define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
1546 #define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
1547 
1548 #define ADC_SQR4_SQ12_Pos                    (25U)
1549 #define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
1550 #define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
1551 #define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
1552 #define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
1553 #define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
1554 #define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
1555 #define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
1556 
1557 /*******************  Bit definition for ADC_SQR5 register  *******************/
1558 #define ADC_SQR5_SQ1_Pos                     (0U)
1559 #define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
1560 #define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
1561 #define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
1562 #define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
1563 #define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
1564 #define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
1565 #define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
1566 
1567 #define ADC_SQR5_SQ2_Pos                     (5U)
1568 #define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
1569 #define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
1570 #define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
1571 #define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
1572 #define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
1573 #define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
1574 #define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
1575 
1576 #define ADC_SQR5_SQ3_Pos                     (10U)
1577 #define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
1578 #define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
1579 #define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
1580 #define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
1581 #define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
1582 #define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
1583 #define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
1584 
1585 #define ADC_SQR5_SQ4_Pos                     (15U)
1586 #define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
1587 #define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
1588 #define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
1589 #define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
1590 #define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
1591 #define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
1592 #define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
1593 
1594 #define ADC_SQR5_SQ5_Pos                     (20U)
1595 #define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
1596 #define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
1597 #define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
1598 #define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
1599 #define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
1600 #define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
1601 #define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
1602 
1603 #define ADC_SQR5_SQ6_Pos                     (25U)
1604 #define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
1605 #define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
1606 #define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
1607 #define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
1608 #define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
1609 #define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
1610 #define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
1611 
1612 
1613 /*******************  Bit definition for ADC_JSQR register  *******************/
1614 #define ADC_JSQR_JSQ1_Pos                    (0U)
1615 #define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
1616 #define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
1617 #define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
1618 #define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
1619 #define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
1620 #define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
1621 #define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
1622 
1623 #define ADC_JSQR_JSQ2_Pos                    (5U)
1624 #define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
1625 #define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
1626 #define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
1627 #define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
1628 #define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
1629 #define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
1630 #define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
1631 
1632 #define ADC_JSQR_JSQ3_Pos                    (10U)
1633 #define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
1634 #define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
1635 #define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
1636 #define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
1637 #define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
1638 #define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
1639 #define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
1640 
1641 #define ADC_JSQR_JSQ4_Pos                    (15U)
1642 #define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
1643 #define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
1644 #define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
1645 #define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
1646 #define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
1647 #define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
1648 #define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
1649 
1650 #define ADC_JSQR_JL_Pos                      (20U)
1651 #define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
1652 #define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
1653 #define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
1654 #define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
1655 
1656 /*******************  Bit definition for ADC_JDR1 register  *******************/
1657 #define ADC_JDR1_JDATA_Pos                   (0U)
1658 #define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
1659 #define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
1660 
1661 /*******************  Bit definition for ADC_JDR2 register  *******************/
1662 #define ADC_JDR2_JDATA_Pos                   (0U)
1663 #define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
1664 #define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
1665 
1666 /*******************  Bit definition for ADC_JDR3 register  *******************/
1667 #define ADC_JDR3_JDATA_Pos                   (0U)
1668 #define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
1669 #define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
1670 
1671 /*******************  Bit definition for ADC_JDR4 register  *******************/
1672 #define ADC_JDR4_JDATA_Pos                   (0U)
1673 #define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
1674 #define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
1675 
1676 /********************  Bit definition for ADC_DR register  ********************/
1677 #define ADC_DR_DATA_Pos                      (0U)
1678 #define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
1679 #define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
1680 
1681 /******************  Bit definition for ADC_SMPR0 register  *******************/
1682 #define ADC_SMPR0_SMP30_Pos                  (0U)
1683 #define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
1684 #define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
1685 #define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
1686 #define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
1687 #define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
1688 
1689 #define ADC_SMPR0_SMP31_Pos                  (3U)
1690 #define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
1691 #define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
1692 #define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
1693 #define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
1694 #define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
1695 
1696 /*******************  Bit definition for ADC_CSR register  ********************/
1697 #define ADC_CSR_AWD1_Pos                     (0U)
1698 #define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
1699 #define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
1700 #define ADC_CSR_EOCS1_Pos                    (1U)
1701 #define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
1702 #define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
1703 #define ADC_CSR_JEOS1_Pos                    (2U)
1704 #define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
1705 #define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
1706 #define ADC_CSR_JSTRT1_Pos                   (3U)
1707 #define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
1708 #define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
1709 #define ADC_CSR_STRT1_Pos                    (4U)
1710 #define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
1711 #define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
1712 #define ADC_CSR_OVR1_Pos                     (5U)
1713 #define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
1714 #define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
1715 #define ADC_CSR_ADONS1_Pos                   (6U)
1716 #define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
1717 #define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
1718 
1719 /* Legacy defines */
1720 #define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
1721 #define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
1722 
1723 /*******************  Bit definition for ADC_CCR register  ********************/
1724 #define ADC_CCR_ADCPRE_Pos                   (16U)
1725 #define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
1726 #define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
1727 #define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
1728 #define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
1729 #define ADC_CCR_TSVREFE_Pos                  (23U)
1730 #define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
1731 #define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
1732 
1733 /******************************************************************************/
1734 /*                                                                            */
1735 /*                       Advanced Encryption Standard (AES)                   */
1736 /*                                                                            */
1737 /******************************************************************************/
1738 /*******************  Bit definition for AES_CR register  *********************/
1739 #define AES_CR_EN_Pos                       (0U)
1740 #define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
1741 #define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
1742 #define AES_CR_DATATYPE_Pos                 (1U)
1743 #define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
1744 #define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
1745 #define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
1746 #define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
1747 
1748 #define AES_CR_MODE_Pos                     (3U)
1749 #define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
1750 #define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
1751 #define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
1752 #define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
1753 
1754 #define AES_CR_CHMOD_Pos                    (5U)
1755 #define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
1756 #define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
1757 #define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
1758 #define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
1759 
1760 #define AES_CR_CCFC_Pos                     (7U)
1761 #define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
1762 #define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
1763 #define AES_CR_ERRC_Pos                     (8U)
1764 #define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
1765 #define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
1766 #define AES_CR_CCIE_Pos                     (9U)
1767 #define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
1768 #define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
1769 #define AES_CR_ERRIE_Pos                    (10U)
1770 #define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
1771 #define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
1772 #define AES_CR_DMAINEN_Pos                  (11U)
1773 #define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
1774 #define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
1775 #define AES_CR_DMAOUTEN_Pos                 (12U)
1776 #define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
1777 #define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
1778 
1779 /*******************  Bit definition for AES_SR register  *********************/
1780 #define AES_SR_CCF_Pos                      (0U)
1781 #define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
1782 #define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
1783 #define AES_SR_RDERR_Pos                    (1U)
1784 #define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
1785 #define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
1786 #define AES_SR_WRERR_Pos                    (2U)
1787 #define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
1788 #define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
1789 
1790 /*******************  Bit definition for AES_DINR register  *******************/
1791 #define AES_DINR_Pos                        (0U)
1792 #define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
1793 #define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
1794 
1795 /*******************  Bit definition for AES_DOUTR register  ******************/
1796 #define AES_DOUTR_Pos                       (0U)
1797 #define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
1798 #define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
1799 
1800 /*******************  Bit definition for AES_KEYR0 register  ******************/
1801 #define AES_KEYR0_Pos                       (0U)
1802 #define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
1803 #define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
1804 
1805 /*******************  Bit definition for AES_KEYR1 register  ******************/
1806 #define AES_KEYR1_Pos                       (0U)
1807 #define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
1808 #define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
1809 
1810 /*******************  Bit definition for AES_KEYR2 register  ******************/
1811 #define AES_KEYR2_Pos                       (0U)
1812 #define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
1813 #define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
1814 
1815 /*******************  Bit definition for AES_KEYR3 register  ******************/
1816 #define AES_KEYR3_Pos                       (0U)
1817 #define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
1818 #define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
1819 
1820 /*******************  Bit definition for AES_IVR0 register  *******************/
1821 #define AES_IVR0_Pos                        (0U)
1822 #define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
1823 #define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
1824 
1825 /*******************  Bit definition for AES_IVR1 register  *******************/
1826 #define AES_IVR1_Pos                        (0U)
1827 #define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
1828 #define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
1829 
1830 /*******************  Bit definition for AES_IVR2 register  *******************/
1831 #define AES_IVR2_Pos                        (0U)
1832 #define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
1833 #define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
1834 
1835 /*******************  Bit definition for AES_IVR3 register  *******************/
1836 #define AES_IVR3_Pos                        (0U)
1837 #define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
1838 #define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
1839 
1840 /******************************************************************************/
1841 /*                                                                            */
1842 /*                      Analog Comparators (COMP)                             */
1843 /*                                                                            */
1844 /******************************************************************************/
1845 
1846 /******************  Bit definition for COMP_CSR register  ********************/
1847 #define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
1848 #define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
1849 #define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
1850 #define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
1851 #define COMP_CSR_CMP1EN_Pos                 (4U)
1852 #define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
1853 #define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
1854 #define COMP_CSR_CMP1OUT_Pos                (7U)
1855 #define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
1856 #define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
1857 #define COMP_CSR_SPEED_Pos                  (12U)
1858 #define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
1859 #define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
1860 #define COMP_CSR_CMP2OUT_Pos                (13U)
1861 #define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
1862 #define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
1863 
1864 #define COMP_CSR_WNDWE_Pos                  (17U)
1865 #define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
1866 #define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
1867 
1868 #define COMP_CSR_INSEL_Pos                  (18U)
1869 #define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
1870 #define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
1871 #define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
1872 #define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
1873 #define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
1874 #define COMP_CSR_OUTSEL_Pos                 (21U)
1875 #define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
1876 #define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
1877 #define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
1878 #define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
1879 #define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
1880 
1881 /* Bits present in COMP register but not related to comparator */
1882 /* (or partially related to comparator, in addition to other peripherals) */
1883 #define COMP_CSR_SW1_Pos                    (5U)
1884 #define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
1885 #define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
1886 #define COMP_CSR_VREFOUTEN_Pos              (16U)
1887 #define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
1888 #define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
1889 
1890 #define COMP_CSR_FCH3_Pos                   (26U)
1891 #define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
1892 #define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
1893 #define COMP_CSR_FCH8_Pos                   (27U)
1894 #define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
1895 #define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
1896 #define COMP_CSR_RCH13_Pos                  (28U)
1897 #define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
1898 #define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
1899 
1900 #define COMP_CSR_CAIE_Pos                   (29U)
1901 #define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
1902 #define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
1903 #define COMP_CSR_CAIF_Pos                   (30U)
1904 #define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
1905 #define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
1906 #define COMP_CSR_TSUSP_Pos                  (31U)
1907 #define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
1908 #define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
1909 
1910 /******************************************************************************/
1911 /*                                                                            */
1912 /*                         Operational Amplifier (OPAMP)                      */
1913 /*                                                                            */
1914 /******************************************************************************/
1915 /*******************  Bit definition for OPAMP_CSR register  ******************/
1916 #define OPAMP_CSR_OPA1PD_Pos                  (0U)
1917 #define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
1918 #define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
1919 #define OPAMP_CSR_S3SEL1_Pos                  (1U)
1920 #define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
1921 #define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
1922 #define OPAMP_CSR_S4SEL1_Pos                  (2U)
1923 #define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
1924 #define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
1925 #define OPAMP_CSR_S5SEL1_Pos                  (3U)
1926 #define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
1927 #define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
1928 #define OPAMP_CSR_S6SEL1_Pos                  (4U)
1929 #define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
1930 #define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
1931 #define OPAMP_CSR_OPA1CAL_L_Pos               (5U)
1932 #define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
1933 #define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
1934 #define OPAMP_CSR_OPA1CAL_H_Pos               (6U)
1935 #define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
1936 #define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
1937 #define OPAMP_CSR_OPA1LPM_Pos                 (7U)
1938 #define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
1939 #define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
1940 #define OPAMP_CSR_OPA2PD_Pos                  (8U)
1941 #define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
1942 #define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
1943 #define OPAMP_CSR_S3SEL2_Pos                  (9U)
1944 #define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
1945 #define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
1946 #define OPAMP_CSR_S4SEL2_Pos                  (10U)
1947 #define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
1948 #define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
1949 #define OPAMP_CSR_S5SEL2_Pos                  (11U)
1950 #define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
1951 #define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
1952 #define OPAMP_CSR_S6SEL2_Pos                  (12U)
1953 #define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
1954 #define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
1955 #define OPAMP_CSR_OPA2CAL_L_Pos               (13U)
1956 #define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
1957 #define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
1958 #define OPAMP_CSR_OPA2CAL_H_Pos               (14U)
1959 #define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
1960 #define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
1961 #define OPAMP_CSR_OPA2LPM_Pos                 (15U)
1962 #define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
1963 #define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
1964 #define OPAMP_CSR_OPA3PD_Pos                  (16U)
1965 #define OPAMP_CSR_OPA3PD_Msk                  (0x1UL << OPAMP_CSR_OPA3PD_Pos)   /*!< 0x00010000 */
1966 #define OPAMP_CSR_OPA3PD                      OPAMP_CSR_OPA3PD_Msk             /*!< OPAMP3 disable */
1967 #define OPAMP_CSR_S3SEL3_Pos                  (17U)
1968 #define OPAMP_CSR_S3SEL3_Msk                  (0x1UL << OPAMP_CSR_S3SEL3_Pos)   /*!< 0x00020000 */
1969 #define OPAMP_CSR_S3SEL3                      OPAMP_CSR_S3SEL3_Msk             /*!< Switch 3 for OPAMP3 Enable */
1970 #define OPAMP_CSR_S4SEL3_Pos                  (18U)
1971 #define OPAMP_CSR_S4SEL3_Msk                  (0x1UL << OPAMP_CSR_S4SEL3_Pos)   /*!< 0x00040000 */
1972 #define OPAMP_CSR_S4SEL3                      OPAMP_CSR_S4SEL3_Msk             /*!< Switch 4 for OPAMP3 Enable */
1973 #define OPAMP_CSR_S5SEL3_Pos                  (19U)
1974 #define OPAMP_CSR_S5SEL3_Msk                  (0x1UL << OPAMP_CSR_S5SEL3_Pos)   /*!< 0x00080000 */
1975 #define OPAMP_CSR_S5SEL3                      OPAMP_CSR_S5SEL3_Msk             /*!< Switch 5 for OPAMP3 Enable */
1976 #define OPAMP_CSR_S6SEL3_Pos                  (20U)
1977 #define OPAMP_CSR_S6SEL3_Msk                  (0x1UL << OPAMP_CSR_S6SEL3_Pos)   /*!< 0x00100000 */
1978 #define OPAMP_CSR_S6SEL3                      OPAMP_CSR_S6SEL3_Msk             /*!< Switch 6 for OPAMP3 Enable */
1979 #define OPAMP_CSR_OPA3CAL_L_Pos               (21U)
1980 #define OPAMP_CSR_OPA3CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */
1981 #define OPAMP_CSR_OPA3CAL_L                   OPAMP_CSR_OPA3CAL_L_Msk          /*!< OPAMP3 Offset calibration for P differential pair */
1982 #define OPAMP_CSR_OPA3CAL_H_Pos               (22U)
1983 #define OPAMP_CSR_OPA3CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */
1984 #define OPAMP_CSR_OPA3CAL_H                   OPAMP_CSR_OPA3CAL_H_Msk          /*!< OPAMP3 Offset calibration for N differential pair */
1985 #define OPAMP_CSR_OPA3LPM_Pos                 (23U)
1986 #define OPAMP_CSR_OPA3LPM_Msk                 (0x1UL << OPAMP_CSR_OPA3LPM_Pos)  /*!< 0x00800000 */
1987 #define OPAMP_CSR_OPA3LPM                     OPAMP_CSR_OPA3LPM_Msk            /*!< OPAMP3 Low power enable */
1988 #define OPAMP_CSR_ANAWSEL1_Pos                (24U)
1989 #define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
1990 #define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */
1991 #define OPAMP_CSR_ANAWSEL2_Pos                (25U)
1992 #define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
1993 #define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
1994 #define OPAMP_CSR_ANAWSEL3_Pos                (26U)
1995 #define OPAMP_CSR_ANAWSEL3_Msk                (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */
1996 #define OPAMP_CSR_ANAWSEL3                    OPAMP_CSR_ANAWSEL3_Msk           /*!< Switch ANA Enable for OPAMP3 */
1997 #define OPAMP_CSR_S7SEL2_Pos                  (27U)
1998 #define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
1999 #define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
2000 #define OPAMP_CSR_AOP_RANGE_Pos               (28U)
2001 #define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
2002 #define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
2003 #define OPAMP_CSR_OPA1CALOUT_Pos              (29U)
2004 #define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
2005 #define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
2006 #define OPAMP_CSR_OPA2CALOUT_Pos              (30U)
2007 #define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
2008 #define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
2009 #define OPAMP_CSR_OPA3CALOUT_Pos              (31U)
2010 #define OPAMP_CSR_OPA3CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */
2011 #define OPAMP_CSR_OPA3CALOUT                  OPAMP_CSR_OPA3CALOUT_Msk         /*!< OPAMP3 calibration output */
2012 
2013 /*******************  Bit definition for OPAMP_OTR register  ******************/
2014 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
2015 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
2016 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
2017 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
2018 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
2019 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
2020 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
2021 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
2022 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
2023 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
2024 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
2025 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
2026 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U)
2027 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */
2028 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
2029 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U)
2030 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */
2031 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
2032 #define OPAMP_OTR_OT_USER_Pos                 (31U)
2033 #define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
2034 #define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
2035 
2036 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
2037 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
2038 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
2039 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
2040 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
2041 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
2042 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
2043 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
2044 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
2045 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
2046 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
2047 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
2048 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
2049 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U)
2050 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */
2051 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
2052 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U)
2053 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */
2054 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
2055 
2056 /******************************************************************************/
2057 /*                                                                            */
2058 /*                       CRC calculation unit (CRC)                           */
2059 /*                                                                            */
2060 /******************************************************************************/
2061 
2062 /*******************  Bit definition for CRC_DR register  *********************/
2063 #define CRC_DR_DR_Pos                       (0U)
2064 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
2065 #define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
2066 
2067 /*******************  Bit definition for CRC_IDR register  ********************/
2068 #define CRC_IDR_IDR_Pos                     (0U)
2069 #define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
2070 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
2071 
2072 /********************  Bit definition for CRC_CR register  ********************/
2073 #define CRC_CR_RESET_Pos                    (0U)
2074 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
2075 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
2076 
2077 /******************************************************************************/
2078 /*                                                                            */
2079 /*                    Digital to Analog Converter (DAC)                       */
2080 /*                                                                            */
2081 /******************************************************************************/
2082 
2083 /********************  Bit definition for DAC_CR register  ********************/
2084 #define DAC_CR_EN1_Pos                      (0U)
2085 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
2086 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
2087 #define DAC_CR_BOFF1_Pos                    (1U)
2088 #define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
2089 #define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
2090 #define DAC_CR_TEN1_Pos                     (2U)
2091 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
2092 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
2093 
2094 #define DAC_CR_TSEL1_Pos                    (3U)
2095 #define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
2096 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2097 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
2098 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
2099 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
2100 
2101 #define DAC_CR_WAVE1_Pos                    (6U)
2102 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
2103 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2104 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
2105 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
2106 
2107 #define DAC_CR_MAMP1_Pos                    (8U)
2108 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
2109 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2110 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
2111 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
2112 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
2113 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
2114 
2115 #define DAC_CR_DMAEN1_Pos                   (12U)
2116 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
2117 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
2118 #define DAC_CR_DMAUDRIE1_Pos                (13U)
2119 #define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
2120 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
2121 #define DAC_CR_EN2_Pos                      (16U)
2122 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
2123 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
2124 #define DAC_CR_BOFF2_Pos                    (17U)
2125 #define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
2126 #define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
2127 #define DAC_CR_TEN2_Pos                     (18U)
2128 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
2129 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
2130 
2131 #define DAC_CR_TSEL2_Pos                    (19U)
2132 #define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
2133 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
2134 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
2135 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
2136 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
2137 
2138 #define DAC_CR_WAVE2_Pos                    (22U)
2139 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
2140 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2141 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
2142 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
2143 
2144 #define DAC_CR_MAMP2_Pos                    (24U)
2145 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
2146 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2147 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
2148 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
2149 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
2150 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
2151 
2152 #define DAC_CR_DMAEN2_Pos                   (28U)
2153 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
2154 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
2155 #define DAC_CR_DMAUDRIE2_Pos                (29U)
2156 #define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
2157 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
2158 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2159 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
2160 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
2161 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
2162 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
2163 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
2164 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
2165 
2166 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2167 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
2168 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
2169 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
2170 
2171 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2172 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
2173 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2174 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
2175 
2176 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2177 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
2178 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
2179 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
2180 
2181 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2182 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
2183 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
2184 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
2185 
2186 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2187 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
2188 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
2189 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
2190 
2191 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2192 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
2193 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
2194 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
2195 
2196 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2197 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
2198 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
2199 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
2200 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
2201 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
2202 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
2203 
2204 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2205 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
2206 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2207 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
2208 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
2209 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
2210 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
2211 
2212 /******************  Bit definition for DAC_DHR8RD register  ******************/
2213 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
2214 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
2215 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
2216 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
2217 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
2218 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
2219 
2220 /*******************  Bit definition for DAC_DOR1 register  *******************/
2221 #define DAC_DOR1_DACC1DOR_Pos               (0U)
2222 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
2223 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
2224 
2225 /*******************  Bit definition for DAC_DOR2 register  *******************/
2226 #define DAC_DOR2_DACC2DOR_Pos               (0U)
2227 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
2228 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
2229 
2230 /********************  Bit definition for DAC_SR register  ********************/
2231 #define DAC_SR_DMAUDR1_Pos                  (13U)
2232 #define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
2233 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
2234 #define DAC_SR_DMAUDR2_Pos                  (29U)
2235 #define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
2236 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
2237 
2238 /******************************************************************************/
2239 /*                                                                            */
2240 /*                           Debug MCU (DBGMCU)                               */
2241 /*                                                                            */
2242 /******************************************************************************/
2243 
2244 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
2245 #define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)
2246 #define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
2247 #define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
2248 
2249 #define DBGMCU_IDCODE_REV_ID_Pos                 (16U)
2250 #define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
2251 #define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
2252 #define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
2253 #define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
2254 #define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
2255 #define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
2256 #define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
2257 #define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
2258 #define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
2259 #define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
2260 #define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
2261 #define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
2262 #define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
2263 #define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
2264 #define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
2265 #define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
2266 #define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
2267 #define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
2268 
2269 /******************  Bit definition for DBGMCU_CR register  *******************/
2270 #define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)
2271 #define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
2272 #define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
2273 #define DBGMCU_CR_DBG_STOP_Pos                   (1U)
2274 #define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
2275 #define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
2276 #define DBGMCU_CR_DBG_STANDBY_Pos                (2U)
2277 #define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
2278 #define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
2279 #define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)
2280 #define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
2281 #define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
2282 
2283 #define DBGMCU_CR_TRACE_MODE_Pos                 (6U)
2284 #define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
2285 #define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
2286 #define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
2287 #define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
2288 
2289 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
2290 
2291 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)
2292 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
2293 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
2294 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)
2295 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
2296 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
2297 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)
2298 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
2299 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
2300 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)
2301 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
2302 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
2303 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)
2304 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
2305 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
2306 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)
2307 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
2308 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
2309 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)
2310 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
2311 #define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
2312 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)
2313 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
2314 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
2315 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)
2316 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
2317 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
2318 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
2319 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
2320 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
2321 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
2322 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
2323 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
2324 
2325 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
2326 
2327 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)
2328 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
2329 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
2330 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)
2331 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
2332 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
2333 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)
2334 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
2335 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
2336 
2337 /******************************************************************************/
2338 /*                                                                            */
2339 /*                           DMA Controller (DMA)                             */
2340 /*                                                                            */
2341 /******************************************************************************/
2342 
2343 /*******************  Bit definition for DMA_ISR register  ********************/
2344 #define DMA_ISR_GIF1_Pos                    (0U)
2345 #define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
2346 #define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
2347 #define DMA_ISR_TCIF1_Pos                   (1U)
2348 #define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
2349 #define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
2350 #define DMA_ISR_HTIF1_Pos                   (2U)
2351 #define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
2352 #define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
2353 #define DMA_ISR_TEIF1_Pos                   (3U)
2354 #define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
2355 #define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
2356 #define DMA_ISR_GIF2_Pos                    (4U)
2357 #define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
2358 #define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
2359 #define DMA_ISR_TCIF2_Pos                   (5U)
2360 #define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
2361 #define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
2362 #define DMA_ISR_HTIF2_Pos                   (6U)
2363 #define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
2364 #define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
2365 #define DMA_ISR_TEIF2_Pos                   (7U)
2366 #define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
2367 #define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
2368 #define DMA_ISR_GIF3_Pos                    (8U)
2369 #define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
2370 #define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
2371 #define DMA_ISR_TCIF3_Pos                   (9U)
2372 #define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
2373 #define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
2374 #define DMA_ISR_HTIF3_Pos                   (10U)
2375 #define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
2376 #define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
2377 #define DMA_ISR_TEIF3_Pos                   (11U)
2378 #define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
2379 #define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
2380 #define DMA_ISR_GIF4_Pos                    (12U)
2381 #define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
2382 #define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
2383 #define DMA_ISR_TCIF4_Pos                   (13U)
2384 #define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
2385 #define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
2386 #define DMA_ISR_HTIF4_Pos                   (14U)
2387 #define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
2388 #define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
2389 #define DMA_ISR_TEIF4_Pos                   (15U)
2390 #define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
2391 #define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
2392 #define DMA_ISR_GIF5_Pos                    (16U)
2393 #define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
2394 #define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
2395 #define DMA_ISR_TCIF5_Pos                   (17U)
2396 #define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
2397 #define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
2398 #define DMA_ISR_HTIF5_Pos                   (18U)
2399 #define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
2400 #define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
2401 #define DMA_ISR_TEIF5_Pos                   (19U)
2402 #define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
2403 #define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
2404 #define DMA_ISR_GIF6_Pos                    (20U)
2405 #define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
2406 #define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
2407 #define DMA_ISR_TCIF6_Pos                   (21U)
2408 #define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
2409 #define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
2410 #define DMA_ISR_HTIF6_Pos                   (22U)
2411 #define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
2412 #define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
2413 #define DMA_ISR_TEIF6_Pos                   (23U)
2414 #define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
2415 #define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
2416 #define DMA_ISR_GIF7_Pos                    (24U)
2417 #define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
2418 #define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
2419 #define DMA_ISR_TCIF7_Pos                   (25U)
2420 #define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
2421 #define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
2422 #define DMA_ISR_HTIF7_Pos                   (26U)
2423 #define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
2424 #define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
2425 #define DMA_ISR_TEIF7_Pos                   (27U)
2426 #define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
2427 #define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
2428 
2429 /*******************  Bit definition for DMA_IFCR register  *******************/
2430 #define DMA_IFCR_CGIF1_Pos                  (0U)
2431 #define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
2432 #define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
2433 #define DMA_IFCR_CTCIF1_Pos                 (1U)
2434 #define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
2435 #define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
2436 #define DMA_IFCR_CHTIF1_Pos                 (2U)
2437 #define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
2438 #define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
2439 #define DMA_IFCR_CTEIF1_Pos                 (3U)
2440 #define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
2441 #define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
2442 #define DMA_IFCR_CGIF2_Pos                  (4U)
2443 #define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
2444 #define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
2445 #define DMA_IFCR_CTCIF2_Pos                 (5U)
2446 #define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
2447 #define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
2448 #define DMA_IFCR_CHTIF2_Pos                 (6U)
2449 #define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
2450 #define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
2451 #define DMA_IFCR_CTEIF2_Pos                 (7U)
2452 #define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
2453 #define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
2454 #define DMA_IFCR_CGIF3_Pos                  (8U)
2455 #define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
2456 #define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
2457 #define DMA_IFCR_CTCIF3_Pos                 (9U)
2458 #define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
2459 #define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
2460 #define DMA_IFCR_CHTIF3_Pos                 (10U)
2461 #define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
2462 #define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
2463 #define DMA_IFCR_CTEIF3_Pos                 (11U)
2464 #define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
2465 #define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
2466 #define DMA_IFCR_CGIF4_Pos                  (12U)
2467 #define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
2468 #define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
2469 #define DMA_IFCR_CTCIF4_Pos                 (13U)
2470 #define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
2471 #define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
2472 #define DMA_IFCR_CHTIF4_Pos                 (14U)
2473 #define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
2474 #define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
2475 #define DMA_IFCR_CTEIF4_Pos                 (15U)
2476 #define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
2477 #define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
2478 #define DMA_IFCR_CGIF5_Pos                  (16U)
2479 #define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
2480 #define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
2481 #define DMA_IFCR_CTCIF5_Pos                 (17U)
2482 #define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
2483 #define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
2484 #define DMA_IFCR_CHTIF5_Pos                 (18U)
2485 #define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
2486 #define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
2487 #define DMA_IFCR_CTEIF5_Pos                 (19U)
2488 #define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
2489 #define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
2490 #define DMA_IFCR_CGIF6_Pos                  (20U)
2491 #define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
2492 #define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
2493 #define DMA_IFCR_CTCIF6_Pos                 (21U)
2494 #define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
2495 #define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
2496 #define DMA_IFCR_CHTIF6_Pos                 (22U)
2497 #define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
2498 #define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
2499 #define DMA_IFCR_CTEIF6_Pos                 (23U)
2500 #define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
2501 #define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
2502 #define DMA_IFCR_CGIF7_Pos                  (24U)
2503 #define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
2504 #define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
2505 #define DMA_IFCR_CTCIF7_Pos                 (25U)
2506 #define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
2507 #define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
2508 #define DMA_IFCR_CHTIF7_Pos                 (26U)
2509 #define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
2510 #define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
2511 #define DMA_IFCR_CTEIF7_Pos                 (27U)
2512 #define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
2513 #define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
2514 
2515 /*******************  Bit definition for DMA_CCR register  *******************/
2516 #define DMA_CCR_EN_Pos                      (0U)
2517 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
2518 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
2519 #define DMA_CCR_TCIE_Pos                    (1U)
2520 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
2521 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
2522 #define DMA_CCR_HTIE_Pos                    (2U)
2523 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
2524 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
2525 #define DMA_CCR_TEIE_Pos                    (3U)
2526 #define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
2527 #define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
2528 #define DMA_CCR_DIR_Pos                     (4U)
2529 #define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
2530 #define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
2531 #define DMA_CCR_CIRC_Pos                    (5U)
2532 #define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
2533 #define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
2534 #define DMA_CCR_PINC_Pos                    (6U)
2535 #define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
2536 #define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
2537 #define DMA_CCR_MINC_Pos                    (7U)
2538 #define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
2539 #define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
2540 
2541 #define DMA_CCR_PSIZE_Pos                   (8U)
2542 #define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
2543 #define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
2544 #define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
2545 #define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
2546 
2547 #define DMA_CCR_MSIZE_Pos                   (10U)
2548 #define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
2549 #define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
2550 #define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
2551 #define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
2552 
2553 #define DMA_CCR_PL_Pos                      (12U)
2554 #define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
2555 #define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
2556 #define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
2557 #define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
2558 
2559 #define DMA_CCR_MEM2MEM_Pos                 (14U)
2560 #define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
2561 #define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
2562 
2563 /******************  Bit definition generic for DMA_CNDTR register  *******************/
2564 #define DMA_CNDTR_NDT_Pos                   (0U)
2565 #define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
2566 #define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
2567 
2568 /******************  Bit definition for DMA_CNDTR1 register  ******************/
2569 #define DMA_CNDTR1_NDT_Pos                  (0U)
2570 #define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
2571 #define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
2572 
2573 /******************  Bit definition for DMA_CNDTR2 register  ******************/
2574 #define DMA_CNDTR2_NDT_Pos                  (0U)
2575 #define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
2576 #define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
2577 
2578 /******************  Bit definition for DMA_CNDTR3 register  ******************/
2579 #define DMA_CNDTR3_NDT_Pos                  (0U)
2580 #define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
2581 #define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
2582 
2583 /******************  Bit definition for DMA_CNDTR4 register  ******************/
2584 #define DMA_CNDTR4_NDT_Pos                  (0U)
2585 #define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
2586 #define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
2587 
2588 /******************  Bit definition for DMA_CNDTR5 register  ******************/
2589 #define DMA_CNDTR5_NDT_Pos                  (0U)
2590 #define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
2591 #define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
2592 
2593 /******************  Bit definition for DMA_CNDTR6 register  ******************/
2594 #define DMA_CNDTR6_NDT_Pos                  (0U)
2595 #define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
2596 #define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
2597 
2598 /******************  Bit definition for DMA_CNDTR7 register  ******************/
2599 #define DMA_CNDTR7_NDT_Pos                  (0U)
2600 #define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
2601 #define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
2602 
2603 /******************  Bit definition generic for DMA_CPAR register  ********************/
2604 #define DMA_CPAR_PA_Pos                     (0U)
2605 #define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
2606 #define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
2607 
2608 /******************  Bit definition for DMA_CPAR1 register  *******************/
2609 #define DMA_CPAR1_PA_Pos                    (0U)
2610 #define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
2611 #define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
2612 
2613 /******************  Bit definition for DMA_CPAR2 register  *******************/
2614 #define DMA_CPAR2_PA_Pos                    (0U)
2615 #define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
2616 #define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
2617 
2618 /******************  Bit definition for DMA_CPAR3 register  *******************/
2619 #define DMA_CPAR3_PA_Pos                    (0U)
2620 #define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
2621 #define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
2622 
2623 
2624 /******************  Bit definition for DMA_CPAR4 register  *******************/
2625 #define DMA_CPAR4_PA_Pos                    (0U)
2626 #define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
2627 #define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
2628 
2629 /******************  Bit definition for DMA_CPAR5 register  *******************/
2630 #define DMA_CPAR5_PA_Pos                    (0U)
2631 #define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
2632 #define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
2633 
2634 /******************  Bit definition for DMA_CPAR6 register  *******************/
2635 #define DMA_CPAR6_PA_Pos                    (0U)
2636 #define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
2637 #define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
2638 
2639 
2640 /******************  Bit definition for DMA_CPAR7 register  *******************/
2641 #define DMA_CPAR7_PA_Pos                    (0U)
2642 #define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
2643 #define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
2644 
2645 /******************  Bit definition generic for DMA_CMAR register  ********************/
2646 #define DMA_CMAR_MA_Pos                     (0U)
2647 #define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
2648 #define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
2649 
2650 /******************  Bit definition for DMA_CMAR1 register  *******************/
2651 #define DMA_CMAR1_MA_Pos                    (0U)
2652 #define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
2653 #define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
2654 
2655 /******************  Bit definition for DMA_CMAR2 register  *******************/
2656 #define DMA_CMAR2_MA_Pos                    (0U)
2657 #define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
2658 #define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
2659 
2660 /******************  Bit definition for DMA_CMAR3 register  *******************/
2661 #define DMA_CMAR3_MA_Pos                    (0U)
2662 #define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
2663 #define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
2664 
2665 
2666 /******************  Bit definition for DMA_CMAR4 register  *******************/
2667 #define DMA_CMAR4_MA_Pos                    (0U)
2668 #define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
2669 #define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
2670 
2671 /******************  Bit definition for DMA_CMAR5 register  *******************/
2672 #define DMA_CMAR5_MA_Pos                    (0U)
2673 #define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
2674 #define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
2675 
2676 /******************  Bit definition for DMA_CMAR6 register  *******************/
2677 #define DMA_CMAR6_MA_Pos                    (0U)
2678 #define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
2679 #define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
2680 
2681 /******************  Bit definition for DMA_CMAR7 register  *******************/
2682 #define DMA_CMAR7_MA_Pos                    (0U)
2683 #define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
2684 #define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
2685 
2686 /******************************************************************************/
2687 /*                                                                            */
2688 /*                  External Interrupt/Event Controller (EXTI)                */
2689 /*                                                                            */
2690 /******************************************************************************/
2691 
2692 /*******************  Bit definition for EXTI_IMR register  *******************/
2693 #define EXTI_IMR_MR0_Pos                    (0U)
2694 #define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
2695 #define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
2696 #define EXTI_IMR_MR1_Pos                    (1U)
2697 #define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
2698 #define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
2699 #define EXTI_IMR_MR2_Pos                    (2U)
2700 #define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
2701 #define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
2702 #define EXTI_IMR_MR3_Pos                    (3U)
2703 #define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
2704 #define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
2705 #define EXTI_IMR_MR4_Pos                    (4U)
2706 #define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
2707 #define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
2708 #define EXTI_IMR_MR5_Pos                    (5U)
2709 #define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
2710 #define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
2711 #define EXTI_IMR_MR6_Pos                    (6U)
2712 #define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
2713 #define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
2714 #define EXTI_IMR_MR7_Pos                    (7U)
2715 #define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
2716 #define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
2717 #define EXTI_IMR_MR8_Pos                    (8U)
2718 #define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
2719 #define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
2720 #define EXTI_IMR_MR9_Pos                    (9U)
2721 #define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
2722 #define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
2723 #define EXTI_IMR_MR10_Pos                   (10U)
2724 #define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
2725 #define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
2726 #define EXTI_IMR_MR11_Pos                   (11U)
2727 #define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
2728 #define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
2729 #define EXTI_IMR_MR12_Pos                   (12U)
2730 #define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
2731 #define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
2732 #define EXTI_IMR_MR13_Pos                   (13U)
2733 #define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
2734 #define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
2735 #define EXTI_IMR_MR14_Pos                   (14U)
2736 #define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
2737 #define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
2738 #define EXTI_IMR_MR15_Pos                   (15U)
2739 #define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
2740 #define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
2741 #define EXTI_IMR_MR16_Pos                   (16U)
2742 #define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
2743 #define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
2744 #define EXTI_IMR_MR17_Pos                   (17U)
2745 #define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
2746 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
2747 #define EXTI_IMR_MR18_Pos                   (18U)
2748 #define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
2749 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
2750 #define EXTI_IMR_MR19_Pos                   (19U)
2751 #define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
2752 #define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
2753 #define EXTI_IMR_MR20_Pos                   (20U)
2754 #define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
2755 #define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
2756 #define EXTI_IMR_MR21_Pos                   (21U)
2757 #define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
2758 #define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
2759 #define EXTI_IMR_MR22_Pos                   (22U)
2760 #define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
2761 #define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
2762 #define EXTI_IMR_MR23_Pos                   (23U)
2763 #define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
2764 #define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
2765 
2766 /* References Defines */
2767 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
2768 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
2769 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
2770 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
2771 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
2772 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
2773 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
2774 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
2775 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
2776 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
2777 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
2778 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
2779 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
2780 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
2781 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
2782 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
2783 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
2784 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
2785 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
2786 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
2787 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
2788 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
2789 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
2790 /* Category 3, 4 & 5 */
2791 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
2792 #define EXTI_IMR_IM_Pos                     (0U)
2793 #define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
2794 #define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
2795 
2796 /*******************  Bit definition for EXTI_EMR register  *******************/
2797 #define EXTI_EMR_MR0_Pos                    (0U)
2798 #define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
2799 #define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
2800 #define EXTI_EMR_MR1_Pos                    (1U)
2801 #define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
2802 #define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
2803 #define EXTI_EMR_MR2_Pos                    (2U)
2804 #define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
2805 #define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
2806 #define EXTI_EMR_MR3_Pos                    (3U)
2807 #define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
2808 #define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
2809 #define EXTI_EMR_MR4_Pos                    (4U)
2810 #define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
2811 #define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
2812 #define EXTI_EMR_MR5_Pos                    (5U)
2813 #define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
2814 #define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
2815 #define EXTI_EMR_MR6_Pos                    (6U)
2816 #define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
2817 #define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
2818 #define EXTI_EMR_MR7_Pos                    (7U)
2819 #define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
2820 #define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
2821 #define EXTI_EMR_MR8_Pos                    (8U)
2822 #define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
2823 #define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
2824 #define EXTI_EMR_MR9_Pos                    (9U)
2825 #define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
2826 #define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
2827 #define EXTI_EMR_MR10_Pos                   (10U)
2828 #define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
2829 #define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
2830 #define EXTI_EMR_MR11_Pos                   (11U)
2831 #define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
2832 #define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
2833 #define EXTI_EMR_MR12_Pos                   (12U)
2834 #define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
2835 #define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
2836 #define EXTI_EMR_MR13_Pos                   (13U)
2837 #define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
2838 #define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
2839 #define EXTI_EMR_MR14_Pos                   (14U)
2840 #define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
2841 #define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
2842 #define EXTI_EMR_MR15_Pos                   (15U)
2843 #define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
2844 #define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
2845 #define EXTI_EMR_MR16_Pos                   (16U)
2846 #define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
2847 #define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
2848 #define EXTI_EMR_MR17_Pos                   (17U)
2849 #define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
2850 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
2851 #define EXTI_EMR_MR18_Pos                   (18U)
2852 #define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
2853 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
2854 #define EXTI_EMR_MR19_Pos                   (19U)
2855 #define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
2856 #define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
2857 #define EXTI_EMR_MR20_Pos                   (20U)
2858 #define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
2859 #define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
2860 #define EXTI_EMR_MR21_Pos                   (21U)
2861 #define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
2862 #define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
2863 #define EXTI_EMR_MR22_Pos                   (22U)
2864 #define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
2865 #define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
2866 #define EXTI_EMR_MR23_Pos                   (23U)
2867 #define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
2868 #define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
2869 
2870 /* References Defines */
2871 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
2872 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
2873 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
2874 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
2875 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
2876 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
2877 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
2878 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
2879 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
2880 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
2881 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
2882 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
2883 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
2884 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
2885 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
2886 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
2887 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
2888 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
2889 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
2890 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
2891 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
2892 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
2893 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
2894 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
2895 
2896 /******************  Bit definition for EXTI_RTSR register  *******************/
2897 #define EXTI_RTSR_TR0_Pos                   (0U)
2898 #define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
2899 #define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
2900 #define EXTI_RTSR_TR1_Pos                   (1U)
2901 #define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
2902 #define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
2903 #define EXTI_RTSR_TR2_Pos                   (2U)
2904 #define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
2905 #define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
2906 #define EXTI_RTSR_TR3_Pos                   (3U)
2907 #define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
2908 #define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
2909 #define EXTI_RTSR_TR4_Pos                   (4U)
2910 #define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
2911 #define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
2912 #define EXTI_RTSR_TR5_Pos                   (5U)
2913 #define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
2914 #define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
2915 #define EXTI_RTSR_TR6_Pos                   (6U)
2916 #define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
2917 #define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
2918 #define EXTI_RTSR_TR7_Pos                   (7U)
2919 #define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
2920 #define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
2921 #define EXTI_RTSR_TR8_Pos                   (8U)
2922 #define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
2923 #define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
2924 #define EXTI_RTSR_TR9_Pos                   (9U)
2925 #define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
2926 #define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
2927 #define EXTI_RTSR_TR10_Pos                  (10U)
2928 #define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
2929 #define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
2930 #define EXTI_RTSR_TR11_Pos                  (11U)
2931 #define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
2932 #define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
2933 #define EXTI_RTSR_TR12_Pos                  (12U)
2934 #define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
2935 #define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
2936 #define EXTI_RTSR_TR13_Pos                  (13U)
2937 #define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
2938 #define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
2939 #define EXTI_RTSR_TR14_Pos                  (14U)
2940 #define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
2941 #define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
2942 #define EXTI_RTSR_TR15_Pos                  (15U)
2943 #define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
2944 #define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
2945 #define EXTI_RTSR_TR16_Pos                  (16U)
2946 #define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
2947 #define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
2948 #define EXTI_RTSR_TR17_Pos                  (17U)
2949 #define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
2950 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
2951 #define EXTI_RTSR_TR18_Pos                  (18U)
2952 #define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
2953 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
2954 #define EXTI_RTSR_TR19_Pos                  (19U)
2955 #define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
2956 #define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
2957 #define EXTI_RTSR_TR20_Pos                  (20U)
2958 #define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
2959 #define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
2960 #define EXTI_RTSR_TR21_Pos                  (21U)
2961 #define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
2962 #define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
2963 #define EXTI_RTSR_TR22_Pos                  (22U)
2964 #define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
2965 #define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
2966 #define EXTI_RTSR_TR23_Pos                  (23U)
2967 #define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
2968 #define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
2969 
2970 /* References Defines */
2971 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
2972 #define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
2973 #define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
2974 #define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
2975 #define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
2976 #define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
2977 #define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
2978 #define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
2979 #define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
2980 #define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
2981 #define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
2982 #define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
2983 #define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
2984 #define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
2985 #define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
2986 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
2987 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
2988 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
2989 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
2990 #define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
2991 #define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
2992 #define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
2993 #define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
2994 #define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
2995 
2996 /******************  Bit definition for EXTI_FTSR register  *******************/
2997 #define EXTI_FTSR_TR0_Pos                   (0U)
2998 #define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
2999 #define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
3000 #define EXTI_FTSR_TR1_Pos                   (1U)
3001 #define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
3002 #define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
3003 #define EXTI_FTSR_TR2_Pos                   (2U)
3004 #define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
3005 #define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
3006 #define EXTI_FTSR_TR3_Pos                   (3U)
3007 #define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
3008 #define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
3009 #define EXTI_FTSR_TR4_Pos                   (4U)
3010 #define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
3011 #define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
3012 #define EXTI_FTSR_TR5_Pos                   (5U)
3013 #define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
3014 #define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
3015 #define EXTI_FTSR_TR6_Pos                   (6U)
3016 #define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
3017 #define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
3018 #define EXTI_FTSR_TR7_Pos                   (7U)
3019 #define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
3020 #define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
3021 #define EXTI_FTSR_TR8_Pos                   (8U)
3022 #define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
3023 #define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
3024 #define EXTI_FTSR_TR9_Pos                   (9U)
3025 #define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
3026 #define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
3027 #define EXTI_FTSR_TR10_Pos                  (10U)
3028 #define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
3029 #define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
3030 #define EXTI_FTSR_TR11_Pos                  (11U)
3031 #define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
3032 #define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
3033 #define EXTI_FTSR_TR12_Pos                  (12U)
3034 #define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
3035 #define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
3036 #define EXTI_FTSR_TR13_Pos                  (13U)
3037 #define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
3038 #define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
3039 #define EXTI_FTSR_TR14_Pos                  (14U)
3040 #define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
3041 #define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
3042 #define EXTI_FTSR_TR15_Pos                  (15U)
3043 #define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
3044 #define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
3045 #define EXTI_FTSR_TR16_Pos                  (16U)
3046 #define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
3047 #define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
3048 #define EXTI_FTSR_TR17_Pos                  (17U)
3049 #define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
3050 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
3051 #define EXTI_FTSR_TR18_Pos                  (18U)
3052 #define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
3053 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
3054 #define EXTI_FTSR_TR19_Pos                  (19U)
3055 #define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
3056 #define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
3057 #define EXTI_FTSR_TR20_Pos                  (20U)
3058 #define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
3059 #define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
3060 #define EXTI_FTSR_TR21_Pos                  (21U)
3061 #define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
3062 #define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
3063 #define EXTI_FTSR_TR22_Pos                  (22U)
3064 #define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
3065 #define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
3066 #define EXTI_FTSR_TR23_Pos                  (23U)
3067 #define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
3068 #define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
3069 
3070 /* References Defines */
3071 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
3072 #define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
3073 #define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
3074 #define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
3075 #define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
3076 #define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
3077 #define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
3078 #define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
3079 #define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
3080 #define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
3081 #define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
3082 #define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
3083 #define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
3084 #define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
3085 #define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
3086 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
3087 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
3088 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
3089 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
3090 #define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
3091 #define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
3092 #define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
3093 #define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
3094 #define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
3095 
3096 /******************  Bit definition for EXTI_SWIER register  ******************/
3097 #define EXTI_SWIER_SWIER0_Pos               (0U)
3098 #define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
3099 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
3100 #define EXTI_SWIER_SWIER1_Pos               (1U)
3101 #define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
3102 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
3103 #define EXTI_SWIER_SWIER2_Pos               (2U)
3104 #define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
3105 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
3106 #define EXTI_SWIER_SWIER3_Pos               (3U)
3107 #define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
3108 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
3109 #define EXTI_SWIER_SWIER4_Pos               (4U)
3110 #define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
3111 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
3112 #define EXTI_SWIER_SWIER5_Pos               (5U)
3113 #define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
3114 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
3115 #define EXTI_SWIER_SWIER6_Pos               (6U)
3116 #define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
3117 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
3118 #define EXTI_SWIER_SWIER7_Pos               (7U)
3119 #define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
3120 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
3121 #define EXTI_SWIER_SWIER8_Pos               (8U)
3122 #define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
3123 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
3124 #define EXTI_SWIER_SWIER9_Pos               (9U)
3125 #define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
3126 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
3127 #define EXTI_SWIER_SWIER10_Pos              (10U)
3128 #define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
3129 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
3130 #define EXTI_SWIER_SWIER11_Pos              (11U)
3131 #define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
3132 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
3133 #define EXTI_SWIER_SWIER12_Pos              (12U)
3134 #define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
3135 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
3136 #define EXTI_SWIER_SWIER13_Pos              (13U)
3137 #define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
3138 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
3139 #define EXTI_SWIER_SWIER14_Pos              (14U)
3140 #define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
3141 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
3142 #define EXTI_SWIER_SWIER15_Pos              (15U)
3143 #define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
3144 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
3145 #define EXTI_SWIER_SWIER16_Pos              (16U)
3146 #define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
3147 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
3148 #define EXTI_SWIER_SWIER17_Pos              (17U)
3149 #define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
3150 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
3151 #define EXTI_SWIER_SWIER18_Pos              (18U)
3152 #define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
3153 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
3154 #define EXTI_SWIER_SWIER19_Pos              (19U)
3155 #define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
3156 #define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
3157 #define EXTI_SWIER_SWIER20_Pos              (20U)
3158 #define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
3159 #define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
3160 #define EXTI_SWIER_SWIER21_Pos              (21U)
3161 #define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
3162 #define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
3163 #define EXTI_SWIER_SWIER22_Pos              (22U)
3164 #define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
3165 #define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
3166 #define EXTI_SWIER_SWIER23_Pos              (23U)
3167 #define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
3168 #define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
3169 
3170 /* References Defines */
3171 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
3172 #define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
3173 #define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
3174 #define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
3175 #define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
3176 #define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
3177 #define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
3178 #define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
3179 #define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
3180 #define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
3181 #define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
3182 #define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
3183 #define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
3184 #define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
3185 #define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
3186 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
3187 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
3188 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
3189 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
3190 #define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
3191 #define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
3192 #define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
3193 #define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
3194 #define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
3195 
3196 /*******************  Bit definition for EXTI_PR register  ********************/
3197 #define EXTI_PR_PR0_Pos                     (0U)
3198 #define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
3199 #define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
3200 #define EXTI_PR_PR1_Pos                     (1U)
3201 #define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
3202 #define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
3203 #define EXTI_PR_PR2_Pos                     (2U)
3204 #define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
3205 #define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
3206 #define EXTI_PR_PR3_Pos                     (3U)
3207 #define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
3208 #define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
3209 #define EXTI_PR_PR4_Pos                     (4U)
3210 #define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
3211 #define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
3212 #define EXTI_PR_PR5_Pos                     (5U)
3213 #define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
3214 #define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
3215 #define EXTI_PR_PR6_Pos                     (6U)
3216 #define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
3217 #define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
3218 #define EXTI_PR_PR7_Pos                     (7U)
3219 #define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
3220 #define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
3221 #define EXTI_PR_PR8_Pos                     (8U)
3222 #define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
3223 #define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
3224 #define EXTI_PR_PR9_Pos                     (9U)
3225 #define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
3226 #define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
3227 #define EXTI_PR_PR10_Pos                    (10U)
3228 #define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
3229 #define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
3230 #define EXTI_PR_PR11_Pos                    (11U)
3231 #define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
3232 #define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
3233 #define EXTI_PR_PR12_Pos                    (12U)
3234 #define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
3235 #define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
3236 #define EXTI_PR_PR13_Pos                    (13U)
3237 #define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
3238 #define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
3239 #define EXTI_PR_PR14_Pos                    (14U)
3240 #define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
3241 #define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
3242 #define EXTI_PR_PR15_Pos                    (15U)
3243 #define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
3244 #define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
3245 #define EXTI_PR_PR16_Pos                    (16U)
3246 #define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
3247 #define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
3248 #define EXTI_PR_PR17_Pos                    (17U)
3249 #define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
3250 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
3251 #define EXTI_PR_PR18_Pos                    (18U)
3252 #define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
3253 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
3254 #define EXTI_PR_PR19_Pos                    (19U)
3255 #define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
3256 #define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
3257 #define EXTI_PR_PR20_Pos                    (20U)
3258 #define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
3259 #define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
3260 #define EXTI_PR_PR21_Pos                    (21U)
3261 #define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
3262 #define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
3263 #define EXTI_PR_PR22_Pos                    (22U)
3264 #define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
3265 #define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
3266 #define EXTI_PR_PR23_Pos                    (23U)
3267 #define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
3268 #define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
3269 
3270 /* References Defines */
3271 #define  EXTI_PR_PIF0 EXTI_PR_PR0
3272 #define  EXTI_PR_PIF1 EXTI_PR_PR1
3273 #define  EXTI_PR_PIF2 EXTI_PR_PR2
3274 #define  EXTI_PR_PIF3 EXTI_PR_PR3
3275 #define  EXTI_PR_PIF4 EXTI_PR_PR4
3276 #define  EXTI_PR_PIF5 EXTI_PR_PR5
3277 #define  EXTI_PR_PIF6 EXTI_PR_PR6
3278 #define  EXTI_PR_PIF7 EXTI_PR_PR7
3279 #define  EXTI_PR_PIF8 EXTI_PR_PR8
3280 #define  EXTI_PR_PIF9 EXTI_PR_PR9
3281 #define  EXTI_PR_PIF10 EXTI_PR_PR10
3282 #define  EXTI_PR_PIF11 EXTI_PR_PR11
3283 #define  EXTI_PR_PIF12 EXTI_PR_PR12
3284 #define  EXTI_PR_PIF13 EXTI_PR_PR13
3285 #define  EXTI_PR_PIF14 EXTI_PR_PR14
3286 #define  EXTI_PR_PIF15 EXTI_PR_PR15
3287 #define  EXTI_PR_PIF16 EXTI_PR_PR16
3288 #define  EXTI_PR_PIF17 EXTI_PR_PR17
3289 #define  EXTI_PR_PIF18 EXTI_PR_PR18
3290 #define  EXTI_PR_PIF19 EXTI_PR_PR19
3291 #define  EXTI_PR_PIF20 EXTI_PR_PR20
3292 #define  EXTI_PR_PIF21 EXTI_PR_PR21
3293 #define  EXTI_PR_PIF22 EXTI_PR_PR22
3294 #define  EXTI_PR_PIF23 EXTI_PR_PR23
3295 
3296 /******************************************************************************/
3297 /*                                                                            */
3298 /*                FLASH, DATA EEPROM and Option Bytes Registers               */
3299 /*                        (FLASH, DATA_EEPROM, OB)                            */
3300 /*                                                                            */
3301 /******************************************************************************/
3302 /*
3303  * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
3304  */
3305 #define FLASH_CUT4
3306 
3307 /*******************  Bit definition for FLASH_ACR register  ******************/
3308 #define FLASH_ACR_LATENCY_Pos                (0U)
3309 #define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
3310 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
3311 #define FLASH_ACR_PRFTEN_Pos                 (1U)
3312 #define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
3313 #define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
3314 #define FLASH_ACR_ACC64_Pos                  (2U)
3315 #define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
3316 #define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
3317 #define FLASH_ACR_SLEEP_PD_Pos               (3U)
3318 #define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
3319 #define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
3320 #define FLASH_ACR_RUN_PD_Pos                 (4U)
3321 #define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
3322 #define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
3323 
3324 /*******************  Bit definition for FLASH_PECR register  ******************/
3325 #define FLASH_PECR_PELOCK_Pos                (0U)
3326 #define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
3327 #define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
3328 #define FLASH_PECR_PRGLOCK_Pos               (1U)
3329 #define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
3330 #define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
3331 #define FLASH_PECR_OPTLOCK_Pos               (2U)
3332 #define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
3333 #define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
3334 #define FLASH_PECR_PROG_Pos                  (3U)
3335 #define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
3336 #define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
3337 #define FLASH_PECR_DATA_Pos                  (4U)
3338 #define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
3339 #define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
3340 #define FLASH_PECR_FTDW_Pos                  (8U)
3341 #define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
3342 #define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
3343 #define FLASH_PECR_ERASE_Pos                 (9U)
3344 #define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
3345 #define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
3346 #define FLASH_PECR_FPRG_Pos                  (10U)
3347 #define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
3348 #define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
3349 #define FLASH_PECR_PARALLBANK_Pos            (15U)
3350 #define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
3351 #define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
3352 #define FLASH_PECR_EOPIE_Pos                 (16U)
3353 #define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
3354 #define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */
3355 #define FLASH_PECR_ERRIE_Pos                 (17U)
3356 #define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
3357 #define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */
3358 #define FLASH_PECR_OBL_LAUNCH_Pos            (18U)
3359 #define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
3360 #define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */
3361 
3362 /******************  Bit definition for FLASH_PDKEYR register  ******************/
3363 #define FLASH_PDKEYR_PDKEYR_Pos              (0U)
3364 #define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
3365 #define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
3366 
3367 /******************  Bit definition for FLASH_PEKEYR register  ******************/
3368 #define FLASH_PEKEYR_PEKEYR_Pos              (0U)
3369 #define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
3370 #define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
3371 
3372 /******************  Bit definition for FLASH_PRGKEYR register  ******************/
3373 #define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)
3374 #define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
3375 #define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
3376 
3377 /******************  Bit definition for FLASH_OPTKEYR register  ******************/
3378 #define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)
3379 #define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
3380 #define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
3381 
3382 /******************  Bit definition for FLASH_SR register  *******************/
3383 #define FLASH_SR_BSY_Pos                     (0U)
3384 #define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
3385 #define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
3386 #define FLASH_SR_EOP_Pos                     (1U)
3387 #define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
3388 #define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
3389 #define FLASH_SR_ENDHV_Pos                   (2U)
3390 #define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
3391 #define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
3392 #define FLASH_SR_READY_Pos                   (3U)
3393 #define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
3394 #define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
3395 
3396 #define FLASH_SR_WRPERR_Pos                  (8U)
3397 #define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
3398 #define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
3399 #define FLASH_SR_PGAERR_Pos                  (9U)
3400 #define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
3401 #define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
3402 #define FLASH_SR_SIZERR_Pos                  (10U)
3403 #define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
3404 #define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
3405 #define FLASH_SR_OPTVERR_Pos                 (11U)
3406 #define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
3407 #define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
3408 #define FLASH_SR_OPTVERRUSR_Pos              (12U)
3409 #define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
3410 #define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
3411 
3412 /******************  Bit definition for FLASH_OBR register  *******************/
3413 #define FLASH_OBR_RDPRT_Pos                  (0U)
3414 #define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
3415 #define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
3416 #define FLASH_OBR_BOR_LEV_Pos                (16U)
3417 #define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
3418 #define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
3419 #define FLASH_OBR_USER_Pos                   (20U)
3420 #define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
3421 #define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
3422 #define FLASH_OBR_IWDG_SW_Pos                (20U)
3423 #define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
3424 #define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
3425 #define FLASH_OBR_nRST_STOP_Pos              (21U)
3426 #define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
3427 #define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
3428 #define FLASH_OBR_nRST_STDBY_Pos             (22U)
3429 #define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
3430 #define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
3431 #define FLASH_OBR_nRST_BFB2_Pos              (23U)
3432 #define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
3433 #define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
3434 
3435 /******************  Bit definition for FLASH_WRPR register  ******************/
3436 #define FLASH_WRPR1_WRP_Pos                  (0U)
3437 #define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
3438 #define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
3439 #define FLASH_WRPR2_WRP_Pos                  (0U)
3440 #define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
3441 #define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */
3442 #define FLASH_WRPR3_WRP_Pos                  (0U)
3443 #define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
3444 #define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */
3445 
3446 /******************************************************************************/
3447 /*                                                                            */
3448 /*                       Flexible Static Memory Controller                    */
3449 /*                                                                            */
3450 /******************************************************************************/
3451 /******************  Bit definition for FSMC_BCRx register (x=1..4) *******************/
3452 #define FSMC_BCRx_MBKEN_Pos                 (0U)
3453 #define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
3454 #define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
3455 #define FSMC_BCRx_MUXEN_Pos                 (1U)
3456 #define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
3457 #define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
3458 
3459 #define FSMC_BCRx_MTYP_Pos                  (2U)
3460 #define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
3461 #define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
3462 #define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
3463 #define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
3464 
3465 #define FSMC_BCRx_MWID_Pos                  (4U)
3466 #define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
3467 #define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
3468 #define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
3469 #define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
3470 
3471 #define FSMC_BCRx_FACCEN_Pos                (6U)
3472 #define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
3473 #define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
3474 #define FSMC_BCRx_BURSTEN_Pos               (8U)
3475 #define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
3476 #define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
3477 #define FSMC_BCRx_WAITPOL_Pos               (9U)
3478 #define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
3479 #define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
3480 #define FSMC_BCRx_WRAPMOD_Pos               (10U)
3481 #define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
3482 #define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
3483 #define FSMC_BCRx_WAITCFG_Pos               (11U)
3484 #define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
3485 #define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
3486 #define FSMC_BCRx_WREN_Pos                  (12U)
3487 #define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
3488 #define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
3489 #define FSMC_BCRx_WAITEN_Pos                (13U)
3490 #define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
3491 #define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
3492 #define FSMC_BCRx_EXTMOD_Pos                (14U)
3493 #define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
3494 #define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
3495 #define FSMC_BCRx_ASYNCWAIT_Pos             (15U)
3496 #define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
3497 #define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
3498 #define FSMC_BCRx_CPSIZE_Pos                (16U)
3499 #define FSMC_BCRx_CPSIZE_Msk                (0x7UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00070000 */
3500 #define FSMC_BCRx_CPSIZE                    FSMC_BCRx_CPSIZE_Msk               /*!< Cellular RAM page size */
3501 #define FSMC_BCRx_CPSIZE_0                  (0x1UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00010000 */
3502 #define FSMC_BCRx_CPSIZE_1                  (0x2UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00020000 */
3503 #define FSMC_BCRx_CPSIZE_2                  (0x4UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00040000 */
3504 #define FSMC_BCRx_CBURSTRW_Pos              (19U)
3505 #define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
3506 #define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
3507 
3508 /******************  Bit definition for FSMC_BTRx register (x=1..4)  ******************/
3509 #define FSMC_BTRx_ADDSET_Pos                (0U)
3510 #define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
3511 #define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
3512 #define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
3513 #define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
3514 #define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
3515 #define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
3516 
3517 #define FSMC_BTRx_ADDHLD_Pos                (4U)
3518 #define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
3519 #define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
3520 #define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
3521 #define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
3522 #define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
3523 #define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
3524 
3525 #define FSMC_BTRx_DATAST_Pos                (8U)
3526 #define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
3527 #define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [7:0] bits (Data-phase duration) */
3528 #define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
3529 #define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
3530 #define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
3531 #define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
3532 #define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
3533 #define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
3534 #define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
3535 #define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
3536 
3537 #define FSMC_BTRx_BUSTURN_Pos               (16U)
3538 #define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
3539 #define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
3540 #define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
3541 #define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
3542 #define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
3543 #define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
3544 
3545 #define FSMC_BTRx_CLKDIV_Pos                (20U)
3546 #define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
3547 #define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
3548 #define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
3549 #define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
3550 #define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
3551 #define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
3552 
3553 #define FSMC_BTRx_DATLAT_Pos                (24U)
3554 #define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
3555 #define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
3556 #define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
3557 #define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
3558 #define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
3559 #define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
3560 
3561 #define FSMC_BTRx_ACCMOD_Pos                (28U)
3562 #define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
3563 #define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
3564 #define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
3565 #define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
3566 
3567 /******************  Bit definition for FSMC_BWTRx register (x=1..4) ******************/
3568 #define FSMC_BWTRx_ADDSET_Pos               (0U)
3569 #define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
3570 #define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
3571 #define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
3572 #define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
3573 #define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
3574 #define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
3575 
3576 #define FSMC_BWTRx_ADDHLD_Pos               (4U)
3577 #define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
3578 #define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
3579 #define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
3580 #define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
3581 #define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
3582 #define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
3583 
3584 #define FSMC_BWTRx_DATAST_Pos               (8U)
3585 #define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
3586 #define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [7:0] bits (Data-phase duration) */
3587 #define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
3588 #define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
3589 #define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
3590 #define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
3591 #define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
3592 #define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
3593 #define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
3594 #define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
3595 
3596 #define FSMC_BWTRx_BUSTURN_Pos              (16U)
3597 #define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
3598 #define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
3599 #define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
3600 #define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
3601 #define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
3602 #define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
3603 
3604 #define FSMC_BWTRx_ACCMOD_Pos               (28U)
3605 #define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
3606 #define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
3607 #define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
3608 #define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
3609 
3610 /******************************************************************************/
3611 /*                                                                            */
3612 /*                            General Purpose I/O                             */
3613 /*                                                                            */
3614 /******************************************************************************/
3615 /******************  Bits definition for GPIO_MODER register  *****************/
3616 #define GPIO_MODER_MODER0_Pos                (0U)
3617 #define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
3618 #define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk
3619 #define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
3620 #define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
3621 
3622 #define GPIO_MODER_MODER1_Pos                (2U)
3623 #define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
3624 #define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk
3625 #define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
3626 #define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
3627 
3628 #define GPIO_MODER_MODER2_Pos                (4U)
3629 #define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
3630 #define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk
3631 #define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
3632 #define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
3633 
3634 #define GPIO_MODER_MODER3_Pos                (6U)
3635 #define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
3636 #define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk
3637 #define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
3638 #define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
3639 
3640 #define GPIO_MODER_MODER4_Pos                (8U)
3641 #define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
3642 #define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk
3643 #define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
3644 #define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
3645 
3646 #define GPIO_MODER_MODER5_Pos                (10U)
3647 #define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
3648 #define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk
3649 #define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
3650 #define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
3651 
3652 #define GPIO_MODER_MODER6_Pos                (12U)
3653 #define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
3654 #define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk
3655 #define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
3656 #define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
3657 
3658 #define GPIO_MODER_MODER7_Pos                (14U)
3659 #define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
3660 #define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk
3661 #define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
3662 #define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
3663 
3664 #define GPIO_MODER_MODER8_Pos                (16U)
3665 #define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
3666 #define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk
3667 #define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
3668 #define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
3669 
3670 #define GPIO_MODER_MODER9_Pos                (18U)
3671 #define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
3672 #define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk
3673 #define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
3674 #define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
3675 
3676 #define GPIO_MODER_MODER10_Pos               (20U)
3677 #define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
3678 #define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk
3679 #define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
3680 #define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
3681 
3682 #define GPIO_MODER_MODER11_Pos               (22U)
3683 #define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
3684 #define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk
3685 #define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
3686 #define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
3687 
3688 #define GPIO_MODER_MODER12_Pos               (24U)
3689 #define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
3690 #define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk
3691 #define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
3692 #define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
3693 
3694 #define GPIO_MODER_MODER13_Pos               (26U)
3695 #define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
3696 #define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk
3697 #define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
3698 #define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
3699 
3700 #define GPIO_MODER_MODER14_Pos               (28U)
3701 #define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
3702 #define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk
3703 #define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
3704 #define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
3705 
3706 #define GPIO_MODER_MODER15_Pos               (30U)
3707 #define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
3708 #define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk
3709 #define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
3710 #define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
3711 
3712 /******************  Bits definition for GPIO_OTYPER register  ****************/
3713 #define GPIO_OTYPER_OT_0                     (0x00000001U)
3714 #define GPIO_OTYPER_OT_1                     (0x00000002U)
3715 #define GPIO_OTYPER_OT_2                     (0x00000004U)
3716 #define GPIO_OTYPER_OT_3                     (0x00000008U)
3717 #define GPIO_OTYPER_OT_4                     (0x00000010U)
3718 #define GPIO_OTYPER_OT_5                     (0x00000020U)
3719 #define GPIO_OTYPER_OT_6                     (0x00000040U)
3720 #define GPIO_OTYPER_OT_7                     (0x00000080U)
3721 #define GPIO_OTYPER_OT_8                     (0x00000100U)
3722 #define GPIO_OTYPER_OT_9                     (0x00000200U)
3723 #define GPIO_OTYPER_OT_10                    (0x00000400U)
3724 #define GPIO_OTYPER_OT_11                    (0x00000800U)
3725 #define GPIO_OTYPER_OT_12                    (0x00001000U)
3726 #define GPIO_OTYPER_OT_13                    (0x00002000U)
3727 #define GPIO_OTYPER_OT_14                    (0x00004000U)
3728 #define GPIO_OTYPER_OT_15                    (0x00008000U)
3729 
3730 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3731 #define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)
3732 #define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
3733 #define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk
3734 #define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
3735 #define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
3736 
3737 #define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)
3738 #define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
3739 #define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk
3740 #define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
3741 #define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
3742 
3743 #define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)
3744 #define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
3745 #define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk
3746 #define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
3747 #define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
3748 
3749 #define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)
3750 #define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
3751 #define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk
3752 #define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
3753 #define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
3754 
3755 #define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)
3756 #define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
3757 #define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk
3758 #define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
3759 #define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
3760 
3761 #define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)
3762 #define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
3763 #define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk
3764 #define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
3765 #define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
3766 
3767 #define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)
3768 #define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
3769 #define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk
3770 #define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
3771 #define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
3772 
3773 #define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)
3774 #define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
3775 #define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk
3776 #define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
3777 #define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
3778 
3779 #define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)
3780 #define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
3781 #define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk
3782 #define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
3783 #define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
3784 
3785 #define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)
3786 #define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
3787 #define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk
3788 #define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
3789 #define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
3790 
3791 #define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)
3792 #define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
3793 #define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk
3794 #define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
3795 #define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
3796 
3797 #define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)
3798 #define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
3799 #define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk
3800 #define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
3801 #define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
3802 
3803 #define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)
3804 #define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
3805 #define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk
3806 #define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
3807 #define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
3808 
3809 #define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)
3810 #define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
3811 #define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk
3812 #define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
3813 #define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
3814 
3815 #define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)
3816 #define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
3817 #define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk
3818 #define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
3819 #define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
3820 
3821 #define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)
3822 #define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
3823 #define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk
3824 #define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
3825 #define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
3826 
3827 /******************  Bits definition for GPIO_PUPDR register  *****************/
3828 #define GPIO_PUPDR_PUPDR0_Pos                (0U)
3829 #define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
3830 #define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk
3831 #define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
3832 #define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
3833 
3834 #define GPIO_PUPDR_PUPDR1_Pos                (2U)
3835 #define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
3836 #define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk
3837 #define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
3838 #define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
3839 
3840 #define GPIO_PUPDR_PUPDR2_Pos                (4U)
3841 #define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
3842 #define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk
3843 #define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
3844 #define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
3845 
3846 #define GPIO_PUPDR_PUPDR3_Pos                (6U)
3847 #define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
3848 #define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk
3849 #define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
3850 #define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
3851 
3852 #define GPIO_PUPDR_PUPDR4_Pos                (8U)
3853 #define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
3854 #define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk
3855 #define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
3856 #define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
3857 
3858 #define GPIO_PUPDR_PUPDR5_Pos                (10U)
3859 #define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
3860 #define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk
3861 #define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
3862 #define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
3863 
3864 #define GPIO_PUPDR_PUPDR6_Pos                (12U)
3865 #define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
3866 #define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk
3867 #define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
3868 #define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
3869 
3870 #define GPIO_PUPDR_PUPDR7_Pos                (14U)
3871 #define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
3872 #define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk
3873 #define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
3874 #define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
3875 
3876 #define GPIO_PUPDR_PUPDR8_Pos                (16U)
3877 #define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
3878 #define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk
3879 #define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
3880 #define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
3881 
3882 #define GPIO_PUPDR_PUPDR9_Pos                (18U)
3883 #define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
3884 #define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk
3885 #define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
3886 #define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
3887 
3888 #define GPIO_PUPDR_PUPDR10_Pos               (20U)
3889 #define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
3890 #define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk
3891 #define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
3892 #define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
3893 
3894 #define GPIO_PUPDR_PUPDR11_Pos               (22U)
3895 #define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
3896 #define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk
3897 #define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
3898 #define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
3899 
3900 #define GPIO_PUPDR_PUPDR12_Pos               (24U)
3901 #define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
3902 #define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk
3903 #define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
3904 #define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
3905 
3906 #define GPIO_PUPDR_PUPDR13_Pos               (26U)
3907 #define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
3908 #define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk
3909 #define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
3910 #define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
3911 
3912 #define GPIO_PUPDR_PUPDR14_Pos               (28U)
3913 #define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
3914 #define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk
3915 #define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
3916 #define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
3917 #define GPIO_PUPDR_PUPDR15_Pos               (30U)
3918 #define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
3919 #define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk
3920 #define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
3921 #define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
3922 
3923 /******************  Bits definition for GPIO_IDR register  *******************/
3924 #define GPIO_IDR_IDR_0                       (0x00000001U)
3925 #define GPIO_IDR_IDR_1                       (0x00000002U)
3926 #define GPIO_IDR_IDR_2                       (0x00000004U)
3927 #define GPIO_IDR_IDR_3                       (0x00000008U)
3928 #define GPIO_IDR_IDR_4                       (0x00000010U)
3929 #define GPIO_IDR_IDR_5                       (0x00000020U)
3930 #define GPIO_IDR_IDR_6                       (0x00000040U)
3931 #define GPIO_IDR_IDR_7                       (0x00000080U)
3932 #define GPIO_IDR_IDR_8                       (0x00000100U)
3933 #define GPIO_IDR_IDR_9                       (0x00000200U)
3934 #define GPIO_IDR_IDR_10                      (0x00000400U)
3935 #define GPIO_IDR_IDR_11                      (0x00000800U)
3936 #define GPIO_IDR_IDR_12                      (0x00001000U)
3937 #define GPIO_IDR_IDR_13                      (0x00002000U)
3938 #define GPIO_IDR_IDR_14                      (0x00004000U)
3939 #define GPIO_IDR_IDR_15                      (0x00008000U)
3940 
3941 /******************  Bits definition for GPIO_ODR register  *******************/
3942 #define GPIO_ODR_ODR_0                       (0x00000001U)
3943 #define GPIO_ODR_ODR_1                       (0x00000002U)
3944 #define GPIO_ODR_ODR_2                       (0x00000004U)
3945 #define GPIO_ODR_ODR_3                       (0x00000008U)
3946 #define GPIO_ODR_ODR_4                       (0x00000010U)
3947 #define GPIO_ODR_ODR_5                       (0x00000020U)
3948 #define GPIO_ODR_ODR_6                       (0x00000040U)
3949 #define GPIO_ODR_ODR_7                       (0x00000080U)
3950 #define GPIO_ODR_ODR_8                       (0x00000100U)
3951 #define GPIO_ODR_ODR_9                       (0x00000200U)
3952 #define GPIO_ODR_ODR_10                      (0x00000400U)
3953 #define GPIO_ODR_ODR_11                      (0x00000800U)
3954 #define GPIO_ODR_ODR_12                      (0x00001000U)
3955 #define GPIO_ODR_ODR_13                      (0x00002000U)
3956 #define GPIO_ODR_ODR_14                      (0x00004000U)
3957 #define GPIO_ODR_ODR_15                      (0x00008000U)
3958 
3959 /******************  Bits definition for GPIO_BSRR register  ******************/
3960 #define GPIO_BSRR_BS_0                       (0x00000001U)
3961 #define GPIO_BSRR_BS_1                       (0x00000002U)
3962 #define GPIO_BSRR_BS_2                       (0x00000004U)
3963 #define GPIO_BSRR_BS_3                       (0x00000008U)
3964 #define GPIO_BSRR_BS_4                       (0x00000010U)
3965 #define GPIO_BSRR_BS_5                       (0x00000020U)
3966 #define GPIO_BSRR_BS_6                       (0x00000040U)
3967 #define GPIO_BSRR_BS_7                       (0x00000080U)
3968 #define GPIO_BSRR_BS_8                       (0x00000100U)
3969 #define GPIO_BSRR_BS_9                       (0x00000200U)
3970 #define GPIO_BSRR_BS_10                      (0x00000400U)
3971 #define GPIO_BSRR_BS_11                      (0x00000800U)
3972 #define GPIO_BSRR_BS_12                      (0x00001000U)
3973 #define GPIO_BSRR_BS_13                      (0x00002000U)
3974 #define GPIO_BSRR_BS_14                      (0x00004000U)
3975 #define GPIO_BSRR_BS_15                      (0x00008000U)
3976 #define GPIO_BSRR_BR_0                       (0x00010000U)
3977 #define GPIO_BSRR_BR_1                       (0x00020000U)
3978 #define GPIO_BSRR_BR_2                       (0x00040000U)
3979 #define GPIO_BSRR_BR_3                       (0x00080000U)
3980 #define GPIO_BSRR_BR_4                       (0x00100000U)
3981 #define GPIO_BSRR_BR_5                       (0x00200000U)
3982 #define GPIO_BSRR_BR_6                       (0x00400000U)
3983 #define GPIO_BSRR_BR_7                       (0x00800000U)
3984 #define GPIO_BSRR_BR_8                       (0x01000000U)
3985 #define GPIO_BSRR_BR_9                       (0x02000000U)
3986 #define GPIO_BSRR_BR_10                      (0x04000000U)
3987 #define GPIO_BSRR_BR_11                      (0x08000000U)
3988 #define GPIO_BSRR_BR_12                      (0x10000000U)
3989 #define GPIO_BSRR_BR_13                      (0x20000000U)
3990 #define GPIO_BSRR_BR_14                      (0x40000000U)
3991 #define GPIO_BSRR_BR_15                      (0x80000000U)
3992 
3993 /****************** Bit definition for GPIO_LCKR register  ********************/
3994 #define GPIO_LCKR_LCK0_Pos                   (0U)
3995 #define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
3996 #define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk
3997 #define GPIO_LCKR_LCK1_Pos                   (1U)
3998 #define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
3999 #define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk
4000 #define GPIO_LCKR_LCK2_Pos                   (2U)
4001 #define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
4002 #define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk
4003 #define GPIO_LCKR_LCK3_Pos                   (3U)
4004 #define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
4005 #define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk
4006 #define GPIO_LCKR_LCK4_Pos                   (4U)
4007 #define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
4008 #define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk
4009 #define GPIO_LCKR_LCK5_Pos                   (5U)
4010 #define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
4011 #define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk
4012 #define GPIO_LCKR_LCK6_Pos                   (6U)
4013 #define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
4014 #define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk
4015 #define GPIO_LCKR_LCK7_Pos                   (7U)
4016 #define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
4017 #define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk
4018 #define GPIO_LCKR_LCK8_Pos                   (8U)
4019 #define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
4020 #define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk
4021 #define GPIO_LCKR_LCK9_Pos                   (9U)
4022 #define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
4023 #define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk
4024 #define GPIO_LCKR_LCK10_Pos                  (10U)
4025 #define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
4026 #define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk
4027 #define GPIO_LCKR_LCK11_Pos                  (11U)
4028 #define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
4029 #define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk
4030 #define GPIO_LCKR_LCK12_Pos                  (12U)
4031 #define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
4032 #define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk
4033 #define GPIO_LCKR_LCK13_Pos                  (13U)
4034 #define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
4035 #define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk
4036 #define GPIO_LCKR_LCK14_Pos                  (14U)
4037 #define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
4038 #define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk
4039 #define GPIO_LCKR_LCK15_Pos                  (15U)
4040 #define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
4041 #define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk
4042 #define GPIO_LCKR_LCKK_Pos                   (16U)
4043 #define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
4044 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk
4045 
4046 /****************** Bit definition for GPIO_AFRL register  ********************/
4047 #define GPIO_AFRL_AFSEL0_Pos                  (0U)
4048 #define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
4049 #define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk
4050 #define GPIO_AFRL_AFSEL1_Pos                  (4U)
4051 #define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
4052 #define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk
4053 #define GPIO_AFRL_AFSEL2_Pos                  (8U)
4054 #define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
4055 #define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk
4056 #define GPIO_AFRL_AFSEL3_Pos                  (12U)
4057 #define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
4058 #define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk
4059 #define GPIO_AFRL_AFSEL4_Pos                  (16U)
4060 #define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
4061 #define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk
4062 #define GPIO_AFRL_AFSEL5_Pos                  (20U)
4063 #define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
4064 #define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk
4065 #define GPIO_AFRL_AFSEL6_Pos                  (24U)
4066 #define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
4067 #define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk
4068 #define GPIO_AFRL_AFSEL7_Pos                  (28U)
4069 #define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
4070 #define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk
4071 
4072 /****************** Bit definition for GPIO_AFRH register  ********************/
4073 #define GPIO_AFRH_AFSEL8_Pos                  (0U)
4074 #define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
4075 #define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk
4076 #define GPIO_AFRH_AFSEL9_Pos                  (4U)
4077 #define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
4078 #define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk
4079 #define GPIO_AFRH_AFSEL10_Pos                  (8U)
4080 #define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
4081 #define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk
4082 #define GPIO_AFRH_AFSEL11_Pos                  (12U)
4083 #define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
4084 #define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk
4085 #define GPIO_AFRH_AFSEL12_Pos                  (16U)
4086 #define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
4087 #define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk
4088 #define GPIO_AFRH_AFSEL13_Pos                  (20U)
4089 #define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
4090 #define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk
4091 #define GPIO_AFRH_AFSEL14_Pos                  (24U)
4092 #define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
4093 #define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk
4094 #define GPIO_AFRH_AFSEL15_Pos                  (28U)
4095 #define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
4096 #define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk
4097 
4098 /****************** Bit definition for GPIO_BRR register  *********************/
4099 #define GPIO_BRR_BR_0                        (0x00000001U)
4100 #define GPIO_BRR_BR_1                        (0x00000002U)
4101 #define GPIO_BRR_BR_2                        (0x00000004U)
4102 #define GPIO_BRR_BR_3                        (0x00000008U)
4103 #define GPIO_BRR_BR_4                        (0x00000010U)
4104 #define GPIO_BRR_BR_5                        (0x00000020U)
4105 #define GPIO_BRR_BR_6                        (0x00000040U)
4106 #define GPIO_BRR_BR_7                        (0x00000080U)
4107 #define GPIO_BRR_BR_8                        (0x00000100U)
4108 #define GPIO_BRR_BR_9                        (0x00000200U)
4109 #define GPIO_BRR_BR_10                       (0x00000400U)
4110 #define GPIO_BRR_BR_11                       (0x00000800U)
4111 #define GPIO_BRR_BR_12                       (0x00001000U)
4112 #define GPIO_BRR_BR_13                       (0x00002000U)
4113 #define GPIO_BRR_BR_14                       (0x00004000U)
4114 #define GPIO_BRR_BR_15                       (0x00008000U)
4115 
4116 /******************************************************************************/
4117 /*                                                                            */
4118 /*                   Inter-integrated Circuit Interface (I2C)                 */
4119 /*                                                                            */
4120 /******************************************************************************/
4121 
4122 /*******************  Bit definition for I2C_CR1 register  ********************/
4123 #define I2C_CR1_PE_Pos                      (0U)
4124 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
4125 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
4126 #define I2C_CR1_SMBUS_Pos                   (1U)
4127 #define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
4128 #define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
4129 #define I2C_CR1_SMBTYPE_Pos                 (3U)
4130 #define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
4131 #define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
4132 #define I2C_CR1_ENARP_Pos                   (4U)
4133 #define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
4134 #define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
4135 #define I2C_CR1_ENPEC_Pos                   (5U)
4136 #define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
4137 #define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
4138 #define I2C_CR1_ENGC_Pos                    (6U)
4139 #define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
4140 #define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
4141 #define I2C_CR1_NOSTRETCH_Pos               (7U)
4142 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
4143 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
4144 #define I2C_CR1_START_Pos                   (8U)
4145 #define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
4146 #define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
4147 #define I2C_CR1_STOP_Pos                    (9U)
4148 #define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
4149 #define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
4150 #define I2C_CR1_ACK_Pos                     (10U)
4151 #define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
4152 #define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
4153 #define I2C_CR1_POS_Pos                     (11U)
4154 #define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
4155 #define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
4156 #define I2C_CR1_PEC_Pos                     (12U)
4157 #define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
4158 #define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
4159 #define I2C_CR1_ALERT_Pos                   (13U)
4160 #define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
4161 #define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
4162 #define I2C_CR1_SWRST_Pos                   (15U)
4163 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
4164 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
4165 
4166 /*******************  Bit definition for I2C_CR2 register  ********************/
4167 #define I2C_CR2_FREQ_Pos                    (0U)
4168 #define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
4169 #define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
4170 #define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
4171 #define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
4172 #define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
4173 #define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
4174 #define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
4175 #define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
4176 
4177 #define I2C_CR2_ITERREN_Pos                 (8U)
4178 #define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
4179 #define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
4180 #define I2C_CR2_ITEVTEN_Pos                 (9U)
4181 #define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
4182 #define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
4183 #define I2C_CR2_ITBUFEN_Pos                 (10U)
4184 #define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
4185 #define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
4186 #define I2C_CR2_DMAEN_Pos                   (11U)
4187 #define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
4188 #define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
4189 #define I2C_CR2_LAST_Pos                    (12U)
4190 #define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
4191 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
4192 
4193 /*******************  Bit definition for I2C_OAR1 register  *******************/
4194 #define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
4195 #define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
4196 
4197 #define I2C_OAR1_ADD0_Pos                   (0U)
4198 #define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
4199 #define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
4200 #define I2C_OAR1_ADD1_Pos                   (1U)
4201 #define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
4202 #define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
4203 #define I2C_OAR1_ADD2_Pos                   (2U)
4204 #define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
4205 #define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
4206 #define I2C_OAR1_ADD3_Pos                   (3U)
4207 #define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
4208 #define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
4209 #define I2C_OAR1_ADD4_Pos                   (4U)
4210 #define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
4211 #define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
4212 #define I2C_OAR1_ADD5_Pos                   (5U)
4213 #define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
4214 #define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
4215 #define I2C_OAR1_ADD6_Pos                   (6U)
4216 #define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
4217 #define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
4218 #define I2C_OAR1_ADD7_Pos                   (7U)
4219 #define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
4220 #define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
4221 #define I2C_OAR1_ADD8_Pos                   (8U)
4222 #define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
4223 #define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
4224 #define I2C_OAR1_ADD9_Pos                   (9U)
4225 #define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
4226 #define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
4227 
4228 #define I2C_OAR1_ADDMODE_Pos                (15U)
4229 #define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
4230 #define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
4231 
4232 /*******************  Bit definition for I2C_OAR2 register  *******************/
4233 #define I2C_OAR2_ENDUAL_Pos                 (0U)
4234 #define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
4235 #define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
4236 #define I2C_OAR2_ADD2_Pos                   (1U)
4237 #define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
4238 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
4239 
4240 /********************  Bit definition for I2C_DR register  ********************/
4241 #define I2C_DR_DR_Pos                       (0U)
4242 #define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
4243 #define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
4244 
4245 /*******************  Bit definition for I2C_SR1 register  ********************/
4246 #define I2C_SR1_SB_Pos                      (0U)
4247 #define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
4248 #define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
4249 #define I2C_SR1_ADDR_Pos                    (1U)
4250 #define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
4251 #define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
4252 #define I2C_SR1_BTF_Pos                     (2U)
4253 #define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
4254 #define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
4255 #define I2C_SR1_ADD10_Pos                   (3U)
4256 #define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
4257 #define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
4258 #define I2C_SR1_STOPF_Pos                   (4U)
4259 #define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
4260 #define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
4261 #define I2C_SR1_RXNE_Pos                    (6U)
4262 #define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
4263 #define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
4264 #define I2C_SR1_TXE_Pos                     (7U)
4265 #define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
4266 #define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
4267 #define I2C_SR1_BERR_Pos                    (8U)
4268 #define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
4269 #define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
4270 #define I2C_SR1_ARLO_Pos                    (9U)
4271 #define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
4272 #define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
4273 #define I2C_SR1_AF_Pos                      (10U)
4274 #define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
4275 #define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
4276 #define I2C_SR1_OVR_Pos                     (11U)
4277 #define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
4278 #define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
4279 #define I2C_SR1_PECERR_Pos                  (12U)
4280 #define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
4281 #define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
4282 #define I2C_SR1_TIMEOUT_Pos                 (14U)
4283 #define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
4284 #define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
4285 #define I2C_SR1_SMBALERT_Pos                (15U)
4286 #define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
4287 #define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
4288 
4289 /*******************  Bit definition for I2C_SR2 register  ********************/
4290 #define I2C_SR2_MSL_Pos                     (0U)
4291 #define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
4292 #define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
4293 #define I2C_SR2_BUSY_Pos                    (1U)
4294 #define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
4295 #define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
4296 #define I2C_SR2_TRA_Pos                     (2U)
4297 #define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
4298 #define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
4299 #define I2C_SR2_GENCALL_Pos                 (4U)
4300 #define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
4301 #define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
4302 #define I2C_SR2_SMBDEFAULT_Pos              (5U)
4303 #define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
4304 #define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
4305 #define I2C_SR2_SMBHOST_Pos                 (6U)
4306 #define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
4307 #define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
4308 #define I2C_SR2_DUALF_Pos                   (7U)
4309 #define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
4310 #define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
4311 #define I2C_SR2_PEC_Pos                     (8U)
4312 #define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
4313 #define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
4314 
4315 /*******************  Bit definition for I2C_CCR register  ********************/
4316 #define I2C_CCR_CCR_Pos                     (0U)
4317 #define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
4318 #define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
4319 #define I2C_CCR_DUTY_Pos                    (14U)
4320 #define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
4321 #define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
4322 #define I2C_CCR_FS_Pos                      (15U)
4323 #define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
4324 #define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
4325 
4326 /******************  Bit definition for I2C_TRISE register  *******************/
4327 #define I2C_TRISE_TRISE_Pos                 (0U)
4328 #define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
4329 #define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
4330 
4331 /******************************************************************************/
4332 /*                                                                            */
4333 /*                        Independent WATCHDOG (IWDG)                         */
4334 /*                                                                            */
4335 /******************************************************************************/
4336 
4337 /*******************  Bit definition for IWDG_KR register  ********************/
4338 #define IWDG_KR_KEY_Pos                     (0U)
4339 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
4340 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
4341 
4342 /*******************  Bit definition for IWDG_PR register  ********************/
4343 #define IWDG_PR_PR_Pos                      (0U)
4344 #define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
4345 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
4346 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
4347 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
4348 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
4349 
4350 /*******************  Bit definition for IWDG_RLR register  *******************/
4351 #define IWDG_RLR_RL_Pos                     (0U)
4352 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
4353 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
4354 
4355 /*******************  Bit definition for IWDG_SR register  ********************/
4356 #define IWDG_SR_PVU_Pos                     (0U)
4357 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
4358 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
4359 #define IWDG_SR_RVU_Pos                     (1U)
4360 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
4361 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
4362 
4363 /******************************************************************************/
4364 /*                                                                            */
4365 /*                          LCD Controller (LCD)                              */
4366 /*                                                                            */
4367 /******************************************************************************/
4368 
4369 /*******************  Bit definition for LCD_CR register  *********************/
4370 #define LCD_CR_LCDEN_Pos           (0U)
4371 #define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
4372 #define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
4373 #define LCD_CR_VSEL_Pos            (1U)
4374 #define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
4375 #define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
4376 
4377 #define LCD_CR_DUTY_Pos            (2U)
4378 #define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
4379 #define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
4380 #define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
4381 #define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
4382 #define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
4383 
4384 #define LCD_CR_BIAS_Pos            (5U)
4385 #define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
4386 #define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
4387 #define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
4388 #define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
4389 
4390 #define LCD_CR_MUX_SEG_Pos         (7U)
4391 #define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
4392 #define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
4393 
4394 /*******************  Bit definition for LCD_FCR register  ********************/
4395 #define LCD_FCR_HD_Pos             (0U)
4396 #define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
4397 #define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
4398 #define LCD_FCR_SOFIE_Pos          (1U)
4399 #define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
4400 #define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
4401 #define LCD_FCR_UDDIE_Pos          (3U)
4402 #define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
4403 #define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
4404 
4405 #define LCD_FCR_PON_Pos            (4U)
4406 #define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
4407 #define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Pulse ON Duration) */
4408 #define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
4409 #define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
4410 #define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
4411 
4412 #define LCD_FCR_DEAD_Pos           (7U)
4413 #define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
4414 #define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
4415 #define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
4416 #define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
4417 #define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
4418 
4419 #define LCD_FCR_CC_Pos             (10U)
4420 #define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
4421 #define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
4422 #define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
4423 #define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
4424 #define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
4425 
4426 #define LCD_FCR_BLINKF_Pos         (13U)
4427 #define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
4428 #define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
4429 #define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
4430 #define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
4431 #define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
4432 
4433 #define LCD_FCR_BLINK_Pos          (16U)
4434 #define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
4435 #define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
4436 #define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
4437 #define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
4438 
4439 #define LCD_FCR_DIV_Pos            (18U)
4440 #define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
4441 #define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
4442 #define LCD_FCR_PS_Pos             (22U)
4443 #define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
4444 #define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
4445 
4446 /*******************  Bit definition for LCD_SR register  *********************/
4447 #define LCD_SR_ENS_Pos             (0U)
4448 #define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
4449 #define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
4450 #define LCD_SR_SOF_Pos             (1U)
4451 #define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
4452 #define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
4453 #define LCD_SR_UDR_Pos             (2U)
4454 #define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
4455 #define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
4456 #define LCD_SR_UDD_Pos             (3U)
4457 #define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
4458 #define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
4459 #define LCD_SR_RDY_Pos             (4U)
4460 #define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
4461 #define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
4462 #define LCD_SR_FCRSR_Pos           (5U)
4463 #define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
4464 #define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
4465 
4466 /*******************  Bit definition for LCD_CLR register  ********************/
4467 #define LCD_CLR_SOFC_Pos           (1U)
4468 #define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
4469 #define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
4470 #define LCD_CLR_UDDC_Pos           (3U)
4471 #define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
4472 #define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
4473 
4474 /*******************  Bit definition for LCD_RAM register  ********************/
4475 #define LCD_RAM_SEGMENT_DATA_Pos   (0U)
4476 #define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
4477 #define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
4478 
4479 /******************************************************************************/
4480 /*                                                                            */
4481 /*                          Power Control (PWR)                               */
4482 /*                                                                            */
4483 /******************************************************************************/
4484 
4485 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
4486 
4487 /********************  Bit definition for PWR_CR register  ********************/
4488 #define PWR_CR_LPSDSR_Pos                   (0U)
4489 #define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
4490 #define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
4491 #define PWR_CR_PDDS_Pos                     (1U)
4492 #define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
4493 #define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
4494 #define PWR_CR_CWUF_Pos                     (2U)
4495 #define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
4496 #define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
4497 #define PWR_CR_CSBF_Pos                     (3U)
4498 #define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
4499 #define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
4500 #define PWR_CR_PVDE_Pos                     (4U)
4501 #define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
4502 #define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
4503 
4504 #define PWR_CR_PLS_Pos                      (5U)
4505 #define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
4506 #define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
4507 #define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
4508 #define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
4509 #define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
4510 
4511 /*!< PVD level configuration */
4512 #define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
4513 #define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
4514 #define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
4515 #define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
4516 #define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
4517 #define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
4518 #define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
4519 #define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
4520 
4521 #define PWR_CR_DBP_Pos                      (8U)
4522 #define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
4523 #define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
4524 #define PWR_CR_ULP_Pos                      (9U)
4525 #define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
4526 #define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
4527 #define PWR_CR_FWU_Pos                      (10U)
4528 #define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
4529 #define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
4530 
4531 #define PWR_CR_VOS_Pos                      (11U)
4532 #define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
4533 #define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
4534 #define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
4535 #define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
4536 #define PWR_CR_LPRUN_Pos                    (14U)
4537 #define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
4538 #define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
4539 
4540 /*******************  Bit definition for PWR_CSR register  ********************/
4541 #define PWR_CSR_WUF_Pos                     (0U)
4542 #define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
4543 #define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
4544 #define PWR_CSR_SBF_Pos                     (1U)
4545 #define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
4546 #define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
4547 #define PWR_CSR_PVDO_Pos                    (2U)
4548 #define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
4549 #define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
4550 #define PWR_CSR_VREFINTRDYF_Pos             (3U)
4551 #define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
4552 #define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
4553 #define PWR_CSR_VOSF_Pos                    (4U)
4554 #define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
4555 #define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
4556 #define PWR_CSR_REGLPF_Pos                  (5U)
4557 #define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
4558 #define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
4559 
4560 #define PWR_CSR_EWUP1_Pos                   (8U)
4561 #define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
4562 #define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
4563 #define PWR_CSR_EWUP2_Pos                   (9U)
4564 #define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
4565 #define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
4566 #define PWR_CSR_EWUP3_Pos                   (10U)
4567 #define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
4568 #define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
4569 
4570 /******************************************************************************/
4571 /*                                                                            */
4572 /*                      Reset and Clock Control (RCC)                         */
4573 /*                                                                            */
4574 /******************************************************************************/
4575 /*
4576 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
4577 */
4578 #define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
4579 
4580 /********************  Bit definition for RCC_CR register  ********************/
4581 #define RCC_CR_HSION_Pos                    (0U)
4582 #define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
4583 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
4584 #define RCC_CR_HSIRDY_Pos                   (1U)
4585 #define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
4586 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
4587 
4588 #define RCC_CR_MSION_Pos                    (8U)
4589 #define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
4590 #define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
4591 #define RCC_CR_MSIRDY_Pos                   (9U)
4592 #define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
4593 #define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
4594 
4595 #define RCC_CR_HSEON_Pos                    (16U)
4596 #define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
4597 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
4598 #define RCC_CR_HSERDY_Pos                   (17U)
4599 #define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
4600 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
4601 #define RCC_CR_HSEBYP_Pos                   (18U)
4602 #define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
4603 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
4604 
4605 #define RCC_CR_PLLON_Pos                    (24U)
4606 #define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
4607 #define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
4608 #define RCC_CR_PLLRDY_Pos                   (25U)
4609 #define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
4610 #define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
4611 #define RCC_CR_CSSON_Pos                    (28U)
4612 #define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
4613 #define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
4614 
4615 #define RCC_CR_RTCPRE_Pos                   (29U)
4616 #define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
4617 #define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
4618 #define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
4619 #define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
4620 
4621 /********************  Bit definition for RCC_ICSCR register  *****************/
4622 #define RCC_ICSCR_HSICAL_Pos                (0U)
4623 #define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
4624 #define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
4625 #define RCC_ICSCR_HSITRIM_Pos               (8U)
4626 #define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
4627 #define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
4628 
4629 #define RCC_ICSCR_MSIRANGE_Pos              (13U)
4630 #define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
4631 #define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
4632 #define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
4633 #define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
4634 #define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
4635 #define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
4636 #define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
4637 #define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
4638 #define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
4639 #define RCC_ICSCR_MSICAL_Pos                (16U)
4640 #define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
4641 #define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
4642 #define RCC_ICSCR_MSITRIM_Pos               (24U)
4643 #define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
4644 #define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
4645 
4646 /********************  Bit definition for RCC_CFGR register  ******************/
4647 #define RCC_CFGR_SW_Pos                     (0U)
4648 #define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
4649 #define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
4650 #define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
4651 #define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
4652 
4653 /*!< SW configuration */
4654 #define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
4655 #define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
4656 #define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
4657 #define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
4658 
4659 #define RCC_CFGR_SWS_Pos                    (2U)
4660 #define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
4661 #define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
4662 #define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
4663 #define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
4664 
4665 /*!< SWS configuration */
4666 #define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
4667 #define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
4668 #define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
4669 #define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
4670 
4671 #define RCC_CFGR_HPRE_Pos                   (4U)
4672 #define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
4673 #define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
4674 #define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
4675 #define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
4676 #define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
4677 #define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
4678 
4679 /*!< HPRE configuration */
4680 #define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
4681 #define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
4682 #define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
4683 #define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
4684 #define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
4685 #define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
4686 #define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
4687 #define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
4688 #define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
4689 
4690 #define RCC_CFGR_PPRE1_Pos                  (8U)
4691 #define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
4692 #define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
4693 #define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
4694 #define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
4695 #define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
4696 
4697 /*!< PPRE1 configuration */
4698 #define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
4699 #define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
4700 #define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
4701 #define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
4702 #define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
4703 
4704 #define RCC_CFGR_PPRE2_Pos                  (11U)
4705 #define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
4706 #define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
4707 #define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
4708 #define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
4709 #define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
4710 
4711 /*!< PPRE2 configuration */
4712 #define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
4713 #define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
4714 #define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
4715 #define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
4716 #define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
4717 
4718 /*!< PLL entry clock source*/
4719 #define RCC_CFGR_PLLSRC_Pos                 (16U)
4720 #define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
4721 #define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
4722 
4723 #define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
4724 #define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
4725 
4726 
4727 /*!< PLLMUL configuration */
4728 #define RCC_CFGR_PLLMUL_Pos                 (18U)
4729 #define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
4730 #define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
4731 #define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
4732 #define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
4733 #define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
4734 #define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
4735 
4736 /*!< PLLMUL configuration */
4737 #define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
4738 #define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
4739 #define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
4740 #define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
4741 #define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
4742 #define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
4743 #define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
4744 #define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
4745 #define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
4746 
4747 /*!< PLLDIV configuration */
4748 #define RCC_CFGR_PLLDIV_Pos                 (22U)
4749 #define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
4750 #define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
4751 #define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
4752 #define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
4753 
4754 
4755 /*!< PLLDIV configuration */
4756 #define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
4757 #define RCC_CFGR_PLLDIV2_Pos                (22U)
4758 #define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
4759 #define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
4760 #define RCC_CFGR_PLLDIV3_Pos                (23U)
4761 #define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
4762 #define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
4763 #define RCC_CFGR_PLLDIV4_Pos                (22U)
4764 #define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
4765 #define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
4766 
4767 
4768 #define RCC_CFGR_MCOSEL_Pos                 (24U)
4769 #define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
4770 #define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
4771 #define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
4772 #define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
4773 #define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
4774 
4775 /*!< MCO configuration */
4776 #define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
4777 #define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)
4778 #define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
4779 #define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
4780 #define RCC_CFGR_MCOSEL_HSI_Pos             (25U)
4781 #define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
4782 #define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
4783 #define RCC_CFGR_MCOSEL_MSI_Pos             (24U)
4784 #define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
4785 #define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
4786 #define RCC_CFGR_MCOSEL_HSE_Pos             (26U)
4787 #define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
4788 #define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
4789 #define RCC_CFGR_MCOSEL_PLL_Pos             (24U)
4790 #define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
4791 #define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
4792 #define RCC_CFGR_MCOSEL_LSI_Pos             (25U)
4793 #define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
4794 #define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
4795 #define RCC_CFGR_MCOSEL_LSE_Pos             (24U)
4796 #define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
4797 #define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
4798 
4799 #define RCC_CFGR_MCOPRE_Pos                 (28U)
4800 #define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
4801 #define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
4802 #define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
4803 #define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
4804 #define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
4805 
4806 /*!< MCO Prescaler configuration */
4807 #define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
4808 #define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
4809 #define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
4810 #define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
4811 #define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
4812 
4813 /* Legacy aliases */
4814 #define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
4815 #define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
4816 #define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
4817 #define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
4818 #define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
4819 #define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
4820 #define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
4821 #define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
4822 #define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
4823 #define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
4824 #define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
4825 #define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
4826 #define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
4827 
4828 /*!<******************  Bit definition for RCC_CIR register  ********************/
4829 #define RCC_CIR_LSIRDYF_Pos                 (0U)
4830 #define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
4831 #define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
4832 #define RCC_CIR_LSERDYF_Pos                 (1U)
4833 #define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
4834 #define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
4835 #define RCC_CIR_HSIRDYF_Pos                 (2U)
4836 #define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
4837 #define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
4838 #define RCC_CIR_HSERDYF_Pos                 (3U)
4839 #define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
4840 #define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
4841 #define RCC_CIR_PLLRDYF_Pos                 (4U)
4842 #define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
4843 #define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
4844 #define RCC_CIR_MSIRDYF_Pos                 (5U)
4845 #define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
4846 #define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
4847 #define RCC_CIR_LSECSSF_Pos                 (6U)
4848 #define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
4849 #define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
4850 #define RCC_CIR_CSSF_Pos                    (7U)
4851 #define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
4852 #define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
4853 
4854 #define RCC_CIR_LSIRDYIE_Pos                (8U)
4855 #define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
4856 #define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
4857 #define RCC_CIR_LSERDYIE_Pos                (9U)
4858 #define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
4859 #define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
4860 #define RCC_CIR_HSIRDYIE_Pos                (10U)
4861 #define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
4862 #define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
4863 #define RCC_CIR_HSERDYIE_Pos                (11U)
4864 #define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
4865 #define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
4866 #define RCC_CIR_PLLRDYIE_Pos                (12U)
4867 #define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
4868 #define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
4869 #define RCC_CIR_MSIRDYIE_Pos                (13U)
4870 #define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
4871 #define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
4872 #define RCC_CIR_LSECSSIE_Pos                (14U)
4873 #define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
4874 #define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
4875 
4876 #define RCC_CIR_LSIRDYC_Pos                 (16U)
4877 #define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
4878 #define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
4879 #define RCC_CIR_LSERDYC_Pos                 (17U)
4880 #define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
4881 #define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
4882 #define RCC_CIR_HSIRDYC_Pos                 (18U)
4883 #define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
4884 #define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
4885 #define RCC_CIR_HSERDYC_Pos                 (19U)
4886 #define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
4887 #define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
4888 #define RCC_CIR_PLLRDYC_Pos                 (20U)
4889 #define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
4890 #define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
4891 #define RCC_CIR_MSIRDYC_Pos                 (21U)
4892 #define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
4893 #define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
4894 #define RCC_CIR_LSECSSC_Pos                 (22U)
4895 #define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
4896 #define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
4897 #define RCC_CIR_CSSC_Pos                    (23U)
4898 #define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
4899 #define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
4900 
4901 /*****************  Bit definition for RCC_AHBRSTR register  ******************/
4902 #define RCC_AHBRSTR_GPIOARST_Pos            (0U)
4903 #define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
4904 #define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
4905 #define RCC_AHBRSTR_GPIOBRST_Pos            (1U)
4906 #define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4907 #define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
4908 #define RCC_AHBRSTR_GPIOCRST_Pos            (2U)
4909 #define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4910 #define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
4911 #define RCC_AHBRSTR_GPIODRST_Pos            (3U)
4912 #define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
4913 #define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
4914 #define RCC_AHBRSTR_GPIOERST_Pos            (4U)
4915 #define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
4916 #define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
4917 #define RCC_AHBRSTR_GPIOHRST_Pos            (5U)
4918 #define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
4919 #define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
4920 #define RCC_AHBRSTR_GPIOFRST_Pos            (6U)
4921 #define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
4922 #define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
4923 #define RCC_AHBRSTR_GPIOGRST_Pos            (7U)
4924 #define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
4925 #define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
4926 #define RCC_AHBRSTR_CRCRST_Pos              (12U)
4927 #define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
4928 #define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
4929 #define RCC_AHBRSTR_FLITFRST_Pos            (15U)
4930 #define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
4931 #define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
4932 #define RCC_AHBRSTR_DMA1RST_Pos             (24U)
4933 #define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
4934 #define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
4935 #define RCC_AHBRSTR_DMA2RST_Pos             (25U)
4936 #define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
4937 #define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
4938 #define RCC_AHBRSTR_AESRST_Pos              (27U)
4939 #define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
4940 #define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
4941 #define RCC_AHBRSTR_FSMCRST_Pos             (30U)
4942 #define RCC_AHBRSTR_FSMCRST_Msk             (0x1UL << RCC_AHBRSTR_FSMCRST_Pos)  /*!< 0x40000000 */
4943 #define RCC_AHBRSTR_FSMCRST                 RCC_AHBRSTR_FSMCRST_Msk            /*!< FSMC reset */
4944 
4945 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
4946 #define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)
4947 #define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
4948 #define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
4949 #define RCC_APB2RSTR_TIM9RST_Pos            (2U)
4950 #define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
4951 #define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
4952 #define RCC_APB2RSTR_TIM10RST_Pos           (3U)
4953 #define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
4954 #define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
4955 #define RCC_APB2RSTR_TIM11RST_Pos           (4U)
4956 #define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
4957 #define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
4958 #define RCC_APB2RSTR_ADC1RST_Pos            (9U)
4959 #define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
4960 #define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
4961 #define RCC_APB2RSTR_SDIORST_Pos            (11U)
4962 #define RCC_APB2RSTR_SDIORST_Msk            (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
4963 #define RCC_APB2RSTR_SDIORST                RCC_APB2RSTR_SDIORST_Msk           /*!< SDIO reset */
4964 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
4965 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
4966 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
4967 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
4968 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
4969 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
4970 
4971 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
4972 #define RCC_APB1RSTR_TIM2RST_Pos            (0U)
4973 #define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
4974 #define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
4975 #define RCC_APB1RSTR_TIM3RST_Pos            (1U)
4976 #define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
4977 #define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
4978 #define RCC_APB1RSTR_TIM4RST_Pos            (2U)
4979 #define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
4980 #define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
4981 #define RCC_APB1RSTR_TIM5RST_Pos            (3U)
4982 #define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
4983 #define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
4984 #define RCC_APB1RSTR_TIM6RST_Pos            (4U)
4985 #define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
4986 #define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
4987 #define RCC_APB1RSTR_TIM7RST_Pos            (5U)
4988 #define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
4989 #define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
4990 #define RCC_APB1RSTR_LCDRST_Pos             (9U)
4991 #define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
4992 #define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
4993 #define RCC_APB1RSTR_WWDGRST_Pos            (11U)
4994 #define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4995 #define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
4996 #define RCC_APB1RSTR_SPI2RST_Pos            (14U)
4997 #define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
4998 #define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
4999 #define RCC_APB1RSTR_SPI3RST_Pos            (15U)
5000 #define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
5001 #define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
5002 #define RCC_APB1RSTR_USART2RST_Pos          (17U)
5003 #define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
5004 #define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
5005 #define RCC_APB1RSTR_USART3RST_Pos          (18U)
5006 #define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
5007 #define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
5008 #define RCC_APB1RSTR_UART4RST_Pos           (19U)
5009 #define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
5010 #define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
5011 #define RCC_APB1RSTR_UART5RST_Pos           (20U)
5012 #define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
5013 #define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
5014 #define RCC_APB1RSTR_I2C1RST_Pos            (21U)
5015 #define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
5016 #define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
5017 #define RCC_APB1RSTR_I2C2RST_Pos            (22U)
5018 #define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
5019 #define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
5020 #define RCC_APB1RSTR_USBRST_Pos             (23U)
5021 #define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
5022 #define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
5023 #define RCC_APB1RSTR_PWRRST_Pos             (28U)
5024 #define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
5025 #define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
5026 #define RCC_APB1RSTR_DACRST_Pos             (29U)
5027 #define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
5028 #define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
5029 #define RCC_APB1RSTR_COMPRST_Pos            (31U)
5030 #define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
5031 #define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
5032 
5033 /******************  Bit definition for RCC_AHBENR register  ******************/
5034 #define RCC_AHBENR_GPIOAEN_Pos              (0U)
5035 #define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
5036 #define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
5037 #define RCC_AHBENR_GPIOBEN_Pos              (1U)
5038 #define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
5039 #define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
5040 #define RCC_AHBENR_GPIOCEN_Pos              (2U)
5041 #define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
5042 #define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
5043 #define RCC_AHBENR_GPIODEN_Pos              (3U)
5044 #define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
5045 #define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
5046 #define RCC_AHBENR_GPIOEEN_Pos              (4U)
5047 #define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
5048 #define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
5049 #define RCC_AHBENR_GPIOHEN_Pos              (5U)
5050 #define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
5051 #define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
5052 #define RCC_AHBENR_GPIOFEN_Pos              (6U)
5053 #define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
5054 #define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
5055 #define RCC_AHBENR_GPIOGEN_Pos              (7U)
5056 #define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
5057 #define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
5058 #define RCC_AHBENR_CRCEN_Pos                (12U)
5059 #define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
5060 #define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
5061 #define RCC_AHBENR_FLITFEN_Pos              (15U)
5062 #define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
5063 #define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
5064                                                                                 the Flash memory is in power down mode) */
5065 #define RCC_AHBENR_DMA1EN_Pos               (24U)
5066 #define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
5067 #define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
5068 #define RCC_AHBENR_DMA2EN_Pos               (25U)
5069 #define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
5070 #define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
5071 #define RCC_AHBENR_AESEN_Pos                (27U)
5072 #define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
5073 #define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
5074 #define RCC_AHBENR_FSMCEN_Pos               (30U)
5075 #define RCC_AHBENR_FSMCEN_Msk               (0x1UL << RCC_AHBENR_FSMCEN_Pos)    /*!< 0x40000000 */
5076 #define RCC_AHBENR_FSMCEN                   RCC_AHBENR_FSMCEN_Msk              /*!< FSMC clock enable */
5077 
5078 /******************  Bit definition for RCC_APB2ENR register  *****************/
5079 #define RCC_APB2ENR_SYSCFGEN_Pos            (0U)
5080 #define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
5081 #define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
5082 #define RCC_APB2ENR_TIM9EN_Pos              (2U)
5083 #define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
5084 #define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
5085 #define RCC_APB2ENR_TIM10EN_Pos             (3U)
5086 #define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
5087 #define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
5088 #define RCC_APB2ENR_TIM11EN_Pos             (4U)
5089 #define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
5090 #define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
5091 #define RCC_APB2ENR_ADC1EN_Pos              (9U)
5092 #define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
5093 #define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
5094 #define RCC_APB2ENR_SDIOEN_Pos              (11U)
5095 #define RCC_APB2ENR_SDIOEN_Msk              (0x1UL << RCC_APB2ENR_SDIOEN_Pos)   /*!< 0x00000800 */
5096 #define RCC_APB2ENR_SDIOEN                  RCC_APB2ENR_SDIOEN_Msk             /*!< SDIO clock enable */
5097 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
5098 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
5099 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
5100 #define RCC_APB2ENR_USART1EN_Pos            (14U)
5101 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
5102 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
5103 
5104 /*****************  Bit definition for RCC_APB1ENR register  ******************/
5105 #define RCC_APB1ENR_TIM2EN_Pos              (0U)
5106 #define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
5107 #define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
5108 #define RCC_APB1ENR_TIM3EN_Pos              (1U)
5109 #define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
5110 #define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
5111 #define RCC_APB1ENR_TIM4EN_Pos              (2U)
5112 #define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
5113 #define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
5114 #define RCC_APB1ENR_TIM5EN_Pos              (3U)
5115 #define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
5116 #define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
5117 #define RCC_APB1ENR_TIM6EN_Pos              (4U)
5118 #define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
5119 #define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
5120 #define RCC_APB1ENR_TIM7EN_Pos              (5U)
5121 #define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
5122 #define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
5123 #define RCC_APB1ENR_LCDEN_Pos               (9U)
5124 #define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
5125 #define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
5126 #define RCC_APB1ENR_WWDGEN_Pos              (11U)
5127 #define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
5128 #define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
5129 #define RCC_APB1ENR_SPI2EN_Pos              (14U)
5130 #define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
5131 #define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
5132 #define RCC_APB1ENR_SPI3EN_Pos              (15U)
5133 #define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
5134 #define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
5135 #define RCC_APB1ENR_USART2EN_Pos            (17U)
5136 #define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
5137 #define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
5138 #define RCC_APB1ENR_USART3EN_Pos            (18U)
5139 #define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
5140 #define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
5141 #define RCC_APB1ENR_UART4EN_Pos             (19U)
5142 #define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
5143 #define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
5144 #define RCC_APB1ENR_UART5EN_Pos             (20U)
5145 #define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
5146 #define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
5147 #define RCC_APB1ENR_I2C1EN_Pos              (21U)
5148 #define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
5149 #define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
5150 #define RCC_APB1ENR_I2C2EN_Pos              (22U)
5151 #define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
5152 #define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
5153 #define RCC_APB1ENR_USBEN_Pos               (23U)
5154 #define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
5155 #define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
5156 #define RCC_APB1ENR_PWREN_Pos               (28U)
5157 #define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
5158 #define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
5159 #define RCC_APB1ENR_DACEN_Pos               (29U)
5160 #define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
5161 #define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
5162 #define RCC_APB1ENR_COMPEN_Pos              (31U)
5163 #define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
5164 #define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
5165 
5166 /******************  Bit definition for RCC_AHBLPENR register  ****************/
5167 #define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)
5168 #define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
5169 #define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
5170 #define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)
5171 #define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
5172 #define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
5173 #define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)
5174 #define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
5175 #define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
5176 #define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)
5177 #define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
5178 #define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
5179 #define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)
5180 #define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
5181 #define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
5182 #define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)
5183 #define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
5184 #define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
5185 #define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)
5186 #define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
5187 #define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
5188 #define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)
5189 #define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
5190 #define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
5191 #define RCC_AHBLPENR_CRCLPEN_Pos            (12U)
5192 #define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
5193 #define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
5194 #define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)
5195 #define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
5196 #define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
5197                                                                                 (has effect only when the Flash memory is
5198                                                                                  in power down mode) */
5199 #define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)
5200 #define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
5201 #define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
5202 #define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)
5203 #define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
5204 #define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
5205 #define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)
5206 #define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
5207 #define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
5208 #define RCC_AHBLPENR_AESLPEN_Pos            (27U)
5209 #define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
5210 #define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
5211 #define RCC_AHBLPENR_FSMCLPEN_Pos           (30U)
5212 #define RCC_AHBLPENR_FSMCLPEN_Msk           (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */
5213 #define RCC_AHBLPENR_FSMCLPEN               RCC_AHBLPENR_FSMCLPEN_Msk          /*!< FSMC clock enabled in sleep mode */
5214 
5215 /******************  Bit definition for RCC_APB2LPENR register  ***************/
5216 #define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)
5217 #define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
5218 #define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
5219 #define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)
5220 #define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
5221 #define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
5222 #define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)
5223 #define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
5224 #define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
5225 #define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)
5226 #define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
5227 #define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
5228 #define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)
5229 #define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
5230 #define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
5231 #define RCC_APB2LPENR_SDIOLPEN_Pos          (11U)
5232 #define RCC_APB2LPENR_SDIOLPEN_Msk          (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
5233 #define RCC_APB2LPENR_SDIOLPEN              RCC_APB2LPENR_SDIOLPEN_Msk         /*!< SDIO clock enabled in sleep mode */
5234 #define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
5235 #define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
5236 #define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
5237 #define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
5238 #define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
5239 #define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
5240 
5241 /*****************  Bit definition for RCC_APB1LPENR register  ****************/
5242 #define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)
5243 #define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
5244 #define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
5245 #define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)
5246 #define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
5247 #define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
5248 #define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)
5249 #define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
5250 #define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
5251 #define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)
5252 #define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
5253 #define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
5254 #define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)
5255 #define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
5256 #define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
5257 #define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)
5258 #define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
5259 #define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
5260 #define RCC_APB1LPENR_LCDLPEN_Pos           (9U)
5261 #define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
5262 #define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
5263 #define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)
5264 #define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
5265 #define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
5266 #define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)
5267 #define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
5268 #define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
5269 #define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)
5270 #define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
5271 #define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
5272 #define RCC_APB1LPENR_USART2LPEN_Pos        (17U)
5273 #define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
5274 #define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
5275 #define RCC_APB1LPENR_USART3LPEN_Pos        (18U)
5276 #define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
5277 #define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
5278 #define RCC_APB1LPENR_UART4LPEN_Pos         (19U)
5279 #define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
5280 #define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
5281 #define RCC_APB1LPENR_UART5LPEN_Pos         (20U)
5282 #define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
5283 #define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
5284 #define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)
5285 #define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
5286 #define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
5287 #define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)
5288 #define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
5289 #define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
5290 #define RCC_APB1LPENR_USBLPEN_Pos           (23U)
5291 #define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
5292 #define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
5293 #define RCC_APB1LPENR_PWRLPEN_Pos           (28U)
5294 #define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
5295 #define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
5296 #define RCC_APB1LPENR_DACLPEN_Pos           (29U)
5297 #define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
5298 #define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
5299 #define RCC_APB1LPENR_COMPLPEN_Pos          (31U)
5300 #define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
5301 #define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
5302 
5303 /*******************  Bit definition for RCC_CSR register  ********************/
5304 #define RCC_CSR_LSION_Pos                   (0U)
5305 #define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
5306 #define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
5307 #define RCC_CSR_LSIRDY_Pos                  (1U)
5308 #define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
5309 #define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
5310 
5311 #define RCC_CSR_LSEON_Pos                   (8U)
5312 #define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
5313 #define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
5314 #define RCC_CSR_LSERDY_Pos                  (9U)
5315 #define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
5316 #define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
5317 #define RCC_CSR_LSEBYP_Pos                  (10U)
5318 #define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
5319 #define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
5320 
5321 #define RCC_CSR_LSECSSON_Pos                (11U)
5322 #define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
5323 #define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
5324 #define RCC_CSR_LSECSSD_Pos                 (12U)
5325 #define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
5326 #define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
5327 
5328 #define RCC_CSR_RTCSEL_Pos                  (16U)
5329 #define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
5330 #define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
5331 #define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
5332 #define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
5333 
5334 /*!< RTC configuration */
5335 #define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
5336 #define RCC_CSR_RTCSEL_LSE_Pos              (16U)
5337 #define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
5338 #define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
5339 #define RCC_CSR_RTCSEL_LSI_Pos              (17U)
5340 #define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
5341 #define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
5342 #define RCC_CSR_RTCSEL_HSE_Pos              (16U)
5343 #define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
5344 #define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
5345 
5346 #define RCC_CSR_RTCEN_Pos                   (22U)
5347 #define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
5348 #define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
5349 #define RCC_CSR_RTCRST_Pos                  (23U)
5350 #define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
5351 #define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
5352 
5353 #define RCC_CSR_RMVF_Pos                    (24U)
5354 #define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
5355 #define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
5356 #define RCC_CSR_OBLRSTF_Pos                 (25U)
5357 #define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
5358 #define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
5359 #define RCC_CSR_PINRSTF_Pos                 (26U)
5360 #define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
5361 #define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
5362 #define RCC_CSR_PORRSTF_Pos                 (27U)
5363 #define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
5364 #define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
5365 #define RCC_CSR_SFTRSTF_Pos                 (28U)
5366 #define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
5367 #define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
5368 #define RCC_CSR_IWDGRSTF_Pos                (29U)
5369 #define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
5370 #define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
5371 #define RCC_CSR_WWDGRSTF_Pos                (30U)
5372 #define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
5373 #define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
5374 #define RCC_CSR_LPWRRSTF_Pos                (31U)
5375 #define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
5376 #define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
5377 
5378 /******************************************************************************/
5379 /*                                                                            */
5380 /*                           Real-Time Clock (RTC)                            */
5381 /*                                                                            */
5382 /******************************************************************************/
5383 /*
5384 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
5385 */
5386 #define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
5387 #define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
5388 #define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
5389 #define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
5390 #define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
5391 #define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
5392 #define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
5393 
5394 /********************  Bits definition for RTC_TR register  *******************/
5395 #define RTC_TR_PM_Pos                        (22U)
5396 #define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
5397 #define RTC_TR_PM                            RTC_TR_PM_Msk
5398 #define RTC_TR_HT_Pos                        (20U)
5399 #define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
5400 #define RTC_TR_HT                            RTC_TR_HT_Msk
5401 #define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
5402 #define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
5403 #define RTC_TR_HU_Pos                        (16U)
5404 #define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
5405 #define RTC_TR_HU                            RTC_TR_HU_Msk
5406 #define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
5407 #define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
5408 #define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
5409 #define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
5410 #define RTC_TR_MNT_Pos                       (12U)
5411 #define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
5412 #define RTC_TR_MNT                           RTC_TR_MNT_Msk
5413 #define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
5414 #define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
5415 #define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
5416 #define RTC_TR_MNU_Pos                       (8U)
5417 #define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
5418 #define RTC_TR_MNU                           RTC_TR_MNU_Msk
5419 #define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
5420 #define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
5421 #define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
5422 #define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
5423 #define RTC_TR_ST_Pos                        (4U)
5424 #define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
5425 #define RTC_TR_ST                            RTC_TR_ST_Msk
5426 #define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
5427 #define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
5428 #define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
5429 #define RTC_TR_SU_Pos                        (0U)
5430 #define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
5431 #define RTC_TR_SU                            RTC_TR_SU_Msk
5432 #define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
5433 #define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
5434 #define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
5435 #define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
5436 
5437 /********************  Bits definition for RTC_DR register  *******************/
5438 #define RTC_DR_YT_Pos                        (20U)
5439 #define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
5440 #define RTC_DR_YT                            RTC_DR_YT_Msk
5441 #define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
5442 #define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
5443 #define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
5444 #define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
5445 #define RTC_DR_YU_Pos                        (16U)
5446 #define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
5447 #define RTC_DR_YU                            RTC_DR_YU_Msk
5448 #define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
5449 #define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
5450 #define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
5451 #define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
5452 #define RTC_DR_WDU_Pos                       (13U)
5453 #define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
5454 #define RTC_DR_WDU                           RTC_DR_WDU_Msk
5455 #define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
5456 #define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
5457 #define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
5458 #define RTC_DR_MT_Pos                        (12U)
5459 #define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
5460 #define RTC_DR_MT                            RTC_DR_MT_Msk
5461 #define RTC_DR_MU_Pos                        (8U)
5462 #define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
5463 #define RTC_DR_MU                            RTC_DR_MU_Msk
5464 #define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
5465 #define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
5466 #define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
5467 #define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
5468 #define RTC_DR_DT_Pos                        (4U)
5469 #define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
5470 #define RTC_DR_DT                            RTC_DR_DT_Msk
5471 #define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
5472 #define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
5473 #define RTC_DR_DU_Pos                        (0U)
5474 #define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
5475 #define RTC_DR_DU                            RTC_DR_DU_Msk
5476 #define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
5477 #define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
5478 #define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
5479 #define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
5480 
5481 /********************  Bits definition for RTC_CR register  *******************/
5482 #define RTC_CR_COE_Pos                       (23U)
5483 #define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
5484 #define RTC_CR_COE                           RTC_CR_COE_Msk
5485 #define RTC_CR_OSEL_Pos                      (21U)
5486 #define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
5487 #define RTC_CR_OSEL                          RTC_CR_OSEL_Msk
5488 #define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
5489 #define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
5490 #define RTC_CR_POL_Pos                       (20U)
5491 #define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
5492 #define RTC_CR_POL                           RTC_CR_POL_Msk
5493 #define RTC_CR_COSEL_Pos                     (19U)
5494 #define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
5495 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk
5496 #define RTC_CR_BKP_Pos                       (18U)
5497 #define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
5498 #define RTC_CR_BKP                           RTC_CR_BKP_Msk
5499 #define RTC_CR_SUB1H_Pos                     (17U)
5500 #define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
5501 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk
5502 #define RTC_CR_ADD1H_Pos                     (16U)
5503 #define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
5504 #define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk
5505 #define RTC_CR_TSIE_Pos                      (15U)
5506 #define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
5507 #define RTC_CR_TSIE                          RTC_CR_TSIE_Msk
5508 #define RTC_CR_WUTIE_Pos                     (14U)
5509 #define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
5510 #define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk
5511 #define RTC_CR_ALRBIE_Pos                    (13U)
5512 #define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
5513 #define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk
5514 #define RTC_CR_ALRAIE_Pos                    (12U)
5515 #define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
5516 #define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk
5517 #define RTC_CR_TSE_Pos                       (11U)
5518 #define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
5519 #define RTC_CR_TSE                           RTC_CR_TSE_Msk
5520 #define RTC_CR_WUTE_Pos                      (10U)
5521 #define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
5522 #define RTC_CR_WUTE                          RTC_CR_WUTE_Msk
5523 #define RTC_CR_ALRBE_Pos                     (9U)
5524 #define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
5525 #define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk
5526 #define RTC_CR_ALRAE_Pos                     (8U)
5527 #define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
5528 #define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk
5529 #define RTC_CR_DCE_Pos                       (7U)
5530 #define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
5531 #define RTC_CR_DCE                           RTC_CR_DCE_Msk
5532 #define RTC_CR_FMT_Pos                       (6U)
5533 #define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
5534 #define RTC_CR_FMT                           RTC_CR_FMT_Msk
5535 #define RTC_CR_BYPSHAD_Pos                   (5U)
5536 #define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
5537 #define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk
5538 #define RTC_CR_REFCKON_Pos                   (4U)
5539 #define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
5540 #define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk
5541 #define RTC_CR_TSEDGE_Pos                    (3U)
5542 #define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
5543 #define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk
5544 #define RTC_CR_WUCKSEL_Pos                   (0U)
5545 #define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
5546 #define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk
5547 #define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
5548 #define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
5549 #define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
5550 
5551 /* Legacy defines */
5552 #define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
5553 #define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
5554 #define  RTC_CR_BCK     RTC_CR_BKP
5555 
5556 /********************  Bits definition for RTC_ISR register  ******************/
5557 #define RTC_ISR_RECALPF_Pos                  (16U)
5558 #define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
5559 #define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk
5560 #define RTC_ISR_TAMP3F_Pos                   (15U)
5561 #define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
5562 #define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk
5563 #define RTC_ISR_TAMP2F_Pos                   (14U)
5564 #define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
5565 #define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk
5566 #define RTC_ISR_TAMP1F_Pos                   (13U)
5567 #define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
5568 #define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk
5569 #define RTC_ISR_TSOVF_Pos                    (12U)
5570 #define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
5571 #define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk
5572 #define RTC_ISR_TSF_Pos                      (11U)
5573 #define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
5574 #define RTC_ISR_TSF                          RTC_ISR_TSF_Msk
5575 #define RTC_ISR_WUTF_Pos                     (10U)
5576 #define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
5577 #define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk
5578 #define RTC_ISR_ALRBF_Pos                    (9U)
5579 #define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
5580 #define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk
5581 #define RTC_ISR_ALRAF_Pos                    (8U)
5582 #define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
5583 #define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk
5584 #define RTC_ISR_INIT_Pos                     (7U)
5585 #define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
5586 #define RTC_ISR_INIT                         RTC_ISR_INIT_Msk
5587 #define RTC_ISR_INITF_Pos                    (6U)
5588 #define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
5589 #define RTC_ISR_INITF                        RTC_ISR_INITF_Msk
5590 #define RTC_ISR_RSF_Pos                      (5U)
5591 #define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
5592 #define RTC_ISR_RSF                          RTC_ISR_RSF_Msk
5593 #define RTC_ISR_INITS_Pos                    (4U)
5594 #define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
5595 #define RTC_ISR_INITS                        RTC_ISR_INITS_Msk
5596 #define RTC_ISR_SHPF_Pos                     (3U)
5597 #define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
5598 #define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk
5599 #define RTC_ISR_WUTWF_Pos                    (2U)
5600 #define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
5601 #define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk
5602 #define RTC_ISR_ALRBWF_Pos                   (1U)
5603 #define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
5604 #define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk
5605 #define RTC_ISR_ALRAWF_Pos                   (0U)
5606 #define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
5607 #define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk
5608 
5609 /********************  Bits definition for RTC_PRER register  *****************/
5610 #define RTC_PRER_PREDIV_A_Pos                (16U)
5611 #define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
5612 #define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk
5613 #define RTC_PRER_PREDIV_S_Pos                (0U)
5614 #define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
5615 #define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk
5616 
5617 /********************  Bits definition for RTC_WUTR register  *****************/
5618 #define RTC_WUTR_WUT_Pos                     (0U)
5619 #define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
5620 #define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk
5621 
5622 /********************  Bits definition for RTC_CALIBR register  ***************/
5623 #define RTC_CALIBR_DCS_Pos                   (7U)
5624 #define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
5625 #define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk
5626 #define RTC_CALIBR_DC_Pos                    (0U)
5627 #define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
5628 #define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk
5629 
5630 /********************  Bits definition for RTC_ALRMAR register  ***************/
5631 #define RTC_ALRMAR_MSK4_Pos                  (31U)
5632 #define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
5633 #define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk
5634 #define RTC_ALRMAR_WDSEL_Pos                 (30U)
5635 #define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
5636 #define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk
5637 #define RTC_ALRMAR_DT_Pos                    (28U)
5638 #define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
5639 #define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk
5640 #define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
5641 #define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
5642 #define RTC_ALRMAR_DU_Pos                    (24U)
5643 #define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
5644 #define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk
5645 #define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
5646 #define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
5647 #define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
5648 #define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
5649 #define RTC_ALRMAR_MSK3_Pos                  (23U)
5650 #define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
5651 #define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk
5652 #define RTC_ALRMAR_PM_Pos                    (22U)
5653 #define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
5654 #define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk
5655 #define RTC_ALRMAR_HT_Pos                    (20U)
5656 #define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
5657 #define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk
5658 #define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
5659 #define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
5660 #define RTC_ALRMAR_HU_Pos                    (16U)
5661 #define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
5662 #define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk
5663 #define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
5664 #define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
5665 #define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
5666 #define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
5667 #define RTC_ALRMAR_MSK2_Pos                  (15U)
5668 #define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
5669 #define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk
5670 #define RTC_ALRMAR_MNT_Pos                   (12U)
5671 #define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
5672 #define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk
5673 #define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
5674 #define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
5675 #define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
5676 #define RTC_ALRMAR_MNU_Pos                   (8U)
5677 #define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
5678 #define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk
5679 #define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
5680 #define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
5681 #define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
5682 #define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
5683 #define RTC_ALRMAR_MSK1_Pos                  (7U)
5684 #define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
5685 #define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk
5686 #define RTC_ALRMAR_ST_Pos                    (4U)
5687 #define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
5688 #define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk
5689 #define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
5690 #define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
5691 #define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
5692 #define RTC_ALRMAR_SU_Pos                    (0U)
5693 #define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
5694 #define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk
5695 #define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
5696 #define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
5697 #define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
5698 #define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
5699 
5700 /********************  Bits definition for RTC_ALRMBR register  ***************/
5701 #define RTC_ALRMBR_MSK4_Pos                  (31U)
5702 #define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
5703 #define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk
5704 #define RTC_ALRMBR_WDSEL_Pos                 (30U)
5705 #define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
5706 #define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk
5707 #define RTC_ALRMBR_DT_Pos                    (28U)
5708 #define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
5709 #define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk
5710 #define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
5711 #define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
5712 #define RTC_ALRMBR_DU_Pos                    (24U)
5713 #define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
5714 #define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk
5715 #define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
5716 #define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
5717 #define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
5718 #define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
5719 #define RTC_ALRMBR_MSK3_Pos                  (23U)
5720 #define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
5721 #define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk
5722 #define RTC_ALRMBR_PM_Pos                    (22U)
5723 #define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
5724 #define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk
5725 #define RTC_ALRMBR_HT_Pos                    (20U)
5726 #define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
5727 #define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk
5728 #define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
5729 #define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
5730 #define RTC_ALRMBR_HU_Pos                    (16U)
5731 #define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
5732 #define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk
5733 #define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
5734 #define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
5735 #define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
5736 #define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
5737 #define RTC_ALRMBR_MSK2_Pos                  (15U)
5738 #define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
5739 #define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk
5740 #define RTC_ALRMBR_MNT_Pos                   (12U)
5741 #define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
5742 #define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk
5743 #define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
5744 #define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
5745 #define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
5746 #define RTC_ALRMBR_MNU_Pos                   (8U)
5747 #define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
5748 #define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk
5749 #define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
5750 #define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
5751 #define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
5752 #define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
5753 #define RTC_ALRMBR_MSK1_Pos                  (7U)
5754 #define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
5755 #define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk
5756 #define RTC_ALRMBR_ST_Pos                    (4U)
5757 #define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
5758 #define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk
5759 #define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
5760 #define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
5761 #define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
5762 #define RTC_ALRMBR_SU_Pos                    (0U)
5763 #define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
5764 #define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk
5765 #define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
5766 #define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
5767 #define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
5768 #define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
5769 
5770 /********************  Bits definition for RTC_WPR register  ******************/
5771 #define RTC_WPR_KEY_Pos                      (0U)
5772 #define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
5773 #define RTC_WPR_KEY                          RTC_WPR_KEY_Msk
5774 
5775 /********************  Bits definition for RTC_SSR register  ******************/
5776 #define RTC_SSR_SS_Pos                       (0U)
5777 #define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
5778 #define RTC_SSR_SS                           RTC_SSR_SS_Msk
5779 
5780 /********************  Bits definition for RTC_SHIFTR register  ***************/
5781 #define RTC_SHIFTR_SUBFS_Pos                 (0U)
5782 #define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
5783 #define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk
5784 #define RTC_SHIFTR_ADD1S_Pos                 (31U)
5785 #define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
5786 #define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk
5787 
5788 /********************  Bits definition for RTC_TSTR register  *****************/
5789 #define RTC_TSTR_PM_Pos                      (22U)
5790 #define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
5791 #define RTC_TSTR_PM                          RTC_TSTR_PM_Msk
5792 #define RTC_TSTR_HT_Pos                      (20U)
5793 #define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
5794 #define RTC_TSTR_HT                          RTC_TSTR_HT_Msk
5795 #define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
5796 #define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
5797 #define RTC_TSTR_HU_Pos                      (16U)
5798 #define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
5799 #define RTC_TSTR_HU                          RTC_TSTR_HU_Msk
5800 #define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
5801 #define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
5802 #define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
5803 #define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
5804 #define RTC_TSTR_MNT_Pos                     (12U)
5805 #define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
5806 #define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk
5807 #define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
5808 #define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
5809 #define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
5810 #define RTC_TSTR_MNU_Pos                     (8U)
5811 #define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
5812 #define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk
5813 #define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
5814 #define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
5815 #define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
5816 #define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
5817 #define RTC_TSTR_ST_Pos                      (4U)
5818 #define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
5819 #define RTC_TSTR_ST                          RTC_TSTR_ST_Msk
5820 #define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
5821 #define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
5822 #define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
5823 #define RTC_TSTR_SU_Pos                      (0U)
5824 #define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
5825 #define RTC_TSTR_SU                          RTC_TSTR_SU_Msk
5826 #define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
5827 #define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
5828 #define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
5829 #define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
5830 
5831 /********************  Bits definition for RTC_TSDR register  *****************/
5832 #define RTC_TSDR_WDU_Pos                     (13U)
5833 #define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
5834 #define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk
5835 #define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
5836 #define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
5837 #define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
5838 #define RTC_TSDR_MT_Pos                      (12U)
5839 #define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
5840 #define RTC_TSDR_MT                          RTC_TSDR_MT_Msk
5841 #define RTC_TSDR_MU_Pos                      (8U)
5842 #define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
5843 #define RTC_TSDR_MU                          RTC_TSDR_MU_Msk
5844 #define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
5845 #define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
5846 #define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
5847 #define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
5848 #define RTC_TSDR_DT_Pos                      (4U)
5849 #define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
5850 #define RTC_TSDR_DT                          RTC_TSDR_DT_Msk
5851 #define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
5852 #define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
5853 #define RTC_TSDR_DU_Pos                      (0U)
5854 #define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
5855 #define RTC_TSDR_DU                          RTC_TSDR_DU_Msk
5856 #define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
5857 #define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
5858 #define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
5859 #define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
5860 
5861 /********************  Bits definition for RTC_TSSSR register  ****************/
5862 #define RTC_TSSSR_SS_Pos                     (0U)
5863 #define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
5864 #define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk
5865 
5866 /********************  Bits definition for RTC_CAL register  *****************/
5867 #define RTC_CALR_CALP_Pos                    (15U)
5868 #define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
5869 #define RTC_CALR_CALP                        RTC_CALR_CALP_Msk
5870 #define RTC_CALR_CALW8_Pos                   (14U)
5871 #define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
5872 #define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk
5873 #define RTC_CALR_CALW16_Pos                  (13U)
5874 #define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
5875 #define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk
5876 #define RTC_CALR_CALM_Pos                    (0U)
5877 #define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
5878 #define RTC_CALR_CALM                        RTC_CALR_CALM_Msk
5879 #define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
5880 #define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
5881 #define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
5882 #define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
5883 #define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
5884 #define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
5885 #define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
5886 #define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
5887 #define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
5888 
5889 /********************  Bits definition for RTC_TAFCR register  ****************/
5890 #define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)
5891 #define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
5892 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk
5893 #define RTC_TAFCR_TAMPPUDIS_Pos              (15U)
5894 #define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
5895 #define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk
5896 #define RTC_TAFCR_TAMPPRCH_Pos               (13U)
5897 #define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
5898 #define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk
5899 #define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
5900 #define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
5901 #define RTC_TAFCR_TAMPFLT_Pos                (11U)
5902 #define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
5903 #define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk
5904 #define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
5905 #define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
5906 #define RTC_TAFCR_TAMPFREQ_Pos               (8U)
5907 #define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
5908 #define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk
5909 #define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
5910 #define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
5911 #define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
5912 #define RTC_TAFCR_TAMPTS_Pos                 (7U)
5913 #define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
5914 #define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk
5915 #define RTC_TAFCR_TAMP3TRG_Pos               (6U)
5916 #define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
5917 #define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk
5918 #define RTC_TAFCR_TAMP3E_Pos                 (5U)
5919 #define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
5920 #define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk
5921 #define RTC_TAFCR_TAMP2TRG_Pos               (4U)
5922 #define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
5923 #define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk
5924 #define RTC_TAFCR_TAMP2E_Pos                 (3U)
5925 #define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
5926 #define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk
5927 #define RTC_TAFCR_TAMPIE_Pos                 (2U)
5928 #define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
5929 #define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk
5930 #define RTC_TAFCR_TAMP1TRG_Pos               (1U)
5931 #define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
5932 #define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk
5933 #define RTC_TAFCR_TAMP1E_Pos                 (0U)
5934 #define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
5935 #define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk
5936 
5937 /********************  Bits definition for RTC_ALRMASSR register  *************/
5938 #define RTC_ALRMASSR_MASKSS_Pos              (24U)
5939 #define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5940 #define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk
5941 #define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5942 #define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5943 #define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5944 #define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5945 #define RTC_ALRMASSR_SS_Pos                  (0U)
5946 #define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
5947 #define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk
5948 
5949 /********************  Bits definition for RTC_ALRMBSSR register  *************/
5950 #define RTC_ALRMBSSR_MASKSS_Pos              (24U)
5951 #define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5952 #define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk
5953 #define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5954 #define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5955 #define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5956 #define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5957 #define RTC_ALRMBSSR_SS_Pos                  (0U)
5958 #define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
5959 #define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk
5960 
5961 /********************  Bits definition for RTC_BKP0R register  ****************/
5962 #define RTC_BKP0R_Pos                        (0U)
5963 #define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
5964 #define RTC_BKP0R                            RTC_BKP0R_Msk
5965 
5966 /********************  Bits definition for RTC_BKP1R register  ****************/
5967 #define RTC_BKP1R_Pos                        (0U)
5968 #define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
5969 #define RTC_BKP1R                            RTC_BKP1R_Msk
5970 
5971 /********************  Bits definition for RTC_BKP2R register  ****************/
5972 #define RTC_BKP2R_Pos                        (0U)
5973 #define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
5974 #define RTC_BKP2R                            RTC_BKP2R_Msk
5975 
5976 /********************  Bits definition for RTC_BKP3R register  ****************/
5977 #define RTC_BKP3R_Pos                        (0U)
5978 #define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
5979 #define RTC_BKP3R                            RTC_BKP3R_Msk
5980 
5981 /********************  Bits definition for RTC_BKP4R register  ****************/
5982 #define RTC_BKP4R_Pos                        (0U)
5983 #define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
5984 #define RTC_BKP4R                            RTC_BKP4R_Msk
5985 
5986 /********************  Bits definition for RTC_BKP5R register  ****************/
5987 #define RTC_BKP5R_Pos                        (0U)
5988 #define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
5989 #define RTC_BKP5R                            RTC_BKP5R_Msk
5990 
5991 /********************  Bits definition for RTC_BKP6R register  ****************/
5992 #define RTC_BKP6R_Pos                        (0U)
5993 #define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
5994 #define RTC_BKP6R                            RTC_BKP6R_Msk
5995 
5996 /********************  Bits definition for RTC_BKP7R register  ****************/
5997 #define RTC_BKP7R_Pos                        (0U)
5998 #define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
5999 #define RTC_BKP7R                            RTC_BKP7R_Msk
6000 
6001 /********************  Bits definition for RTC_BKP8R register  ****************/
6002 #define RTC_BKP8R_Pos                        (0U)
6003 #define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
6004 #define RTC_BKP8R                            RTC_BKP8R_Msk
6005 
6006 /********************  Bits definition for RTC_BKP9R register  ****************/
6007 #define RTC_BKP9R_Pos                        (0U)
6008 #define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
6009 #define RTC_BKP9R                            RTC_BKP9R_Msk
6010 
6011 /********************  Bits definition for RTC_BKP10R register  ***************/
6012 #define RTC_BKP10R_Pos                       (0U)
6013 #define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
6014 #define RTC_BKP10R                           RTC_BKP10R_Msk
6015 
6016 /********************  Bits definition for RTC_BKP11R register  ***************/
6017 #define RTC_BKP11R_Pos                       (0U)
6018 #define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
6019 #define RTC_BKP11R                           RTC_BKP11R_Msk
6020 
6021 /********************  Bits definition for RTC_BKP12R register  ***************/
6022 #define RTC_BKP12R_Pos                       (0U)
6023 #define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
6024 #define RTC_BKP12R                           RTC_BKP12R_Msk
6025 
6026 /********************  Bits definition for RTC_BKP13R register  ***************/
6027 #define RTC_BKP13R_Pos                       (0U)
6028 #define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
6029 #define RTC_BKP13R                           RTC_BKP13R_Msk
6030 
6031 /********************  Bits definition for RTC_BKP14R register  ***************/
6032 #define RTC_BKP14R_Pos                       (0U)
6033 #define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
6034 #define RTC_BKP14R                           RTC_BKP14R_Msk
6035 
6036 /********************  Bits definition for RTC_BKP15R register  ***************/
6037 #define RTC_BKP15R_Pos                       (0U)
6038 #define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
6039 #define RTC_BKP15R                           RTC_BKP15R_Msk
6040 
6041 /********************  Bits definition for RTC_BKP16R register  ***************/
6042 #define RTC_BKP16R_Pos                       (0U)
6043 #define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
6044 #define RTC_BKP16R                           RTC_BKP16R_Msk
6045 
6046 /********************  Bits definition for RTC_BKP17R register  ***************/
6047 #define RTC_BKP17R_Pos                       (0U)
6048 #define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
6049 #define RTC_BKP17R                           RTC_BKP17R_Msk
6050 
6051 /********************  Bits definition for RTC_BKP18R register  ***************/
6052 #define RTC_BKP18R_Pos                       (0U)
6053 #define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
6054 #define RTC_BKP18R                           RTC_BKP18R_Msk
6055 
6056 /********************  Bits definition for RTC_BKP19R register  ***************/
6057 #define RTC_BKP19R_Pos                       (0U)
6058 #define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
6059 #define RTC_BKP19R                           RTC_BKP19R_Msk
6060 
6061 /********************  Bits definition for RTC_BKP20R register  ***************/
6062 #define RTC_BKP20R_Pos                       (0U)
6063 #define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
6064 #define RTC_BKP20R                           RTC_BKP20R_Msk
6065 
6066 /********************  Bits definition for RTC_BKP21R register  ***************/
6067 #define RTC_BKP21R_Pos                       (0U)
6068 #define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
6069 #define RTC_BKP21R                           RTC_BKP21R_Msk
6070 
6071 /********************  Bits definition for RTC_BKP22R register  ***************/
6072 #define RTC_BKP22R_Pos                       (0U)
6073 #define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
6074 #define RTC_BKP22R                           RTC_BKP22R_Msk
6075 
6076 /********************  Bits definition for RTC_BKP23R register  ***************/
6077 #define RTC_BKP23R_Pos                       (0U)
6078 #define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
6079 #define RTC_BKP23R                           RTC_BKP23R_Msk
6080 
6081 /********************  Bits definition for RTC_BKP24R register  ***************/
6082 #define RTC_BKP24R_Pos                       (0U)
6083 #define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
6084 #define RTC_BKP24R                           RTC_BKP24R_Msk
6085 
6086 /********************  Bits definition for RTC_BKP25R register  ***************/
6087 #define RTC_BKP25R_Pos                       (0U)
6088 #define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
6089 #define RTC_BKP25R                           RTC_BKP25R_Msk
6090 
6091 /********************  Bits definition for RTC_BKP26R register  ***************/
6092 #define RTC_BKP26R_Pos                       (0U)
6093 #define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
6094 #define RTC_BKP26R                           RTC_BKP26R_Msk
6095 
6096 /********************  Bits definition for RTC_BKP27R register  ***************/
6097 #define RTC_BKP27R_Pos                       (0U)
6098 #define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
6099 #define RTC_BKP27R                           RTC_BKP27R_Msk
6100 
6101 /********************  Bits definition for RTC_BKP28R register  ***************/
6102 #define RTC_BKP28R_Pos                       (0U)
6103 #define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
6104 #define RTC_BKP28R                           RTC_BKP28R_Msk
6105 
6106 /********************  Bits definition for RTC_BKP29R register  ***************/
6107 #define RTC_BKP29R_Pos                       (0U)
6108 #define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
6109 #define RTC_BKP29R                           RTC_BKP29R_Msk
6110 
6111 /********************  Bits definition for RTC_BKP30R register  ***************/
6112 #define RTC_BKP30R_Pos                       (0U)
6113 #define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
6114 #define RTC_BKP30R                           RTC_BKP30R_Msk
6115 
6116 /********************  Bits definition for RTC_BKP31R register  ***************/
6117 #define RTC_BKP31R_Pos                       (0U)
6118 #define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
6119 #define RTC_BKP31R                           RTC_BKP31R_Msk
6120 
6121 /******************** Number of backup registers ******************************/
6122 #define RTC_BKP_NUMBER 32
6123 
6124 /******************************************************************************/
6125 /*                                                                            */
6126 /*                          SD host Interface                                 */
6127 /*                                                                            */
6128 /******************************************************************************/
6129 
6130 /******************  Bit definition for SDIO_POWER register  ******************/
6131 #define SDIO_POWER_PWRCTRL_Pos              (0U)
6132 #define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
6133 #define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
6134 #define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000001 */
6135 #define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000002 */
6136 
6137 /******************  Bit definition for SDIO_CLKCR register  ******************/
6138 #define SDIO_CLKCR_CLKDIV_Pos               (0U)
6139 #define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
6140 #define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
6141 #define SDIO_CLKCR_CLKEN_Pos                (8U)
6142 #define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
6143 #define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
6144 #define SDIO_CLKCR_PWRSAV_Pos               (9U)
6145 #define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
6146 #define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
6147 #define SDIO_CLKCR_BYPASS_Pos               (10U)
6148 #define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
6149 #define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
6150 
6151 #define SDIO_CLKCR_WIDBUS_Pos               (11U)
6152 #define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
6153 #define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
6154 #define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00000800 */
6155 #define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001000 */
6156 
6157 #define SDIO_CLKCR_NEGEDGE_Pos              (13U)
6158 #define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
6159 #define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
6160 #define SDIO_CLKCR_HWFC_EN_Pos              (14U)
6161 #define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
6162 #define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
6163 
6164 /*******************  Bit definition for SDIO_ARG register  *******************/
6165 #define SDIO_ARG_CMDARG_Pos                 (0U)
6166 #define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
6167 #define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
6168 
6169 /*******************  Bit definition for SDIO_CMD register  *******************/
6170 #define SDIO_CMD_CMDINDEX_Pos               (0U)
6171 #define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
6172 #define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
6173 
6174 #define SDIO_CMD_WAITRESP_Pos               (6U)
6175 #define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
6176 #define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
6177 #define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000040 */
6178 #define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000080 */
6179 
6180 #define SDIO_CMD_WAITINT_Pos                (8U)
6181 #define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
6182 #define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
6183 #define SDIO_CMD_WAITPEND_Pos               (9U)
6184 #define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
6185 #define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
6186 #define SDIO_CMD_CPSMEN_Pos                 (10U)
6187 #define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
6188 #define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
6189 #define SDIO_CMD_SDIOSUSPEND_Pos            (11U)
6190 #define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
6191 #define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
6192 #define SDIO_CMD_ENCMDCOMPL_Pos             (12U)
6193 #define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
6194 #define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
6195 #define SDIO_CMD_NIEN_Pos                   (13U)
6196 #define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
6197 #define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
6198 #define SDIO_CMD_CEATACMD_Pos               (14U)
6199 #define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
6200 #define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
6201 
6202 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
6203 #define SDIO_RESPCMD_RESPCMD_Pos            (0U)
6204 #define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
6205 #define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
6206 
6207 /******************  Bit definition for SDIO_RESP0 register  ******************/
6208 #define SDIO_RESP0_CARDSTATUS0_Pos          (0U)
6209 #define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
6210 #define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
6211 
6212 /******************  Bit definition for SDIO_RESP1 register  ******************/
6213 #define SDIO_RESP1_CARDSTATUS1_Pos          (0U)
6214 #define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
6215 #define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
6216 
6217 /******************  Bit definition for SDIO_RESP2 register  ******************/
6218 #define SDIO_RESP2_CARDSTATUS2_Pos          (0U)
6219 #define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
6220 #define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
6221 
6222 /******************  Bit definition for SDIO_RESP3 register  ******************/
6223 #define SDIO_RESP3_CARDSTATUS3_Pos          (0U)
6224 #define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
6225 #define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
6226 
6227 /******************  Bit definition for SDIO_RESP4 register  ******************/
6228 #define SDIO_RESP4_CARDSTATUS4_Pos          (0U)
6229 #define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
6230 #define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
6231 
6232 /******************  Bit definition for SDIO_DTIMER register  *****************/
6233 #define SDIO_DTIMER_DATATIME_Pos            (0U)
6234 #define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
6235 #define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
6236 
6237 /******************  Bit definition for SDIO_DLEN register  *******************/
6238 #define SDIO_DLEN_DATALENGTH_Pos            (0U)
6239 #define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
6240 #define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
6241 
6242 /******************  Bit definition for SDIO_DCTRL register  ******************/
6243 #define SDIO_DCTRL_DTEN_Pos                 (0U)
6244 #define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
6245 #define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
6246 #define SDIO_DCTRL_DTDIR_Pos                (1U)
6247 #define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
6248 #define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
6249 #define SDIO_DCTRL_DTMODE_Pos               (2U)
6250 #define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
6251 #define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
6252 #define SDIO_DCTRL_DMAEN_Pos                (3U)
6253 #define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
6254 #define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
6255 
6256 #define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)
6257 #define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
6258 #define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
6259 #define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
6260 #define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
6261 #define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
6262 #define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
6263 
6264 #define SDIO_DCTRL_RWSTART_Pos              (8U)
6265 #define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
6266 #define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
6267 #define SDIO_DCTRL_RWSTOP_Pos               (9U)
6268 #define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
6269 #define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
6270 #define SDIO_DCTRL_RWMOD_Pos                (10U)
6271 #define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
6272 #define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
6273 #define SDIO_DCTRL_SDIOEN_Pos               (11U)
6274 #define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
6275 #define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
6276 
6277 /******************  Bit definition for SDIO_DCOUNT register  *****************/
6278 #define SDIO_DCOUNT_DATACOUNT_Pos           (0U)
6279 #define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
6280 #define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
6281 
6282 /******************  Bit definition for SDIO_STA register  ********************/
6283 #define SDIO_STA_CCRCFAIL_Pos               (0U)
6284 #define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
6285 #define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
6286 #define SDIO_STA_DCRCFAIL_Pos               (1U)
6287 #define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
6288 #define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
6289 #define SDIO_STA_CTIMEOUT_Pos               (2U)
6290 #define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
6291 #define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
6292 #define SDIO_STA_DTIMEOUT_Pos               (3U)
6293 #define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
6294 #define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
6295 #define SDIO_STA_TXUNDERR_Pos               (4U)
6296 #define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
6297 #define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
6298 #define SDIO_STA_RXOVERR_Pos                (5U)
6299 #define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
6300 #define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
6301 #define SDIO_STA_CMDREND_Pos                (6U)
6302 #define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
6303 #define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
6304 #define SDIO_STA_CMDSENT_Pos                (7U)
6305 #define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
6306 #define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
6307 #define SDIO_STA_DATAEND_Pos                (8U)
6308 #define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
6309 #define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
6310 #define SDIO_STA_STBITERR_Pos               (9U)
6311 #define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
6312 #define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
6313 #define SDIO_STA_DBCKEND_Pos                (10U)
6314 #define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
6315 #define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
6316 #define SDIO_STA_CMDACT_Pos                 (11U)
6317 #define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
6318 #define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
6319 #define SDIO_STA_TXACT_Pos                  (12U)
6320 #define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
6321 #define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
6322 #define SDIO_STA_RXACT_Pos                  (13U)
6323 #define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
6324 #define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
6325 #define SDIO_STA_TXFIFOHE_Pos               (14U)
6326 #define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
6327 #define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
6328 #define SDIO_STA_RXFIFOHF_Pos               (15U)
6329 #define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
6330 #define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
6331 #define SDIO_STA_TXFIFOF_Pos                (16U)
6332 #define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
6333 #define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
6334 #define SDIO_STA_RXFIFOF_Pos                (17U)
6335 #define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
6336 #define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
6337 #define SDIO_STA_TXFIFOE_Pos                (18U)
6338 #define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
6339 #define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
6340 #define SDIO_STA_RXFIFOE_Pos                (19U)
6341 #define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
6342 #define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
6343 #define SDIO_STA_TXDAVL_Pos                 (20U)
6344 #define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
6345 #define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
6346 #define SDIO_STA_RXDAVL_Pos                 (21U)
6347 #define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
6348 #define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
6349 #define SDIO_STA_SDIOIT_Pos                 (22U)
6350 #define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
6351 #define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
6352 #define SDIO_STA_CEATAEND_Pos               (23U)
6353 #define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
6354 #define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
6355 
6356 /*******************  Bit definition for SDIO_ICR register  *******************/
6357 #define SDIO_ICR_CCRCFAILC_Pos              (0U)
6358 #define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
6359 #define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
6360 #define SDIO_ICR_DCRCFAILC_Pos              (1U)
6361 #define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
6362 #define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
6363 #define SDIO_ICR_CTIMEOUTC_Pos              (2U)
6364 #define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
6365 #define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
6366 #define SDIO_ICR_DTIMEOUTC_Pos              (3U)
6367 #define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
6368 #define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
6369 #define SDIO_ICR_TXUNDERRC_Pos              (4U)
6370 #define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
6371 #define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
6372 #define SDIO_ICR_RXOVERRC_Pos               (5U)
6373 #define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
6374 #define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
6375 #define SDIO_ICR_CMDRENDC_Pos               (6U)
6376 #define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
6377 #define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
6378 #define SDIO_ICR_CMDSENTC_Pos               (7U)
6379 #define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
6380 #define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
6381 #define SDIO_ICR_DATAENDC_Pos               (8U)
6382 #define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
6383 #define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
6384 #define SDIO_ICR_STBITERRC_Pos              (9U)
6385 #define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
6386 #define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
6387 #define SDIO_ICR_DBCKENDC_Pos               (10U)
6388 #define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
6389 #define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
6390 #define SDIO_ICR_SDIOITC_Pos                (22U)
6391 #define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
6392 #define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
6393 #define SDIO_ICR_CEATAENDC_Pos              (23U)
6394 #define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
6395 #define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
6396 
6397 /******************  Bit definition for SDIO_MASK register  *******************/
6398 #define SDIO_MASK_CCRCFAILIE_Pos            (0U)
6399 #define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
6400 #define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
6401 #define SDIO_MASK_DCRCFAILIE_Pos            (1U)
6402 #define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
6403 #define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
6404 #define SDIO_MASK_CTIMEOUTIE_Pos            (2U)
6405 #define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
6406 #define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
6407 #define SDIO_MASK_DTIMEOUTIE_Pos            (3U)
6408 #define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
6409 #define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
6410 #define SDIO_MASK_TXUNDERRIE_Pos            (4U)
6411 #define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
6412 #define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
6413 #define SDIO_MASK_RXOVERRIE_Pos             (5U)
6414 #define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
6415 #define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
6416 #define SDIO_MASK_CMDRENDIE_Pos             (6U)
6417 #define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
6418 #define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
6419 #define SDIO_MASK_CMDSENTIE_Pos             (7U)
6420 #define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
6421 #define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
6422 #define SDIO_MASK_DATAENDIE_Pos             (8U)
6423 #define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
6424 #define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
6425 #define SDIO_MASK_STBITERRIE_Pos            (9U)
6426 #define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
6427 #define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
6428 #define SDIO_MASK_DBCKENDIE_Pos             (10U)
6429 #define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
6430 #define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
6431 #define SDIO_MASK_CMDACTIE_Pos              (11U)
6432 #define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
6433 #define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
6434 #define SDIO_MASK_TXACTIE_Pos               (12U)
6435 #define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
6436 #define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
6437 #define SDIO_MASK_RXACTIE_Pos               (13U)
6438 #define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
6439 #define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
6440 #define SDIO_MASK_TXFIFOHEIE_Pos            (14U)
6441 #define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
6442 #define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
6443 #define SDIO_MASK_RXFIFOHFIE_Pos            (15U)
6444 #define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
6445 #define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
6446 #define SDIO_MASK_TXFIFOFIE_Pos             (16U)
6447 #define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
6448 #define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
6449 #define SDIO_MASK_RXFIFOFIE_Pos             (17U)
6450 #define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
6451 #define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
6452 #define SDIO_MASK_TXFIFOEIE_Pos             (18U)
6453 #define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
6454 #define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
6455 #define SDIO_MASK_RXFIFOEIE_Pos             (19U)
6456 #define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
6457 #define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
6458 #define SDIO_MASK_TXDAVLIE_Pos              (20U)
6459 #define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
6460 #define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
6461 #define SDIO_MASK_RXDAVLIE_Pos              (21U)
6462 #define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
6463 #define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
6464 #define SDIO_MASK_SDIOITIE_Pos              (22U)
6465 #define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
6466 #define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
6467 #define SDIO_MASK_CEATAENDIE_Pos            (23U)
6468 #define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
6469 #define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
6470 
6471 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
6472 #define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)
6473 #define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
6474 #define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
6475 
6476 /******************  Bit definition for SDIO_FIFO register  *******************/
6477 #define SDIO_FIFO_FIFODATA_Pos              (0U)
6478 #define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
6479 #define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
6480 
6481 /******************************************************************************/
6482 /*                                                                            */
6483 /*                     Serial Peripheral Interface (SPI)                      */
6484 /*                                                                            */
6485 /******************************************************************************/
6486 
6487 /*
6488  * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
6489  */
6490 #define SPI_I2S_SUPPORT
6491 
6492 /*******************  Bit definition for SPI_CR1 register  ********************/
6493 #define SPI_CR1_CPHA_Pos                    (0U)
6494 #define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
6495 #define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
6496 #define SPI_CR1_CPOL_Pos                    (1U)
6497 #define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
6498 #define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
6499 #define SPI_CR1_MSTR_Pos                    (2U)
6500 #define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
6501 #define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
6502 
6503 #define SPI_CR1_BR_Pos                      (3U)
6504 #define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
6505 #define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
6506 #define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
6507 #define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
6508 #define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
6509 
6510 #define SPI_CR1_SPE_Pos                     (6U)
6511 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
6512 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
6513 #define SPI_CR1_LSBFIRST_Pos                (7U)
6514 #define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
6515 #define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
6516 #define SPI_CR1_SSI_Pos                     (8U)
6517 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
6518 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
6519 #define SPI_CR1_SSM_Pos                     (9U)
6520 #define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
6521 #define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
6522 #define SPI_CR1_RXONLY_Pos                  (10U)
6523 #define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
6524 #define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
6525 #define SPI_CR1_DFF_Pos                     (11U)
6526 #define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
6527 #define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
6528 #define SPI_CR1_CRCNEXT_Pos                 (12U)
6529 #define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
6530 #define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
6531 #define SPI_CR1_CRCEN_Pos                   (13U)
6532 #define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
6533 #define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
6534 #define SPI_CR1_BIDIOE_Pos                  (14U)
6535 #define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
6536 #define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
6537 #define SPI_CR1_BIDIMODE_Pos                (15U)
6538 #define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
6539 #define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
6540 
6541 /*******************  Bit definition for SPI_CR2 register  ********************/
6542 #define SPI_CR2_RXDMAEN_Pos                 (0U)
6543 #define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
6544 #define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
6545 #define SPI_CR2_TXDMAEN_Pos                 (1U)
6546 #define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
6547 #define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
6548 #define SPI_CR2_SSOE_Pos                    (2U)
6549 #define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
6550 #define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
6551 #define SPI_CR2_FRF_Pos                     (4U)
6552 #define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
6553 #define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
6554 #define SPI_CR2_ERRIE_Pos                   (5U)
6555 #define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
6556 #define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
6557 #define SPI_CR2_RXNEIE_Pos                  (6U)
6558 #define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
6559 #define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
6560 #define SPI_CR2_TXEIE_Pos                   (7U)
6561 #define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
6562 #define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
6563 
6564 /********************  Bit definition for SPI_SR register  ********************/
6565 #define SPI_SR_RXNE_Pos                     (0U)
6566 #define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
6567 #define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
6568 #define SPI_SR_TXE_Pos                      (1U)
6569 #define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
6570 #define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
6571 #define SPI_SR_CHSIDE_Pos                   (2U)
6572 #define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
6573 #define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
6574 #define SPI_SR_UDR_Pos                      (3U)
6575 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
6576 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
6577 #define SPI_SR_CRCERR_Pos                   (4U)
6578 #define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
6579 #define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
6580 #define SPI_SR_MODF_Pos                     (5U)
6581 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
6582 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
6583 #define SPI_SR_OVR_Pos                      (6U)
6584 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
6585 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
6586 #define SPI_SR_BSY_Pos                      (7U)
6587 #define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
6588 #define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
6589 #define SPI_SR_FRE_Pos                      (8U)
6590 #define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
6591 #define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
6592 
6593 /********************  Bit definition for SPI_DR register  ********************/
6594 #define SPI_DR_DR_Pos                       (0U)
6595 #define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
6596 #define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
6597 
6598 /*******************  Bit definition for SPI_CRCPR register  ******************/
6599 #define SPI_CRCPR_CRCPOLY_Pos               (0U)
6600 #define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
6601 #define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
6602 
6603 /******************  Bit definition for SPI_RXCRCR register  ******************/
6604 #define SPI_RXCRCR_RXCRC_Pos                (0U)
6605 #define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
6606 #define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
6607 
6608 /******************  Bit definition for SPI_TXCRCR register  ******************/
6609 #define SPI_TXCRCR_TXCRC_Pos                (0U)
6610 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
6611 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
6612 
6613 /******************  Bit definition for SPI_I2SCFGR register  *****************/
6614 #define SPI_I2SCFGR_CHLEN_Pos               (0U)
6615 #define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
6616 #define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
6617 
6618 #define SPI_I2SCFGR_DATLEN_Pos              (1U)
6619 #define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
6620 #define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
6621 #define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
6622 #define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
6623 
6624 #define SPI_I2SCFGR_CKPOL_Pos               (3U)
6625 #define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
6626 #define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
6627 
6628 #define SPI_I2SCFGR_I2SSTD_Pos              (4U)
6629 #define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
6630 #define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
6631 #define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
6632 #define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
6633 
6634 #define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
6635 #define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
6636 #define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
6637 
6638 #define SPI_I2SCFGR_I2SCFG_Pos              (8U)
6639 #define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
6640 #define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6641 #define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
6642 #define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
6643 
6644 #define SPI_I2SCFGR_I2SE_Pos                (10U)
6645 #define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
6646 #define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
6647 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)
6648 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
6649 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
6650 
6651 /******************  Bit definition for SPI_I2SPR register  *******************/
6652 #define SPI_I2SPR_I2SDIV_Pos                (0U)
6653 #define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
6654 #define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
6655 #define SPI_I2SPR_ODD_Pos                   (8U)
6656 #define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
6657 #define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
6658 #define SPI_I2SPR_MCKOE_Pos                 (9U)
6659 #define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
6660 #define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
6661 
6662 /******************************************************************************/
6663 /*                                                                            */
6664 /*                       System Configuration (SYSCFG)                        */
6665 /*                                                                            */
6666 /******************************************************************************/
6667 /*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
6668 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
6669 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
6670 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
6671 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
6672 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
6673 #define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)
6674 #define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
6675 #define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
6676 #define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
6677 #define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
6678 
6679 /*****************  Bit definition for SYSCFG_PMC register  *******************/
6680 #define SYSCFG_PMC_USB_PU_Pos           (0U)
6681 #define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
6682 #define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
6683 #define SYSCFG_PMC_LCD_CAPA_Pos         (1U)
6684 #define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
6685 #define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
6686 #define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
6687 #define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
6688 #define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
6689 #define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
6690 #define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
6691 
6692 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
6693 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
6694 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
6695 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
6696 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
6697 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
6698 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
6699 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
6700 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
6701 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
6702 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
6703 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
6704 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
6705 
6706 /**
6707   * @brief  EXTI0 configuration
6708   */
6709 #define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
6710 #define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
6711 #define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
6712 #define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
6713 #define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
6714 #define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
6715 #define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
6716 #define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
6717 
6718 /**
6719   * @brief  EXTI1 configuration
6720   */
6721 #define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
6722 #define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
6723 #define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
6724 #define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
6725 #define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
6726 #define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
6727 #define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
6728 #define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
6729 
6730 /**
6731   * @brief  EXTI2 configuration
6732   */
6733 #define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
6734 #define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
6735 #define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
6736 #define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
6737 #define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
6738 #define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
6739 #define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
6740 #define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
6741 
6742 /**
6743   * @brief  EXTI3 configuration
6744   */
6745 #define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
6746 #define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
6747 #define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
6748 #define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
6749 #define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
6750 #define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
6751 #define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
6752 
6753 /*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
6754 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
6755 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
6756 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
6757 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
6758 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
6759 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
6760 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
6761 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
6762 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
6763 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
6764 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
6765 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
6766 
6767 /**
6768   * @brief  EXTI4 configuration
6769   */
6770 #define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
6771 #define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
6772 #define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
6773 #define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
6774 #define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
6775 #define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
6776 #define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
6777 
6778 /**
6779   * @brief  EXTI5 configuration
6780   */
6781 #define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
6782 #define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
6783 #define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
6784 #define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
6785 #define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
6786 #define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
6787 #define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
6788 
6789 /**
6790   * @brief  EXTI6 configuration
6791   */
6792 #define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
6793 #define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
6794 #define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
6795 #define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
6796 #define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
6797 #define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
6798 #define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
6799 
6800 /**
6801   * @brief  EXTI7 configuration
6802   */
6803 #define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
6804 #define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
6805 #define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
6806 #define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
6807 #define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
6808 #define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
6809 #define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
6810 
6811 /*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
6812 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
6813 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
6814 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
6815 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
6816 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
6817 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
6818 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
6819 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
6820 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
6821 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
6822 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
6823 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
6824 
6825 /**
6826   * @brief  EXTI8 configuration
6827   */
6828 #define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
6829 #define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
6830 #define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
6831 #define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
6832 #define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
6833 #define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
6834 #define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
6835 
6836 /**
6837   * @brief  EXTI9 configuration
6838   */
6839 #define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
6840 #define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
6841 #define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
6842 #define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
6843 #define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
6844 #define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
6845 #define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
6846 
6847 /**
6848   * @brief  EXTI10 configuration
6849   */
6850 #define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
6851 #define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
6852 #define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
6853 #define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
6854 #define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
6855 #define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
6856 #define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
6857 
6858 /**
6859   * @brief  EXTI11 configuration
6860   */
6861 #define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
6862 #define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
6863 #define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
6864 #define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
6865 #define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
6866 #define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
6867 #define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
6868 
6869 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
6870 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
6871 #define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
6872 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
6873 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
6874 #define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
6875 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
6876 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
6877 #define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
6878 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
6879 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
6880 #define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
6881 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
6882 
6883 /**
6884   * @brief  EXTI12 configuration
6885   */
6886 #define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
6887 #define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
6888 #define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
6889 #define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
6890 #define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
6891 #define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
6892 #define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
6893 
6894 /**
6895   * @brief  EXTI13 configuration
6896   */
6897 #define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
6898 #define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
6899 #define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
6900 #define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
6901 #define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
6902 #define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
6903 #define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
6904 
6905 /**
6906   * @brief  EXTI14 configuration
6907   */
6908 #define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
6909 #define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
6910 #define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
6911 #define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
6912 #define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
6913 #define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
6914 #define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
6915 
6916 /**
6917   * @brief  EXTI15 configuration
6918   */
6919 #define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
6920 #define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
6921 #define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
6922 #define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
6923 #define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
6924 #define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
6925 #define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
6926 
6927 /******************************************************************************/
6928 /*                                                                            */
6929 /*                       Routing Interface (RI)                               */
6930 /*                                                                            */
6931 /******************************************************************************/
6932 
6933 /********************  Bit definition for RI_ICR register  ********************/
6934 #define RI_ICR_IC1OS_Pos                (0U)
6935 #define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
6936 #define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
6937 #define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
6938 #define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
6939 #define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
6940 #define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
6941 
6942 #define RI_ICR_IC2OS_Pos                (4U)
6943 #define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
6944 #define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
6945 #define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
6946 #define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
6947 #define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
6948 #define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
6949 
6950 #define RI_ICR_IC3OS_Pos                (8U)
6951 #define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
6952 #define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
6953 #define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
6954 #define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
6955 #define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
6956 #define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
6957 
6958 #define RI_ICR_IC4OS_Pos                (12U)
6959 #define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
6960 #define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
6961 #define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
6962 #define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
6963 #define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
6964 #define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
6965 
6966 #define RI_ICR_TIM_Pos                  (16U)
6967 #define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
6968 #define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
6969 #define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
6970 #define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
6971 
6972 #define RI_ICR_IC1_Pos                  (18U)
6973 #define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
6974 #define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
6975 #define RI_ICR_IC2_Pos                  (19U)
6976 #define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
6977 #define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
6978 #define RI_ICR_IC3_Pos                  (20U)
6979 #define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
6980 #define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
6981 #define RI_ICR_IC4_Pos                  (21U)
6982 #define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
6983 #define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
6984 
6985 /********************  Bit definition for RI_ASCR1 register  ********************/
6986 #define RI_ASCR1_CH_Pos                 (0U)
6987 #define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
6988 #define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
6989 #define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
6990 #define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
6991 #define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
6992 #define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
6993 #define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
6994 #define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
6995 #define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
6996 #define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
6997 #define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
6998 #define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
6999 #define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
7000 #define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
7001 #define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
7002 #define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
7003 #define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
7004 #define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
7005 #define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
7006 #define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
7007 #define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
7008 #define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
7009 #define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
7010 #define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
7011 #define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
7012 #define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
7013 #define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
7014 #define RI_ASCR1_VCOMP_Pos              (26U)
7015 #define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
7016 #define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
7017 #define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
7018 #define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
7019 #define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
7020 #define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
7021 #define RI_ASCR1_SCM_Pos                (31U)
7022 #define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
7023 #define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
7024 
7025 /********************  Bit definition for RI_ASCR2 register  ********************/
7026 #define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
7027 #define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
7028 #define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
7029 #define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
7030 #define RI_ASCR2_GR6_Pos                (4U)
7031 #define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
7032 #define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
7033 #define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
7034 #define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
7035 #define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
7036 #define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
7037 #define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
7038 #define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
7039 #define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
7040 #define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
7041 #define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
7042 #define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
7043 #define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
7044 #define RI_ASCR2_CH0b_Pos               (16U)
7045 #define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
7046 #define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
7047 #define RI_ASCR2_CH1b_Pos               (17U)
7048 #define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
7049 #define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
7050 #define RI_ASCR2_CH2b_Pos               (18U)
7051 #define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
7052 #define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
7053 #define RI_ASCR2_CH3b_Pos               (19U)
7054 #define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
7055 #define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
7056 #define RI_ASCR2_CH6b_Pos               (20U)
7057 #define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
7058 #define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
7059 #define RI_ASCR2_CH7b_Pos               (21U)
7060 #define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
7061 #define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
7062 #define RI_ASCR2_CH8b_Pos               (22U)
7063 #define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
7064 #define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
7065 #define RI_ASCR2_CH9b_Pos               (23U)
7066 #define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
7067 #define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
7068 #define RI_ASCR2_CH10b_Pos              (24U)
7069 #define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
7070 #define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
7071 #define RI_ASCR2_CH11b_Pos              (25U)
7072 #define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
7073 #define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
7074 #define RI_ASCR2_CH12b_Pos              (26U)
7075 #define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
7076 #define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
7077 
7078 /********************  Bit definition for RI_HYSCR1 register  ********************/
7079 #define RI_HYSCR1_PA_Pos                (0U)
7080 #define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
7081 #define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
7082 #define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
7083 #define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
7084 #define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
7085 #define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
7086 #define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
7087 #define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
7088 #define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
7089 #define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
7090 #define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
7091 #define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
7092 #define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
7093 #define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
7094 #define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
7095 #define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
7096 #define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
7097 #define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
7098 
7099 #define RI_HYSCR1_PB_Pos                (16U)
7100 #define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
7101 #define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
7102 #define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
7103 #define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
7104 #define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
7105 #define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
7106 #define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
7107 #define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
7108 #define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
7109 #define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
7110 #define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
7111 #define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
7112 #define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
7113 #define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
7114 #define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
7115 #define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
7116 #define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
7117 #define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
7118 
7119 /********************  Bit definition for RI_HYSCR2 register  ********************/
7120 #define RI_HYSCR2_PC_Pos                (0U)
7121 #define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
7122 #define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
7123 #define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
7124 #define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
7125 #define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
7126 #define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
7127 #define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
7128 #define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
7129 #define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
7130 #define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
7131 #define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
7132 #define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
7133 #define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
7134 #define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
7135 #define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
7136 #define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
7137 #define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
7138 #define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
7139 
7140 #define RI_HYSCR2_PD_Pos                (16U)
7141 #define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
7142 #define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
7143 #define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
7144 #define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
7145 #define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
7146 #define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
7147 #define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
7148 #define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
7149 #define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
7150 #define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
7151 #define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
7152 #define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
7153 #define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
7154 #define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
7155 #define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
7156 #define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
7157 #define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
7158 #define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
7159 
7160 /********************  Bit definition for RI_HYSCR3 register  ********************/
7161 #define RI_HYSCR3_PE_Pos                (0U)
7162 #define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
7163 #define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
7164 #define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
7165 #define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
7166 #define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
7167 #define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
7168 #define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
7169 #define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
7170 #define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
7171 #define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
7172 #define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
7173 #define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
7174 #define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
7175 #define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
7176 #define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
7177 #define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
7178 #define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
7179 #define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
7180 #define RI_HYSCR3_PF_Pos                (16U)
7181 #define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
7182 #define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
7183 #define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
7184 #define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
7185 #define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
7186 #define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
7187 #define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
7188 #define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
7189 #define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
7190 #define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
7191 #define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
7192 #define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
7193 #define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
7194 #define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
7195 #define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
7196 #define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
7197 #define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
7198 #define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
7199 /********************  Bit definition for RI_HYSCR4 register  ********************/
7200 #define RI_HYSCR4_PG_Pos                (0U)
7201 #define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
7202 #define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
7203 #define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
7204 #define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
7205 #define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
7206 #define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
7207 #define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
7208 #define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
7209 #define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
7210 #define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
7211 #define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
7212 #define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
7213 #define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
7214 #define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
7215 #define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
7216 #define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
7217 #define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
7218 #define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
7219 
7220 /********************  Bit definition for RI_ASMR1 register  ********************/
7221 #define RI_ASMR1_PA_Pos                 (0U)
7222 #define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
7223 #define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
7224 #define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
7225 #define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
7226 #define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
7227 #define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
7228 #define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
7229 #define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
7230 #define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
7231 #define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
7232 #define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
7233 #define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
7234 #define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
7235 #define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
7236 #define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
7237 #define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
7238 #define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
7239 #define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
7240 
7241 /********************  Bit definition for RI_CMR1 register  ********************/
7242 #define RI_CMR1_PA_Pos                  (0U)
7243 #define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
7244 #define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
7245 #define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
7246 #define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
7247 #define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
7248 #define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
7249 #define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
7250 #define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
7251 #define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
7252 #define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
7253 #define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
7254 #define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
7255 #define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
7256 #define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
7257 #define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
7258 #define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
7259 #define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
7260 #define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
7261 
7262 /********************  Bit definition for RI_CICR1 register  ********************/
7263 #define RI_CICR1_PA_Pos                 (0U)
7264 #define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
7265 #define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
7266 #define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
7267 #define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
7268 #define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
7269 #define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
7270 #define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
7271 #define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
7272 #define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
7273 #define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
7274 #define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
7275 #define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
7276 #define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
7277 #define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
7278 #define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
7279 #define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
7280 #define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
7281 #define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
7282 
7283 /********************  Bit definition for RI_ASMR2 register  ********************/
7284 #define RI_ASMR2_PB_Pos                 (0U)
7285 #define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
7286 #define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
7287 #define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
7288 #define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
7289 #define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
7290 #define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
7291 #define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
7292 #define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
7293 #define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
7294 #define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
7295 #define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
7296 #define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
7297 #define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
7298 #define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
7299 #define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
7300 #define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
7301 #define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
7302 #define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
7303 
7304 /********************  Bit definition for RI_CMR2 register  ********************/
7305 #define RI_CMR2_PB_Pos                  (0U)
7306 #define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
7307 #define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
7308 #define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
7309 #define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
7310 #define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
7311 #define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
7312 #define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
7313 #define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
7314 #define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
7315 #define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
7316 #define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
7317 #define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
7318 #define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
7319 #define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
7320 #define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
7321 #define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
7322 #define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
7323 #define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
7324 
7325 /********************  Bit definition for RI_CICR2 register  ********************/
7326 #define RI_CICR2_PB_Pos                 (0U)
7327 #define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
7328 #define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
7329 #define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
7330 #define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
7331 #define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
7332 #define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
7333 #define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
7334 #define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
7335 #define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
7336 #define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
7337 #define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
7338 #define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
7339 #define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
7340 #define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
7341 #define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
7342 #define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
7343 #define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
7344 #define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
7345 
7346 /********************  Bit definition for RI_ASMR3 register  ********************/
7347 #define RI_ASMR3_PC_Pos                 (0U)
7348 #define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
7349 #define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
7350 #define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
7351 #define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
7352 #define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
7353 #define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
7354 #define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
7355 #define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
7356 #define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
7357 #define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
7358 #define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
7359 #define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
7360 #define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
7361 #define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
7362 #define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
7363 #define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
7364 #define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
7365 #define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
7366 
7367 /********************  Bit definition for RI_CMR3 register  ********************/
7368 #define RI_CMR3_PC_Pos                  (0U)
7369 #define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
7370 #define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
7371 #define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
7372 #define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
7373 #define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
7374 #define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
7375 #define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
7376 #define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
7377 #define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
7378 #define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
7379 #define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
7380 #define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
7381 #define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
7382 #define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
7383 #define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
7384 #define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
7385 #define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
7386 #define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
7387 
7388 /********************  Bit definition for RI_CICR3 register  ********************/
7389 #define RI_CICR3_PC_Pos                 (0U)
7390 #define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
7391 #define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
7392 #define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
7393 #define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
7394 #define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
7395 #define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
7396 #define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
7397 #define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
7398 #define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
7399 #define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
7400 #define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
7401 #define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
7402 #define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
7403 #define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
7404 #define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
7405 #define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
7406 #define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
7407 #define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
7408 
7409 /********************  Bit definition for RI_ASMR4 register  ********************/
7410 #define RI_ASMR4_PF_Pos                 (0U)
7411 #define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
7412 #define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
7413 #define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
7414 #define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
7415 #define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
7416 #define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
7417 #define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
7418 #define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
7419 #define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
7420 #define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
7421 #define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
7422 #define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
7423 #define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
7424 #define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
7425 #define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
7426 #define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
7427 #define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
7428 #define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
7429 
7430 /********************  Bit definition for RI_CMR4 register  ********************/
7431 #define RI_CMR4_PF_Pos                  (0U)
7432 #define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
7433 #define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
7434 #define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
7435 #define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
7436 #define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
7437 #define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
7438 #define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
7439 #define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
7440 #define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
7441 #define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
7442 #define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
7443 #define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
7444 #define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
7445 #define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
7446 #define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
7447 #define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
7448 #define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
7449 #define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
7450 
7451 /********************  Bit definition for RI_CICR4 register  ********************/
7452 #define RI_CICR4_PF_Pos                 (0U)
7453 #define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
7454 #define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
7455 #define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
7456 #define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
7457 #define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
7458 #define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
7459 #define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
7460 #define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
7461 #define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
7462 #define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
7463 #define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
7464 #define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
7465 #define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
7466 #define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
7467 #define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
7468 #define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
7469 #define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
7470 #define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
7471 
7472 /********************  Bit definition for RI_ASMR5 register  ********************/
7473 #define RI_ASMR5_PG_Pos                 (0U)
7474 #define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
7475 #define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
7476 #define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
7477 #define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
7478 #define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
7479 #define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
7480 #define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
7481 #define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
7482 #define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
7483 #define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
7484 #define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
7485 #define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
7486 #define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
7487 #define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
7488 #define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
7489 #define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
7490 #define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
7491 #define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
7492 
7493 /********************  Bit definition for RI_CMR5 register  ********************/
7494 #define RI_CMR5_PG_Pos                  (0U)
7495 #define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
7496 #define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
7497 #define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
7498 #define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
7499 #define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
7500 #define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
7501 #define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
7502 #define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
7503 #define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
7504 #define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
7505 #define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
7506 #define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
7507 #define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
7508 #define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
7509 #define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
7510 #define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
7511 #define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
7512 #define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
7513 
7514 /********************  Bit definition for RI_CICR5 register  ********************/
7515 #define RI_CICR5_PG_Pos                 (0U)
7516 #define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
7517 #define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
7518 #define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
7519 #define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
7520 #define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
7521 #define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
7522 #define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
7523 #define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
7524 #define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
7525 #define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
7526 #define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
7527 #define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
7528 #define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
7529 #define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
7530 #define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
7531 #define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
7532 #define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
7533 #define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
7534 
7535 /******************************************************************************/
7536 /*                                                                            */
7537 /*                               Timers (TIM)                                 */
7538 /*                                                                            */
7539 /******************************************************************************/
7540 
7541 /*******************  Bit definition for TIM_CR1 register  ********************/
7542 #define TIM_CR1_CEN_Pos                     (0U)
7543 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
7544 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
7545 #define TIM_CR1_UDIS_Pos                    (1U)
7546 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
7547 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
7548 #define TIM_CR1_URS_Pos                     (2U)
7549 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
7550 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
7551 #define TIM_CR1_OPM_Pos                     (3U)
7552 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
7553 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
7554 #define TIM_CR1_DIR_Pos                     (4U)
7555 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
7556 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
7557 
7558 #define TIM_CR1_CMS_Pos                     (5U)
7559 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
7560 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
7561 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
7562 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
7563 
7564 #define TIM_CR1_ARPE_Pos                    (7U)
7565 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
7566 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
7567 
7568 #define TIM_CR1_CKD_Pos                     (8U)
7569 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
7570 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
7571 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
7572 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
7573 
7574 /*******************  Bit definition for TIM_CR2 register  ********************/
7575 #define TIM_CR2_CCDS_Pos                    (3U)
7576 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
7577 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
7578 
7579 #define TIM_CR2_MMS_Pos                     (4U)
7580 #define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
7581 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
7582 #define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
7583 #define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
7584 #define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
7585 
7586 #define TIM_CR2_TI1S_Pos                    (7U)
7587 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
7588 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
7589 
7590 /*******************  Bit definition for TIM_SMCR register  *******************/
7591 #define TIM_SMCR_SMS_Pos                    (0U)
7592 #define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
7593 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
7594 #define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
7595 #define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
7596 #define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
7597 
7598 #define TIM_SMCR_OCCS_Pos                   (3U)
7599 #define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
7600 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
7601 
7602 #define TIM_SMCR_TS_Pos                     (4U)
7603 #define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
7604 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
7605 #define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
7606 #define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
7607 #define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
7608 
7609 #define TIM_SMCR_MSM_Pos                    (7U)
7610 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
7611 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
7612 
7613 #define TIM_SMCR_ETF_Pos                    (8U)
7614 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
7615 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
7616 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
7617 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
7618 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
7619 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
7620 
7621 #define TIM_SMCR_ETPS_Pos                   (12U)
7622 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
7623 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
7624 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
7625 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
7626 
7627 #define TIM_SMCR_ECE_Pos                    (14U)
7628 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
7629 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
7630 #define TIM_SMCR_ETP_Pos                    (15U)
7631 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
7632 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
7633 
7634 /*******************  Bit definition for TIM_DIER register  *******************/
7635 #define TIM_DIER_UIE_Pos                    (0U)
7636 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
7637 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
7638 #define TIM_DIER_CC1IE_Pos                  (1U)
7639 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
7640 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
7641 #define TIM_DIER_CC2IE_Pos                  (2U)
7642 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
7643 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
7644 #define TIM_DIER_CC3IE_Pos                  (3U)
7645 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
7646 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
7647 #define TIM_DIER_CC4IE_Pos                  (4U)
7648 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
7649 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
7650 #define TIM_DIER_TIE_Pos                    (6U)
7651 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
7652 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
7653 #define TIM_DIER_UDE_Pos                    (8U)
7654 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
7655 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
7656 #define TIM_DIER_CC1DE_Pos                  (9U)
7657 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
7658 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
7659 #define TIM_DIER_CC2DE_Pos                  (10U)
7660 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
7661 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
7662 #define TIM_DIER_CC3DE_Pos                  (11U)
7663 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
7664 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
7665 #define TIM_DIER_CC4DE_Pos                  (12U)
7666 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
7667 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
7668 #define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
7669 #define TIM_DIER_TDE_Pos                    (14U)
7670 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
7671 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
7672 
7673 /********************  Bit definition for TIM_SR register  ********************/
7674 #define TIM_SR_UIF_Pos                      (0U)
7675 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
7676 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
7677 #define TIM_SR_CC1IF_Pos                    (1U)
7678 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
7679 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
7680 #define TIM_SR_CC2IF_Pos                    (2U)
7681 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
7682 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
7683 #define TIM_SR_CC3IF_Pos                    (3U)
7684 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
7685 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
7686 #define TIM_SR_CC4IF_Pos                    (4U)
7687 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
7688 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
7689 #define TIM_SR_TIF_Pos                      (6U)
7690 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
7691 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
7692 #define TIM_SR_CC1OF_Pos                    (9U)
7693 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
7694 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
7695 #define TIM_SR_CC2OF_Pos                    (10U)
7696 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
7697 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
7698 #define TIM_SR_CC3OF_Pos                    (11U)
7699 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
7700 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
7701 #define TIM_SR_CC4OF_Pos                    (12U)
7702 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
7703 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
7704 
7705 /*******************  Bit definition for TIM_EGR register  ********************/
7706 #define TIM_EGR_UG_Pos                      (0U)
7707 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
7708 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
7709 #define TIM_EGR_CC1G_Pos                    (1U)
7710 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
7711 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
7712 #define TIM_EGR_CC2G_Pos                    (2U)
7713 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
7714 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
7715 #define TIM_EGR_CC3G_Pos                    (3U)
7716 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
7717 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
7718 #define TIM_EGR_CC4G_Pos                    (4U)
7719 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
7720 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
7721 #define TIM_EGR_TG_Pos                      (6U)
7722 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
7723 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
7724 
7725 /******************  Bit definition for TIM_CCMR1 register  *******************/
7726 #define TIM_CCMR1_CC1S_Pos                  (0U)
7727 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
7728 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7729 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
7730 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
7731 
7732 #define TIM_CCMR1_OC1FE_Pos                 (2U)
7733 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
7734 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
7735 #define TIM_CCMR1_OC1PE_Pos                 (3U)
7736 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
7737 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
7738 
7739 #define TIM_CCMR1_OC1M_Pos                  (4U)
7740 #define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
7741 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7742 #define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
7743 #define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
7744 #define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
7745 
7746 #define TIM_CCMR1_OC1CE_Pos                 (7U)
7747 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
7748 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
7749 
7750 #define TIM_CCMR1_CC2S_Pos                  (8U)
7751 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
7752 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7753 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
7754 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
7755 
7756 #define TIM_CCMR1_OC2FE_Pos                 (10U)
7757 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
7758 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
7759 #define TIM_CCMR1_OC2PE_Pos                 (11U)
7760 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
7761 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
7762 
7763 #define TIM_CCMR1_OC2M_Pos                  (12U)
7764 #define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
7765 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7766 #define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
7767 #define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
7768 #define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
7769 
7770 #define TIM_CCMR1_OC2CE_Pos                 (15U)
7771 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
7772 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
7773 
7774 /*----------------------------------------------------------------------------*/
7775 
7776 #define TIM_CCMR1_IC1PSC_Pos                (2U)
7777 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
7778 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7779 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
7780 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
7781 
7782 #define TIM_CCMR1_IC1F_Pos                  (4U)
7783 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
7784 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7785 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
7786 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
7787 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
7788 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
7789 
7790 #define TIM_CCMR1_IC2PSC_Pos                (10U)
7791 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
7792 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7793 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
7794 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
7795 
7796 #define TIM_CCMR1_IC2F_Pos                  (12U)
7797 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
7798 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7799 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
7800 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
7801 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
7802 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
7803 
7804 /******************  Bit definition for TIM_CCMR2 register  *******************/
7805 #define TIM_CCMR2_CC3S_Pos                  (0U)
7806 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
7807 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7808 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
7809 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
7810 
7811 #define TIM_CCMR2_OC3FE_Pos                 (2U)
7812 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
7813 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
7814 #define TIM_CCMR2_OC3PE_Pos                 (3U)
7815 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
7816 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
7817 
7818 #define TIM_CCMR2_OC3M_Pos                  (4U)
7819 #define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
7820 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7821 #define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
7822 #define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
7823 #define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
7824 
7825 #define TIM_CCMR2_OC3CE_Pos                 (7U)
7826 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
7827 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
7828 
7829 #define TIM_CCMR2_CC4S_Pos                  (8U)
7830 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
7831 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7832 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
7833 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
7834 
7835 #define TIM_CCMR2_OC4FE_Pos                 (10U)
7836 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
7837 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
7838 #define TIM_CCMR2_OC4PE_Pos                 (11U)
7839 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
7840 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
7841 
7842 #define TIM_CCMR2_OC4M_Pos                  (12U)
7843 #define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
7844 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7845 #define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
7846 #define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
7847 #define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
7848 
7849 #define TIM_CCMR2_OC4CE_Pos                 (15U)
7850 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
7851 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
7852 
7853 /*----------------------------------------------------------------------------*/
7854 
7855 #define TIM_CCMR2_IC3PSC_Pos                (2U)
7856 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
7857 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7858 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
7859 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
7860 
7861 #define TIM_CCMR2_IC3F_Pos                  (4U)
7862 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
7863 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7864 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
7865 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
7866 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
7867 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
7868 
7869 #define TIM_CCMR2_IC4PSC_Pos                (10U)
7870 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
7871 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7872 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
7873 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
7874 
7875 #define TIM_CCMR2_IC4F_Pos                  (12U)
7876 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
7877 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7878 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
7879 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
7880 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
7881 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
7882 
7883 /*******************  Bit definition for TIM_CCER register  *******************/
7884 #define TIM_CCER_CC1E_Pos                   (0U)
7885 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
7886 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
7887 #define TIM_CCER_CC1P_Pos                   (1U)
7888 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
7889 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
7890 #define TIM_CCER_CC1NP_Pos                  (3U)
7891 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
7892 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
7893 #define TIM_CCER_CC2E_Pos                   (4U)
7894 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
7895 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
7896 #define TIM_CCER_CC2P_Pos                   (5U)
7897 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
7898 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
7899 #define TIM_CCER_CC2NP_Pos                  (7U)
7900 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
7901 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
7902 #define TIM_CCER_CC3E_Pos                   (8U)
7903 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
7904 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
7905 #define TIM_CCER_CC3P_Pos                   (9U)
7906 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
7907 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
7908 #define TIM_CCER_CC3NP_Pos                  (11U)
7909 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
7910 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
7911 #define TIM_CCER_CC4E_Pos                   (12U)
7912 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
7913 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
7914 #define TIM_CCER_CC4P_Pos                   (13U)
7915 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
7916 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
7917 #define TIM_CCER_CC4NP_Pos                  (15U)
7918 #define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
7919 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
7920 
7921 /*******************  Bit definition for TIM_CNT register  ********************/
7922 #define TIM_CNT_CNT_Pos                     (0U)
7923 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
7924 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
7925 
7926 /*******************  Bit definition for TIM_PSC register  ********************/
7927 #define TIM_PSC_PSC_Pos                     (0U)
7928 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
7929 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
7930 
7931 /*******************  Bit definition for TIM_ARR register  ********************/
7932 #define TIM_ARR_ARR_Pos                     (0U)
7933 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
7934 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
7935 
7936 /*******************  Bit definition for TIM_CCR1 register  *******************/
7937 #define TIM_CCR1_CCR1_Pos                   (0U)
7938 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
7939 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
7940 
7941 /*******************  Bit definition for TIM_CCR2 register  *******************/
7942 #define TIM_CCR2_CCR2_Pos                   (0U)
7943 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
7944 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
7945 
7946 /*******************  Bit definition for TIM_CCR3 register  *******************/
7947 #define TIM_CCR3_CCR3_Pos                   (0U)
7948 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
7949 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
7950 
7951 /*******************  Bit definition for TIM_CCR4 register  *******************/
7952 #define TIM_CCR4_CCR4_Pos                   (0U)
7953 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
7954 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
7955 
7956 /*******************  Bit definition for TIM_DCR register  ********************/
7957 #define TIM_DCR_DBA_Pos                     (0U)
7958 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
7959 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
7960 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
7961 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
7962 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
7963 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
7964 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
7965 
7966 #define TIM_DCR_DBL_Pos                     (8U)
7967 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
7968 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
7969 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
7970 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
7971 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
7972 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
7973 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
7974 
7975 /*******************  Bit definition for TIM_DMAR register  *******************/
7976 #define TIM_DMAR_DMAB_Pos                   (0U)
7977 #define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
7978 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
7979 
7980 /*******************  Bit definition for TIM_OR register  *********************/
7981 #define TIM_OR_TI1RMP_Pos                   (0U)
7982 #define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
7983 #define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
7984 #define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
7985 #define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
7986 
7987 #define TIM_OR_ETR_RMP_Pos                  (2U)
7988 #define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
7989 #define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
7990 #define TIM_OR_TI1_RMP_RI_Pos               (3U)
7991 #define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
7992 #define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
7993 
7994 /*----------------------------------------------------------------------------*/
7995 #define TIM9_OR_ITR1_RMP_Pos                (2U)
7996 #define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
7997 #define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
7998 
7999 /*----------------------------------------------------------------------------*/
8000 #define TIM2_OR_ITR1_RMP_Pos                (0U)
8001 #define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
8002 #define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
8003 
8004 /*----------------------------------------------------------------------------*/
8005 #define TIM3_OR_ITR2_RMP_Pos                (0U)
8006 #define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
8007 #define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
8008 
8009 /*----------------------------------------------------------------------------*/
8010 
8011 /******************************************************************************/
8012 /*                                                                            */
8013 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
8014 /*                                                                            */
8015 /******************************************************************************/
8016 
8017 /*******************  Bit definition for USART_SR register  *******************/
8018 #define USART_SR_PE_Pos                     (0U)
8019 #define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
8020 #define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
8021 #define USART_SR_FE_Pos                     (1U)
8022 #define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
8023 #define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
8024 #define USART_SR_NE_Pos                     (2U)
8025 #define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
8026 #define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
8027 #define USART_SR_ORE_Pos                    (3U)
8028 #define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
8029 #define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
8030 #define USART_SR_IDLE_Pos                   (4U)
8031 #define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
8032 #define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
8033 #define USART_SR_RXNE_Pos                   (5U)
8034 #define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
8035 #define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
8036 #define USART_SR_TC_Pos                     (6U)
8037 #define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
8038 #define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
8039 #define USART_SR_TXE_Pos                    (7U)
8040 #define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
8041 #define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
8042 #define USART_SR_LBD_Pos                    (8U)
8043 #define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
8044 #define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
8045 #define USART_SR_CTS_Pos                    (9U)
8046 #define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
8047 #define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
8048 
8049 /*******************  Bit definition for USART_DR register  *******************/
8050 #define USART_DR_DR_Pos                     (0U)
8051 #define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
8052 #define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
8053 
8054 /******************  Bit definition for USART_BRR register  *******************/
8055 #define USART_BRR_DIV_Fraction_Pos    (0U)
8056 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
8057 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
8058 #define USART_BRR_DIV_Mantissa_Pos    (4U)
8059 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
8060 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
8061 
8062 /* Legacy aliases */
8063 #define  USART_BRR_DIV_FRACTION_Pos              USART_BRR_DIV_Fraction_Pos
8064 #define  USART_BRR_DIV_FRACTION_Msk              USART_BRR_DIV_Fraction_Msk
8065 #define  USART_BRR_DIV_FRACTION                  USART_BRR_DIV_Fraction
8066 
8067 #define  USART_BRR_DIV_MANTISSA_Pos              USART_BRR_DIV_Mantissa_Pos
8068 #define  USART_BRR_DIV_MANTISSA_Msk              USART_BRR_DIV_Mantissa_Msk
8069 #define  USART_BRR_DIV_MANTISSA                  USART_BRR_DIV_Mantissa
8070 
8071 /******************  Bit definition for USART_CR1 register  *******************/
8072 #define USART_CR1_SBK_Pos                   (0U)
8073 #define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
8074 #define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
8075 #define USART_CR1_RWU_Pos                   (1U)
8076 #define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
8077 #define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
8078 #define USART_CR1_RE_Pos                    (2U)
8079 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
8080 #define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
8081 #define USART_CR1_TE_Pos                    (3U)
8082 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
8083 #define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
8084 #define USART_CR1_IDLEIE_Pos                (4U)
8085 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
8086 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
8087 #define USART_CR1_RXNEIE_Pos                (5U)
8088 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
8089 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
8090 #define USART_CR1_TCIE_Pos                  (6U)
8091 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
8092 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
8093 #define USART_CR1_TXEIE_Pos                 (7U)
8094 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
8095 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
8096 #define USART_CR1_PEIE_Pos                  (8U)
8097 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
8098 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
8099 #define USART_CR1_PS_Pos                    (9U)
8100 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
8101 #define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
8102 #define USART_CR1_PCE_Pos                   (10U)
8103 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
8104 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
8105 #define USART_CR1_WAKE_Pos                  (11U)
8106 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
8107 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
8108 #define USART_CR1_M_Pos                     (12U)
8109 #define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
8110 #define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
8111 #define USART_CR1_UE_Pos                    (13U)
8112 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
8113 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
8114 #define USART_CR1_OVER8_Pos                 (15U)
8115 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
8116 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
8117 
8118 /******************  Bit definition for USART_CR2 register  *******************/
8119 #define USART_CR2_ADD_Pos                   (0U)
8120 #define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
8121 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
8122 #define USART_CR2_LBDL_Pos                  (5U)
8123 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
8124 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
8125 #define USART_CR2_LBDIE_Pos                 (6U)
8126 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
8127 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
8128 #define USART_CR2_LBCL_Pos                  (8U)
8129 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
8130 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
8131 #define USART_CR2_CPHA_Pos                  (9U)
8132 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
8133 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
8134 #define USART_CR2_CPOL_Pos                  (10U)
8135 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
8136 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
8137 #define USART_CR2_CLKEN_Pos                 (11U)
8138 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
8139 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
8140 
8141 #define USART_CR2_STOP_Pos                  (12U)
8142 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
8143 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
8144 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
8145 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
8146 
8147 #define USART_CR2_LINEN_Pos                 (14U)
8148 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
8149 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
8150 
8151 /******************  Bit definition for USART_CR3 register  *******************/
8152 #define USART_CR3_EIE_Pos                   (0U)
8153 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
8154 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
8155 #define USART_CR3_IREN_Pos                  (1U)
8156 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
8157 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
8158 #define USART_CR3_IRLP_Pos                  (2U)
8159 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
8160 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
8161 #define USART_CR3_HDSEL_Pos                 (3U)
8162 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
8163 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
8164 #define USART_CR3_NACK_Pos                  (4U)
8165 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
8166 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
8167 #define USART_CR3_SCEN_Pos                  (5U)
8168 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
8169 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
8170 #define USART_CR3_DMAR_Pos                  (6U)
8171 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
8172 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
8173 #define USART_CR3_DMAT_Pos                  (7U)
8174 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
8175 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
8176 #define USART_CR3_RTSE_Pos                  (8U)
8177 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
8178 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
8179 #define USART_CR3_CTSE_Pos                  (9U)
8180 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
8181 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
8182 #define USART_CR3_CTSIE_Pos                 (10U)
8183 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
8184 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
8185 #define USART_CR3_ONEBIT_Pos                (11U)
8186 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
8187 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
8188 
8189 /******************  Bit definition for USART_GTPR register  ******************/
8190 #define USART_GTPR_PSC_Pos                  (0U)
8191 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
8192 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
8193 #define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
8194 #define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
8195 #define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
8196 #define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
8197 #define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
8198 #define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
8199 #define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
8200 #define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
8201 
8202 #define USART_GTPR_GT_Pos                   (8U)
8203 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
8204 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
8205 
8206 /******************************************************************************/
8207 /*                                                                            */
8208 /*                     Universal Serial Bus (USB)                             */
8209 /*                                                                            */
8210 /******************************************************************************/
8211 
8212 /*!<Endpoint-specific registers */
8213 
8214 #define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
8215 #define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
8216 #define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
8217 #define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
8218 #define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
8219 #define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
8220 #define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
8221 #define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
8222 
8223 /* bit positions */
8224 #define USB_EP_CTR_RX_Pos                     (15U)
8225 #define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
8226 #define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
8227 #define USB_EP_DTOG_RX_Pos                    (14U)
8228 #define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
8229 #define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
8230 #define USB_EPRX_STAT_Pos                     (12U)
8231 #define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
8232 #define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
8233 #define USB_EP_SETUP_Pos                      (11U)
8234 #define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
8235 #define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
8236 #define USB_EP_T_FIELD_Pos                    (9U)
8237 #define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
8238 #define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
8239 #define USB_EP_KIND_Pos                       (8U)
8240 #define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
8241 #define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
8242 #define USB_EP_CTR_TX_Pos                     (7U)
8243 #define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
8244 #define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
8245 #define USB_EP_DTOG_TX_Pos                    (6U)
8246 #define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
8247 #define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
8248 #define USB_EPTX_STAT_Pos                     (4U)
8249 #define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
8250 #define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
8251 #define USB_EPADDR_FIELD_Pos                  (0U)
8252 #define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
8253 #define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
8254 
8255 /* EndPoint REGister MASK (no toggle fields) */
8256 #define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
8257                                                                                /*!< EP_TYPE[1:0] EndPoint TYPE */
8258 #define USB_EP_TYPE_MASK_Pos                  (9U)
8259 #define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
8260 #define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
8261 #define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
8262 #define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
8263 #define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
8264 #define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
8265 #define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
8266 
8267 #define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
8268                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
8269 #define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
8270 #define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
8271 #define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
8272 #define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
8273 #define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
8274 #define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
8275 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
8276                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
8277 #define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
8278 #define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
8279 #define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
8280 #define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
8281 #define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
8282 #define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
8283 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
8284 
8285 /*******************  Bit definition for USB_EP0R register  *******************/
8286 #define USB_EP0R_EA_Pos                       (0U)
8287 #define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
8288 #define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
8289 
8290 #define USB_EP0R_STAT_TX_Pos                  (4U)
8291 #define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
8292 #define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8293 #define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
8294 #define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
8295 
8296 #define USB_EP0R_DTOG_TX_Pos                  (6U)
8297 #define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
8298 #define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8299 #define USB_EP0R_CTR_TX_Pos                   (7U)
8300 #define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
8301 #define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8302 #define USB_EP0R_EP_KIND_Pos                  (8U)
8303 #define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
8304 #define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
8305 
8306 #define USB_EP0R_EP_TYPE_Pos                  (9U)
8307 #define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
8308 #define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8309 #define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
8310 #define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
8311 
8312 #define USB_EP0R_SETUP_Pos                    (11U)
8313 #define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
8314 #define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
8315 
8316 #define USB_EP0R_STAT_RX_Pos                  (12U)
8317 #define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
8318 #define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8319 #define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
8320 #define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
8321 
8322 #define USB_EP0R_DTOG_RX_Pos                  (14U)
8323 #define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
8324 #define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8325 #define USB_EP0R_CTR_RX_Pos                   (15U)
8326 #define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
8327 #define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8328 
8329 /*******************  Bit definition for USB_EP1R register  *******************/
8330 #define USB_EP1R_EA_Pos                       (0U)
8331 #define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
8332 #define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
8333 
8334 #define USB_EP1R_STAT_TX_Pos                  (4U)
8335 #define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
8336 #define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8337 #define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
8338 #define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
8339 
8340 #define USB_EP1R_DTOG_TX_Pos                  (6U)
8341 #define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
8342 #define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8343 #define USB_EP1R_CTR_TX_Pos                   (7U)
8344 #define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
8345 #define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8346 #define USB_EP1R_EP_KIND_Pos                  (8U)
8347 #define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
8348 #define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
8349 
8350 #define USB_EP1R_EP_TYPE_Pos                  (9U)
8351 #define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
8352 #define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8353 #define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
8354 #define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
8355 
8356 #define USB_EP1R_SETUP_Pos                    (11U)
8357 #define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
8358 #define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
8359 
8360 #define USB_EP1R_STAT_RX_Pos                  (12U)
8361 #define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
8362 #define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8363 #define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
8364 #define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
8365 
8366 #define USB_EP1R_DTOG_RX_Pos                  (14U)
8367 #define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
8368 #define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8369 #define USB_EP1R_CTR_RX_Pos                   (15U)
8370 #define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
8371 #define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8372 
8373 /*******************  Bit definition for USB_EP2R register  *******************/
8374 #define USB_EP2R_EA_Pos                       (0U)
8375 #define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
8376 #define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
8377 
8378 #define USB_EP2R_STAT_TX_Pos                  (4U)
8379 #define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
8380 #define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8381 #define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
8382 #define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
8383 
8384 #define USB_EP2R_DTOG_TX_Pos                  (6U)
8385 #define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
8386 #define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8387 #define USB_EP2R_CTR_TX_Pos                   (7U)
8388 #define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
8389 #define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8390 #define USB_EP2R_EP_KIND_Pos                  (8U)
8391 #define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
8392 #define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
8393 
8394 #define USB_EP2R_EP_TYPE_Pos                  (9U)
8395 #define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
8396 #define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8397 #define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
8398 #define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
8399 
8400 #define USB_EP2R_SETUP_Pos                    (11U)
8401 #define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
8402 #define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
8403 
8404 #define USB_EP2R_STAT_RX_Pos                  (12U)
8405 #define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
8406 #define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8407 #define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
8408 #define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
8409 
8410 #define USB_EP2R_DTOG_RX_Pos                  (14U)
8411 #define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
8412 #define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8413 #define USB_EP2R_CTR_RX_Pos                   (15U)
8414 #define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
8415 #define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8416 
8417 /*******************  Bit definition for USB_EP3R register  *******************/
8418 #define USB_EP3R_EA_Pos                       (0U)
8419 #define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
8420 #define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
8421 
8422 #define USB_EP3R_STAT_TX_Pos                  (4U)
8423 #define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
8424 #define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8425 #define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
8426 #define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
8427 
8428 #define USB_EP3R_DTOG_TX_Pos                  (6U)
8429 #define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
8430 #define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8431 #define USB_EP3R_CTR_TX_Pos                   (7U)
8432 #define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
8433 #define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8434 #define USB_EP3R_EP_KIND_Pos                  (8U)
8435 #define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
8436 #define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
8437 
8438 #define USB_EP3R_EP_TYPE_Pos                  (9U)
8439 #define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
8440 #define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8441 #define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
8442 #define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
8443 
8444 #define USB_EP3R_SETUP_Pos                    (11U)
8445 #define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
8446 #define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
8447 
8448 #define USB_EP3R_STAT_RX_Pos                  (12U)
8449 #define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
8450 #define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8451 #define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
8452 #define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
8453 
8454 #define USB_EP3R_DTOG_RX_Pos                  (14U)
8455 #define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
8456 #define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8457 #define USB_EP3R_CTR_RX_Pos                   (15U)
8458 #define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
8459 #define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8460 
8461 /*******************  Bit definition for USB_EP4R register  *******************/
8462 #define USB_EP4R_EA_Pos                       (0U)
8463 #define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
8464 #define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
8465 
8466 #define USB_EP4R_STAT_TX_Pos                  (4U)
8467 #define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
8468 #define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8469 #define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
8470 #define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
8471 
8472 #define USB_EP4R_DTOG_TX_Pos                  (6U)
8473 #define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
8474 #define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8475 #define USB_EP4R_CTR_TX_Pos                   (7U)
8476 #define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
8477 #define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8478 #define USB_EP4R_EP_KIND_Pos                  (8U)
8479 #define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
8480 #define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
8481 
8482 #define USB_EP4R_EP_TYPE_Pos                  (9U)
8483 #define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
8484 #define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8485 #define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
8486 #define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
8487 
8488 #define USB_EP4R_SETUP_Pos                    (11U)
8489 #define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
8490 #define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
8491 
8492 #define USB_EP4R_STAT_RX_Pos                  (12U)
8493 #define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
8494 #define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8495 #define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
8496 #define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
8497 
8498 #define USB_EP4R_DTOG_RX_Pos                  (14U)
8499 #define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
8500 #define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8501 #define USB_EP4R_CTR_RX_Pos                   (15U)
8502 #define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
8503 #define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8504 
8505 /*******************  Bit definition for USB_EP5R register  *******************/
8506 #define USB_EP5R_EA_Pos                       (0U)
8507 #define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
8508 #define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
8509 
8510 #define USB_EP5R_STAT_TX_Pos                  (4U)
8511 #define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
8512 #define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8513 #define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
8514 #define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
8515 
8516 #define USB_EP5R_DTOG_TX_Pos                  (6U)
8517 #define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
8518 #define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8519 #define USB_EP5R_CTR_TX_Pos                   (7U)
8520 #define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
8521 #define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8522 #define USB_EP5R_EP_KIND_Pos                  (8U)
8523 #define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
8524 #define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
8525 
8526 #define USB_EP5R_EP_TYPE_Pos                  (9U)
8527 #define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
8528 #define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8529 #define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
8530 #define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
8531 
8532 #define USB_EP5R_SETUP_Pos                    (11U)
8533 #define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
8534 #define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
8535 
8536 #define USB_EP5R_STAT_RX_Pos                  (12U)
8537 #define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
8538 #define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8539 #define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
8540 #define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
8541 
8542 #define USB_EP5R_DTOG_RX_Pos                  (14U)
8543 #define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
8544 #define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8545 #define USB_EP5R_CTR_RX_Pos                   (15U)
8546 #define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
8547 #define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8548 
8549 /*******************  Bit definition for USB_EP6R register  *******************/
8550 #define USB_EP6R_EA_Pos                       (0U)
8551 #define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
8552 #define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
8553 
8554 #define USB_EP6R_STAT_TX_Pos                  (4U)
8555 #define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
8556 #define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8557 #define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
8558 #define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
8559 
8560 #define USB_EP6R_DTOG_TX_Pos                  (6U)
8561 #define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
8562 #define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8563 #define USB_EP6R_CTR_TX_Pos                   (7U)
8564 #define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
8565 #define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8566 #define USB_EP6R_EP_KIND_Pos                  (8U)
8567 #define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
8568 #define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
8569 
8570 #define USB_EP6R_EP_TYPE_Pos                  (9U)
8571 #define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
8572 #define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8573 #define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
8574 #define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
8575 
8576 #define USB_EP6R_SETUP_Pos                    (11U)
8577 #define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
8578 #define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
8579 
8580 #define USB_EP6R_STAT_RX_Pos                  (12U)
8581 #define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
8582 #define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8583 #define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
8584 #define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
8585 
8586 #define USB_EP6R_DTOG_RX_Pos                  (14U)
8587 #define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
8588 #define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8589 #define USB_EP6R_CTR_RX_Pos                   (15U)
8590 #define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
8591 #define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8592 
8593 /*******************  Bit definition for USB_EP7R register  *******************/
8594 #define USB_EP7R_EA_Pos                       (0U)
8595 #define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
8596 #define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
8597 
8598 #define USB_EP7R_STAT_TX_Pos                  (4U)
8599 #define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
8600 #define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
8601 #define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
8602 #define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
8603 
8604 #define USB_EP7R_DTOG_TX_Pos                  (6U)
8605 #define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
8606 #define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
8607 #define USB_EP7R_CTR_TX_Pos                   (7U)
8608 #define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
8609 #define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
8610 #define USB_EP7R_EP_KIND_Pos                  (8U)
8611 #define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
8612 #define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
8613 
8614 #define USB_EP7R_EP_TYPE_Pos                  (9U)
8615 #define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
8616 #define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
8617 #define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
8618 #define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
8619 
8620 #define USB_EP7R_SETUP_Pos                    (11U)
8621 #define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
8622 #define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
8623 
8624 #define USB_EP7R_STAT_RX_Pos                  (12U)
8625 #define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
8626 #define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
8627 #define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
8628 #define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
8629 
8630 #define USB_EP7R_DTOG_RX_Pos                  (14U)
8631 #define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
8632 #define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
8633 #define USB_EP7R_CTR_RX_Pos                   (15U)
8634 #define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
8635 #define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
8636 
8637 /*!<Common registers */
8638 
8639 #define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
8640 #define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
8641 #define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
8642 #define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
8643 #define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
8644 
8645 
8646 
8647 /*******************  Bit definition for USB_CNTR register  *******************/
8648 #define USB_CNTR_FRES_Pos                     (0U)
8649 #define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
8650 #define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
8651 #define USB_CNTR_PDWN_Pos                     (1U)
8652 #define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
8653 #define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
8654 #define USB_CNTR_LPMODE_Pos                   (2U)
8655 #define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
8656 #define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
8657 #define USB_CNTR_FSUSP_Pos                    (3U)
8658 #define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
8659 #define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
8660 #define USB_CNTR_RESUME_Pos                   (4U)
8661 #define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
8662 #define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
8663 #define USB_CNTR_ESOFM_Pos                    (8U)
8664 #define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
8665 #define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
8666 #define USB_CNTR_SOFM_Pos                     (9U)
8667 #define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
8668 #define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
8669 #define USB_CNTR_RESETM_Pos                   (10U)
8670 #define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
8671 #define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
8672 #define USB_CNTR_SUSPM_Pos                    (11U)
8673 #define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
8674 #define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
8675 #define USB_CNTR_WKUPM_Pos                    (12U)
8676 #define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
8677 #define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
8678 #define USB_CNTR_ERRM_Pos                     (13U)
8679 #define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
8680 #define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
8681 #define USB_CNTR_PMAOVRM_Pos                  (14U)
8682 #define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
8683 #define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
8684 #define USB_CNTR_CTRM_Pos                     (15U)
8685 #define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
8686 #define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
8687 
8688 /*******************  Bit definition for USB_ISTR register  *******************/
8689 #define USB_ISTR_EP_ID_Pos                    (0U)
8690 #define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
8691 #define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
8692 #define USB_ISTR_DIR_Pos                      (4U)
8693 #define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
8694 #define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
8695 #define USB_ISTR_ESOF_Pos                     (8U)
8696 #define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
8697 #define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
8698 #define USB_ISTR_SOF_Pos                      (9U)
8699 #define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
8700 #define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
8701 #define USB_ISTR_RESET_Pos                    (10U)
8702 #define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
8703 #define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
8704 #define USB_ISTR_SUSP_Pos                     (11U)
8705 #define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
8706 #define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
8707 #define USB_ISTR_WKUP_Pos                     (12U)
8708 #define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
8709 #define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
8710 #define USB_ISTR_ERR_Pos                      (13U)
8711 #define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
8712 #define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
8713 #define USB_ISTR_PMAOVR_Pos                   (14U)
8714 #define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
8715 #define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
8716 #define USB_ISTR_CTR_Pos                      (15U)
8717 #define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
8718 #define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
8719 
8720 #define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
8721 #define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
8722 #define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
8723 #define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
8724 #define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
8725 #define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
8726 #define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
8727 #define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
8728 
8729 
8730 /*******************  Bit definition for USB_FNR register  ********************/
8731 #define USB_FNR_FN_Pos                        (0U)
8732 #define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
8733 #define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
8734 #define USB_FNR_LSOF_Pos                      (11U)
8735 #define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
8736 #define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
8737 #define USB_FNR_LCK_Pos                       (13U)
8738 #define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
8739 #define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
8740 #define USB_FNR_RXDM_Pos                      (14U)
8741 #define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
8742 #define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
8743 #define USB_FNR_RXDP_Pos                      (15U)
8744 #define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
8745 #define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
8746 
8747 /******************  Bit definition for USB_DADDR register  *******************/
8748 #define USB_DADDR_ADD_Pos                     (0U)
8749 #define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
8750 #define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
8751 #define USB_DADDR_ADD0_Pos                    (0U)
8752 #define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
8753 #define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
8754 #define USB_DADDR_ADD1_Pos                    (1U)
8755 #define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
8756 #define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
8757 #define USB_DADDR_ADD2_Pos                    (2U)
8758 #define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
8759 #define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
8760 #define USB_DADDR_ADD3_Pos                    (3U)
8761 #define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
8762 #define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
8763 #define USB_DADDR_ADD4_Pos                    (4U)
8764 #define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
8765 #define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
8766 #define USB_DADDR_ADD5_Pos                    (5U)
8767 #define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
8768 #define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
8769 #define USB_DADDR_ADD6_Pos                    (6U)
8770 #define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
8771 #define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
8772 
8773 #define USB_DADDR_EF_Pos                      (7U)
8774 #define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
8775 #define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
8776 
8777 /******************  Bit definition for USB_BTABLE register  ******************/
8778 #define USB_BTABLE_BTABLE_Pos                 (3U)
8779 #define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
8780 #define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
8781 
8782 /*!< Buffer descriptor table */
8783 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
8784 #define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)
8785 #define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
8786 #define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
8787 
8788 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
8789 #define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)
8790 #define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
8791 #define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
8792 
8793 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
8794 #define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)
8795 #define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
8796 #define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
8797 
8798 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
8799 #define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)
8800 #define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
8801 #define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
8802 
8803 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
8804 #define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)
8805 #define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
8806 #define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
8807 
8808 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
8809 #define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)
8810 #define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
8811 #define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
8812 
8813 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
8814 #define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)
8815 #define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
8816 #define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
8817 
8818 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
8819 #define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)
8820 #define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
8821 #define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
8822 
8823 /*----------------------------------------------------------------------------*/
8824 
8825 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
8826 #define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)
8827 #define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
8828 #define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
8829 
8830 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
8831 #define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)
8832 #define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
8833 #define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
8834 
8835 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
8836 #define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)
8837 #define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
8838 #define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
8839 
8840 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
8841 #define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)
8842 #define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
8843 #define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
8844 
8845 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
8846 #define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)
8847 #define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
8848 #define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
8849 
8850 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
8851 #define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)
8852 #define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
8853 #define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
8854 
8855 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
8856 #define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)
8857 #define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
8858 #define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
8859 
8860 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
8861 #define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)
8862 #define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
8863 #define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
8864 
8865 /*----------------------------------------------------------------------------*/
8866 
8867 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
8868 #define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
8869 
8870 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
8871 #define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
8872 
8873 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
8874 #define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
8875 
8876 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
8877 #define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
8878 
8879 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
8880 #define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
8881 
8882 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
8883 #define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
8884 
8885 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
8886 #define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
8887 
8888 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
8889 #define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
8890 
8891 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
8892 #define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
8893 
8894 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
8895 #define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
8896 
8897 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
8898 #define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
8899 
8900 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
8901 #define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
8902 
8903 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
8904 #define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
8905 
8906 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
8907 #define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
8908 
8909 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
8910 #define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
8911 
8912 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
8913 #define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
8914 
8915 /*----------------------------------------------------------------------------*/
8916 
8917 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
8918 #define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)
8919 #define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
8920 #define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
8921 
8922 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
8923 #define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)
8924 #define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
8925 #define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
8926 
8927 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
8928 #define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)
8929 #define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
8930 #define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
8931 
8932 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
8933 #define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)
8934 #define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
8935 #define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
8936 
8937 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
8938 #define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)
8939 #define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
8940 #define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
8941 
8942 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
8943 #define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)
8944 #define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
8945 #define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
8946 
8947 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
8948 #define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)
8949 #define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
8950 #define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
8951 
8952 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
8953 #define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)
8954 #define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
8955 #define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
8956 
8957 /*----------------------------------------------------------------------------*/
8958 
8959 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
8960 #define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)
8961 #define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
8962 #define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
8963 
8964 #define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)
8965 #define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
8966 #define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
8967 #define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
8968 #define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
8969 #define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
8970 #define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
8971 #define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
8972 
8973 #define USB_COUNT0_RX_BLSIZE_Pos              (15U)
8974 #define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
8975 #define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
8976 
8977 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
8978 #define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)
8979 #define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
8980 #define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
8981 
8982 #define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)
8983 #define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
8984 #define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
8985 #define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
8986 #define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
8987 #define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
8988 #define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
8989 #define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
8990 
8991 #define USB_COUNT1_RX_BLSIZE_Pos              (15U)
8992 #define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
8993 #define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
8994 
8995 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
8996 #define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)
8997 #define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
8998 #define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
8999 
9000 #define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)
9001 #define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9002 #define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9003 #define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9004 #define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9005 #define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9006 #define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9007 #define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9008 
9009 #define USB_COUNT2_RX_BLSIZE_Pos              (15U)
9010 #define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
9011 #define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
9012 
9013 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
9014 #define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)
9015 #define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
9016 #define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
9017 
9018 #define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)
9019 #define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9020 #define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9021 #define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9022 #define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9023 #define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9024 #define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9025 #define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9026 
9027 #define USB_COUNT3_RX_BLSIZE_Pos              (15U)
9028 #define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
9029 #define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
9030 
9031 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
9032 #define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)
9033 #define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
9034 #define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
9035 
9036 #define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)
9037 #define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9038 #define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9039 #define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9040 #define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9041 #define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9042 #define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9043 #define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9044 
9045 #define USB_COUNT4_RX_BLSIZE_Pos              (15U)
9046 #define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
9047 #define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
9048 
9049 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
9050 #define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)
9051 #define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
9052 #define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
9053 
9054 #define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)
9055 #define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9056 #define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9057 #define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9058 #define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9059 #define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9060 #define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9061 #define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9062 
9063 #define USB_COUNT5_RX_BLSIZE_Pos              (15U)
9064 #define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
9065 #define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
9066 
9067 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
9068 #define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)
9069 #define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
9070 #define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
9071 
9072 #define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)
9073 #define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9074 #define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9075 #define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9076 #define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9077 #define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9078 #define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9079 #define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9080 
9081 #define USB_COUNT6_RX_BLSIZE_Pos              (15U)
9082 #define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
9083 #define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
9084 
9085 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
9086 #define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)
9087 #define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
9088 #define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
9089 
9090 #define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)
9091 #define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
9092 #define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
9093 #define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
9094 #define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
9095 #define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
9096 #define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
9097 #define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
9098 
9099 #define USB_COUNT7_RX_BLSIZE_Pos              (15U)
9100 #define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
9101 #define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
9102 
9103 /*----------------------------------------------------------------------------*/
9104 
9105 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
9106 #define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9107 
9108 #define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9109 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9110 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9111 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9112 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9113 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9114 
9115 #define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9116 
9117 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
9118 #define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9119 
9120 #define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9121 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
9122 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9123 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9124 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9125 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9126 
9127 #define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9128 
9129 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
9130 #define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9131 
9132 #define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9133 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9134 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9135 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9136 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9137 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9138 
9139 #define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9140 
9141 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
9142 #define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9143 
9144 #define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9145 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9146 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9147 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9148 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9149 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9150 
9151 #define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9152 
9153 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
9154 #define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9155 
9156 #define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9157 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9158 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9159 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9160 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9161 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9162 
9163 #define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9164 
9165 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
9166 #define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9167 
9168 #define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9169 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9170 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9171 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9172 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9173 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9174 
9175 #define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9176 
9177 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
9178 #define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9179 
9180 #define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9181 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9182 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9183 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9184 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9185 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9186 
9187 #define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9188 
9189 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
9190 #define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9191 
9192 #define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9193 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9194 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9195 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9196 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9197 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9198 
9199 #define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9200 
9201 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
9202 #define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9203 
9204 #define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9205 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9206 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9207 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9208 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9209 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9210 
9211 #define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9212 
9213 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
9214 #define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9215 
9216 #define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9217 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9218 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9219 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9220 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9221 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9222 
9223 #define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9224 
9225 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
9226 #define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9227 
9228 #define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9229 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9230 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9231 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9232 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9233 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9234 
9235 #define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9236 
9237 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
9238 #define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9239 
9240 #define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9241 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9242 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9243 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9244 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9245 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9246 
9247 #define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9248 
9249 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
9250 #define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9251 
9252 #define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9253 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9254 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9255 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9256 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9257 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9258 
9259 #define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9260 
9261 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
9262 #define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9263 
9264 #define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9265 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9266 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9267 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9268 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9269 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9270 
9271 #define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9272 
9273 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
9274 #define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
9275 
9276 #define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
9277 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
9278 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
9279 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
9280 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
9281 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
9282 
9283 #define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
9284 
9285 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
9286 #define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
9287 
9288 #define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
9289 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
9290 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
9291 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
9292 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
9293 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
9294 
9295 #define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
9296 
9297 /******************************************************************************/
9298 /*                                                                            */
9299 /*                         Window WATCHDOG (WWDG)                             */
9300 /*                                                                            */
9301 /******************************************************************************/
9302 
9303 /*******************  Bit definition for WWDG_CR register  ********************/
9304 #define WWDG_CR_T_Pos                       (0U)
9305 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
9306 #define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
9307 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
9308 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
9309 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
9310 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
9311 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
9312 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
9313 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
9314 
9315 /* Legacy defines */
9316 #define  WWDG_CR_T0 WWDG_CR_T_0
9317 #define  WWDG_CR_T1 WWDG_CR_T_1
9318 #define  WWDG_CR_T2 WWDG_CR_T_2
9319 #define  WWDG_CR_T3 WWDG_CR_T_3
9320 #define  WWDG_CR_T4 WWDG_CR_T_4
9321 #define  WWDG_CR_T5 WWDG_CR_T_5
9322 #define  WWDG_CR_T6 WWDG_CR_T_6
9323 
9324 #define WWDG_CR_WDGA_Pos                    (7U)
9325 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
9326 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
9327 
9328 /*******************  Bit definition for WWDG_CFR register  *******************/
9329 #define WWDG_CFR_W_Pos                      (0U)
9330 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
9331 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
9332 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
9333 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
9334 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
9335 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
9336 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
9337 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
9338 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
9339 
9340 /* Legacy defines */
9341 #define  WWDG_CFR_W0 WWDG_CFR_W_0
9342 #define  WWDG_CFR_W1 WWDG_CFR_W_1
9343 #define  WWDG_CFR_W2 WWDG_CFR_W_2
9344 #define  WWDG_CFR_W3 WWDG_CFR_W_3
9345 #define  WWDG_CFR_W4 WWDG_CFR_W_4
9346 #define  WWDG_CFR_W5 WWDG_CFR_W_5
9347 #define  WWDG_CFR_W6 WWDG_CFR_W_6
9348 
9349 #define WWDG_CFR_WDGTB_Pos                  (7U)
9350 #define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
9351 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
9352 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
9353 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
9354 
9355 /* Legacy defines */
9356 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
9357 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
9358 
9359 #define WWDG_CFR_EWI_Pos                    (9U)
9360 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
9361 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
9362 
9363 /*******************  Bit definition for WWDG_SR register  ********************/
9364 #define WWDG_SR_EWIF_Pos                    (0U)
9365 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
9366 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
9367 
9368  /**
9369   * @}
9370   */
9371 /** @addtogroup Exported_macro
9372   * @{
9373   */
9374 
9375 /****************************** ADC Instances *********************************/
9376 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9377 
9378 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
9379 
9380 /****************************** AES Instances *********************************/
9381 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
9382 
9383 /******************************** COMP Instances ******************************/
9384 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
9385                                         ((INSTANCE) == COMP2))
9386 
9387 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
9388 
9389 /****************************** CRC Instances *********************************/
9390 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9391 
9392 /****************************** DAC Instances *********************************/
9393 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
9394 
9395 /****************************** DMA Instances *********************************/
9396 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9397                                        ((INSTANCE) == DMA1_Channel2) || \
9398                                        ((INSTANCE) == DMA1_Channel3) || \
9399                                        ((INSTANCE) == DMA1_Channel4) || \
9400                                        ((INSTANCE) == DMA1_Channel5) || \
9401                                        ((INSTANCE) == DMA1_Channel6) || \
9402                                        ((INSTANCE) == DMA1_Channel7) || \
9403                                        ((INSTANCE) == DMA2_Channel1) || \
9404                                        ((INSTANCE) == DMA2_Channel2) || \
9405                                        ((INSTANCE) == DMA2_Channel3) || \
9406                                        ((INSTANCE) == DMA2_Channel4) || \
9407                                        ((INSTANCE) == DMA2_Channel5))
9408 
9409 /******************************* GPIO Instances *******************************/
9410 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9411                                         ((INSTANCE) == GPIOB) || \
9412                                         ((INSTANCE) == GPIOC) || \
9413                                         ((INSTANCE) == GPIOD) || \
9414                                         ((INSTANCE) == GPIOE) || \
9415                                         ((INSTANCE) == GPIOF) || \
9416                                         ((INSTANCE) == GPIOG) || \
9417                                         ((INSTANCE) == GPIOH))
9418 
9419 /**************************** GPIO Alternate Function Instances ***************/
9420 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9421 
9422 /**************************** GPIO Lock Instances *****************************/
9423 /* On L1, all GPIO Bank support the Lock mechanism */
9424 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9425 
9426 /******************************** I2C Instances *******************************/
9427 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9428                                        ((INSTANCE) == I2C2))
9429 
9430 /****************************** SMBUS Instances *******************************/
9431 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
9432 
9433 /******************************** I2S Instances *******************************/
9434 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
9435                                        ((INSTANCE) == SPI3))
9436 /****************************** IWDG Instances ********************************/
9437 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
9438 
9439 /****************************** OPAMP Instances *******************************/
9440 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
9441                                          ((INSTANCE) == OPAMP2) || \
9442                                          ((INSTANCE) == OPAMP3))
9443 
9444 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON)
9445 
9446 /****************************** RTC Instances *********************************/
9447 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
9448 
9449 /****************************** SDIO Instances *********************************/
9450 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
9451 
9452 /******************************** SPI Instances *******************************/
9453 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9454                                        ((INSTANCE) == SPI2) || \
9455                                        ((INSTANCE) == SPI3))
9456 
9457 /****************************** TIM Instances *********************************/
9458 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
9459                                    ((INSTANCE) == TIM3)    || \
9460                                    ((INSTANCE) == TIM4)    || \
9461                                    ((INSTANCE) == TIM5)    || \
9462                                    ((INSTANCE) == TIM6)    || \
9463                                    ((INSTANCE) == TIM7)    || \
9464                                    ((INSTANCE) == TIM9)    || \
9465                                    ((INSTANCE) == TIM10)   || \
9466                                    ((INSTANCE) == TIM11))
9467 
9468 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9469                                        ((INSTANCE) == TIM3)  || \
9470                                        ((INSTANCE) == TIM4)  || \
9471                                        ((INSTANCE) == TIM5)  || \
9472                                        ((INSTANCE) == TIM9)  || \
9473                                        ((INSTANCE) == TIM10) || \
9474                                        ((INSTANCE) == TIM11))
9475 
9476 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9477                                        ((INSTANCE) == TIM3)  || \
9478                                        ((INSTANCE) == TIM4)  || \
9479                                        ((INSTANCE) == TIM5)  || \
9480                                        ((INSTANCE) == TIM9))
9481 
9482 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9483                                        ((INSTANCE) == TIM3)  || \
9484                                        ((INSTANCE) == TIM4)  || \
9485                                        ((INSTANCE) == TIM5))
9486 
9487 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9488                                        ((INSTANCE) == TIM3)  || \
9489                                        ((INSTANCE) == TIM4)  || \
9490                                        ((INSTANCE) == TIM5))
9491 
9492 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9493                                                         ((INSTANCE) == TIM3)  || \
9494                                                         ((INSTANCE) == TIM4)  || \
9495                                                         ((INSTANCE) == TIM5)  || \
9496                                                         ((INSTANCE) == TIM9))
9497 
9498 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9499                                                         ((INSTANCE) == TIM3)  || \
9500                                                         ((INSTANCE) == TIM4)  || \
9501                                                         ((INSTANCE) == TIM5)  || \
9502                                                         ((INSTANCE) == TIM9)  || \
9503                                                         ((INSTANCE) == TIM10) || \
9504                                                         ((INSTANCE) == TIM11))
9505 
9506 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9507                                                    ((INSTANCE) == TIM3)  || \
9508                                                    ((INSTANCE) == TIM4)  || \
9509                                                    ((INSTANCE) == TIM5)  || \
9510                                                    ((INSTANCE) == TIM9))
9511 
9512 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9513                                                     ((INSTANCE) == TIM3)  || \
9514                                                     ((INSTANCE) == TIM4)  || \
9515                                                     ((INSTANCE) == TIM5)  || \
9516                                                     ((INSTANCE) == TIM9))
9517 
9518 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9519                                                 ((INSTANCE) == TIM3)  || \
9520                                                 ((INSTANCE) == TIM4))
9521 
9522 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9523                                        ((INSTANCE) == TIM3)  || \
9524                                        ((INSTANCE) == TIM4)  || \
9525                                        ((INSTANCE) == TIM5))
9526 
9527 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9528                                        ((INSTANCE) == TIM3)  || \
9529                                        ((INSTANCE) == TIM4)  || \
9530                                        ((INSTANCE) == TIM5)  || \
9531                                        ((INSTANCE) == TIM9))
9532 
9533 
9534 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9535                                           ((INSTANCE) == TIM3)  || \
9536                                           ((INSTANCE) == TIM4)  || \
9537                                           ((INSTANCE) == TIM5)  || \
9538                                           ((INSTANCE) == TIM6)  || \
9539                                           ((INSTANCE) == TIM7)  || \
9540                                           ((INSTANCE) == TIM9))
9541 
9542 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9543                                          ((INSTANCE) == TIM3)  || \
9544                                          ((INSTANCE) == TIM4)  || \
9545                                          ((INSTANCE) == TIM9))
9546 
9547 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
9548 
9549 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9550                                             ((INSTANCE) == TIM3)  || \
9551                                             ((INSTANCE) == TIM4)  || \
9552                                             ((INSTANCE) == TIM5))
9553 
9554 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9555     ((((INSTANCE) == TIM2) &&                   \
9556      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9557       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9558       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9559       ((CHANNEL) == TIM_CHANNEL_4)))           \
9560     ||                                         \
9561     (((INSTANCE) == TIM3) &&                   \
9562      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9563       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9564       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9565       ((CHANNEL) == TIM_CHANNEL_4)))           \
9566     ||                                         \
9567     (((INSTANCE) == TIM4) &&                   \
9568      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9569       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9570       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9571       ((CHANNEL) == TIM_CHANNEL_4)))           \
9572     ||                                         \
9573     (((INSTANCE) == TIM5) &&                   \
9574      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9575       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9576       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9577       ((CHANNEL) == TIM_CHANNEL_4)))           \
9578     ||                                         \
9579     (((INSTANCE) == TIM9) &&                  \
9580      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9581       ((CHANNEL) == TIM_CHANNEL_2)))           \
9582     ||                                         \
9583     (((INSTANCE) == TIM10) &&                  \
9584      (((CHANNEL) == TIM_CHANNEL_1)))           \
9585     ||                                         \
9586     (((INSTANCE) == TIM11) &&                  \
9587      (((CHANNEL) == TIM_CHANNEL_1))))
9588 
9589 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9590                                                   ((INSTANCE) == TIM3)  || \
9591                                                   ((INSTANCE) == TIM4)  || \
9592                                                   ((INSTANCE) == TIM5)  || \
9593                                                   ((INSTANCE) == TIM9)  || \
9594                                                   ((INSTANCE) == TIM10) || \
9595                                                   ((INSTANCE) == TIM11))
9596 
9597 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
9598                                        ((INSTANCE) == TIM3)    || \
9599                                        ((INSTANCE) == TIM4)    || \
9600                                        ((INSTANCE) == TIM5)    || \
9601                                        ((INSTANCE) == TIM6)    || \
9602                                        ((INSTANCE) == TIM7))
9603 
9604 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9605                                           ((INSTANCE) == TIM3)  || \
9606                                           ((INSTANCE) == TIM4)  || \
9607                                           ((INSTANCE) == TIM5))
9608 
9609 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
9610                                                        ((INSTANCE) == TIM3)    || \
9611                                                        ((INSTANCE) == TIM4)    || \
9612                                                        ((INSTANCE) == TIM5)    || \
9613                                                        ((INSTANCE) == TIM9))
9614 
9615 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
9616                                                      ((INSTANCE) == TIM3)  || \
9617                                                      ((INSTANCE) == TIM4)  || \
9618                                                      ((INSTANCE) == TIM5)  || \
9619                                                      ((INSTANCE) == TIM9))
9620 
9621 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
9622                                          ((INSTANCE) == TIM3)    || \
9623                                          ((INSTANCE) == TIM9)    || \
9624                                          ((INSTANCE) == TIM10)   || \
9625                                          ((INSTANCE) == TIM11))
9626 
9627 /******************** USART Instances : Synchronous mode **********************/
9628 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9629                                      ((INSTANCE) == USART2) || \
9630                                      ((INSTANCE) == USART3))
9631 
9632 /******************** UART Instances : Asynchronous mode **********************/
9633 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9634                                     ((INSTANCE) == USART2) || \
9635                                     ((INSTANCE) == USART3) || \
9636                                     ((INSTANCE) == UART4)  || \
9637                                     ((INSTANCE) == UART5))
9638 
9639 /******************** UART Instances : Half-Duplex mode **********************/
9640 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9641                                                  ((INSTANCE) == USART2) || \
9642                                                  ((INSTANCE) == USART3) || \
9643                                                  ((INSTANCE) == UART4)  || \
9644                                                  ((INSTANCE) == UART5))
9645 
9646 /******************** UART Instances : LIN mode **********************/
9647 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9648                                           ((INSTANCE) == USART2) || \
9649                                           ((INSTANCE) == USART3) || \
9650                                           ((INSTANCE) == UART4)  || \
9651                                           ((INSTANCE) == UART5))
9652 
9653 /****************** UART Instances : Hardware Flow control ********************/
9654 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9655                                            ((INSTANCE) == USART2) || \
9656                                            ((INSTANCE) == USART3))
9657 
9658 /********************* UART Instances : Smard card mode ***********************/
9659 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9660                                          ((INSTANCE) == USART2) || \
9661                                          ((INSTANCE) == USART3))
9662 
9663 /*********************** UART Instances : IRDA mode ***************************/
9664 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9665                                     ((INSTANCE) == USART2) || \
9666                                     ((INSTANCE) == USART3) || \
9667                                     ((INSTANCE) == UART4)  || \
9668                                     ((INSTANCE) == UART5))
9669 
9670 /***************** UART Instances : Multi-Processor mode **********************/
9671 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9672                                                      ((INSTANCE) == USART2) || \
9673                                                      ((INSTANCE) == USART3) || \
9674                                                      ((INSTANCE) == UART4)  || \
9675                                                      ((INSTANCE) == UART5))
9676 
9677 /****************************** WWDG Instances ********************************/
9678 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
9679 
9680 
9681 /****************************** LCD Instances ********************************/
9682 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
9683 
9684 /****************************** USB Instances ********************************/
9685 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
9686 #define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
9687 
9688 /**
9689   * @}
9690   */
9691 
9692 /******************************************************************************/
9693 /*  For a painless codes migration between the STM32L1xx device product       */
9694 /*  lines, the aliases defined below are put in place to overcome the         */
9695 /*  differences in the interrupt handlers and IRQn definitions.               */
9696 /*  No need to update developed interrupt code when moving across             */
9697 /*  product lines within the same STM32L1 Family                              */
9698 /******************************************************************************/
9699 
9700 /* Aliases for __IRQn */
9701 
9702 /* Aliases for __IRQHandler */
9703 
9704 /**
9705   * @}
9706   */
9707 
9708 /**
9709   * @}
9710   */
9711 
9712 #ifdef __cplusplus
9713 }
9714 #endif /* __cplusplus */
9715 
9716 #endif /* __STM32L162xD_H */
9717 
9718 
9719 
9720