Home
last modified time | relevance | path

Searched refs:APBSMENR1 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h2010 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
2012 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
2014 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
2016 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
2017 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
2019 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
2021 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
2022 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
2023 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
2025 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
[all …]
Dstm32g0xx_ll_bus.h814 SET_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
816 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
886 CLEAR_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h1315 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
1317 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
1318 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
1319 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
1321 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
1324 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
1327 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
1329 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
1330 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
1332 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
[all …]
Dstm32c0xx_ll_bus.h500 SET_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
502 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
534 CLEAR_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h1838 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
1840 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
1842 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
1844 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
1846 #define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SM…
1849 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LCDSMEN)
1852 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSME…
1854 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
1857 #define __HAL_RCC_LPUART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART3SM…
1861 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
[all …]
Dstm32u0xx_ll_bus.h795 SET_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
797 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_EnableClockStopSleep()
863 CLEAR_BIT(RCC->APBSMENR1, Periphs); in LL_APB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h359 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32c031xx.h361 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32c071xx.h384 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h361 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g050xx.h366 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g070xx.h365 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g031xx.h386 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g041xx.h387 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g051xx.h426 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g061xx.h427 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g071xx.h443 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g081xx.h444 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g0b0xx.h373 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g0c1xx.h523 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
Dstm32g0b1xx.h522 …__IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, … member
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h490 …__IO uint32_t APBSMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode register, … member
Dstm32u083xx.h550 …__IO uint32_t APBSMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode register, … member
Dstm32u073xx.h516 …__IO uint32_t APBSMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode register, … member