Home
last modified time | relevance | path

Searched refs:AHBENR (Results 1 – 25 of 131) sorted by relevance

123456

/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
696 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
703 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
705 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
710 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
[all …]
Dstm32f3xx_hal_rcc_ex.h1876 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1878 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1882 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
1889 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1896 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1898 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1903 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1905 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1912 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
[all …]
Dstm32f3xx_ll_bus.h288 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
290 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
339 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
387 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h622 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
624 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
629 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
636 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
638 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
643 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
645 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
650 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
[all …]
Dstm32f0xx_hal_rcc_ex.h941 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
943 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
947 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
955 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
957 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
961 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
972 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
974 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
978 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
989 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
[all …]
Dstm32f0xx_ll_bus.h228 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
230 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
267 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
303 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc_ex.h160 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
162 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
165 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
175 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
177 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
182 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
184 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
188 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
189 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
201 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
[all …]
Dstm32l1xx_hal_rcc.h643 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
645 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
650 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
657 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
659 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
664 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
666 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
671 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
673 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
[all …]
Dstm32l1xx_ll_bus.h217 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
219 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
260 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
300 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h629 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
635 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
642 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
644 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
648 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
654 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
656 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
661 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
667 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
[all …]
Dstm32f1xx_hal_rcc.h323 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
325 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
331 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
339 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
341 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
347 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
349 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
353 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
354 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
[all …]
Dstm32f1xx_ll_bus.h270 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
272 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
307 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
341 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h702 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
704 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
712 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
719 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
721 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
727 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
729 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
735 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \
737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \
[all …]
Dstm32u0xx_ll_bus.h214 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
216 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
244 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
271 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h678 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
680 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
686 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
688 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
694 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
696 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
701 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
702 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
703 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
798 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
[all …]
Dstm32l0xx_hal_rcc_ex.h583 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
585 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
588 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
590 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U)
591 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U)
598 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
600 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
603 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
605 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U)
606 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U)
[all …]
Dstm32l0xx_ll_bus.h225 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
227 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
252 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
276 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h861 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
863 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
870 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
872 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
881 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
883 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
889 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
891 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
898 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
900 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
[all …]
Dstm32g0xx_ll_bus.h253 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
255 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
277 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
298 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h698 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
700 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
706 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
708 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
714 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
716 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
721 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
722 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
723 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
1017 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
[all …]
Dstm32c0xx_ll_bus.h186 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
188 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
205 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
221 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dsystem_stm32l1xx.c312 RCC->AHBENR = 0x000080D8; in SystemInit_ExtMemCtl()
315 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); in SystemInit_ExtMemCtl()
367 RCC->AHBENR = 0x400080D8; in SystemInit_ExtMemCtl()
370 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_bus.h232 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
234 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
258 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
281 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dsystem_stm32f1xx.c356 RCC->AHBENR = 0x00000114U; in SystemInit_ExtMemCtl()
359 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32f101x6.h353 __IO uint32_t AHBENR; member

123456