1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ##### RCC Limitations #####
19 ==============================================================================
20 [..]
21 A delay between an RCC peripheral clock enable and the effective peripheral
22 enabling should be taken into account in order to manage the peripheral read/write
23 from/to registers.
24 (+) This delay depends on the peripheral mapping.
25 (++) AHB & APB peripherals, 1 dummy read is necessary
26
27 [..]
28 Workarounds:
29 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
30 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
31
32 @endverbatim
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32WB0x_LL_BUS_H
38 #define STM32WB0x_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif /* __cplusplus */
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32wb0x.h"
46
47 /** @addtogroup STM32WB0x_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
69 * @{
70 */
71
72 /** @defgroup BUS_LL_AHB1_GRP1_PERIPH AHB PERIPH
73 * @{
74 */
75 #define LL_AHB1_GRP1_PERIPH_ALL (RCC_AHBENR_DMAEN| \
76 RCC_AHBENR_GPIOAEN|\
77 RCC_AHBENR_GPIOBEN|\
78 RCC_AHBENR_CRCEN| \
79 RCC_AHBENR_PKAEN| \
80 RCC_AHBENR_RNGEN)
81 #define LL_AHB1_GRP1_PERIPH_DMA RCC_AHBENR_DMAEN
82 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
83 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
84 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
85 #if defined(PKA)
86 #define LL_AHB1_GRP1_PERIPH_PKA RCC_AHBENR_PKAEN
87 #endif
88 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
89
90 /**
91 * @}
92 */
93
94 /** @defgroup BUS_LL_APB0_GRP1_PERIPH APB0 PERIPH
95 * @{
96 */
97 #if defined(STM32WB06) || defined(STM32WB07)
98 #define LL_APB0_GRP1_PERIPH_ALL (RCC_APB0ENR_TIM1EN|RCC_APB0ENR_SYSCFGEN|RCC_APB0ENR_RTCEN|RCC_APB0ENR_WDGEN)
99 #elif defined(STM32WB05) || defined(STM32WB09)
100 #define LL_APB0_GRP1_PERIPH_ALL (RCC_APB0ENR_TIM2EN| \
101 RCC_APB0ENR_TIM16EN| \
102 RCC_APB0ENR_TIM17EN| \
103 RCC_APB0ENR_SYSCFGEN| \
104 RCC_APB0ENR_RTCEN| \
105 RCC_APB0ENR_WDGEN)
106 #endif
107 #if defined(TIM1)
108 #define LL_APB0_GRP1_PERIPH_TIM1 RCC_APB0ENR_TIM1EN
109 #endif
110 #if defined(TIM2)
111 #define LL_APB0_GRP1_PERIPH_TIM2 RCC_APB0ENR_TIM2EN
112 #endif
113 #if defined(TIM16)
114 #define LL_APB0_GRP1_PERIPH_TIM16 RCC_APB0ENR_TIM16EN
115 #endif
116 #if defined(TIM17)
117 #define LL_APB0_GRP1_PERIPH_TIM17 RCC_APB0ENR_TIM17EN
118 #endif
119 #define LL_APB0_GRP1_PERIPH_SYSCFG RCC_APB0ENR_SYSCFGEN
120 #define LL_APB0_GRP1_PERIPH_RTC RCC_APB0ENR_RTCEN
121 #define LL_APB0_GRP1_PERIPH_WDG RCC_APB0ENR_WDGEN
122
123 /**
124 * @}
125 */
126
127
128 /** @defgroup BUS_LL_APB1_GRP1_PERIPH APB1 PERIPH
129 * @{
130 */
131 #if defined(STM32WB06) || defined(STM32WB07)
132 #define LL_APB1_GRP1_PERIPH_ALL (RCC_APB1ENR_SPI1EN |\
133 RCC_APB1ENR_ADCDIGEN |\
134 RCC_APB1ENR_ADCANAEN |\
135 RCC_APB1ENR_LPUARTEN |\
136 RCC_APB1ENR_USARTEN |\
137 RCC_APB1ENR_SPI2EN |\
138 RCC_APB1ENR_SPI3EN |\
139 RCC_APB1ENR_I2C1EN |\
140 RCC_APB1ENR_I2C2EN)
141
142 #define LL_APB1_GRP1_RESET_PERIPH_ALL (RCC_APB1ENR_SPI1EN |\
143 RCC_APB1ENR_ADCDIGEN |\
144 RCC_APB1ENR_LPUARTEN |\
145 RCC_APB1ENR_USARTEN |\
146 RCC_APB1ENR_SPI2EN |\
147 RCC_APB1ENR_SPI3EN |\
148 RCC_APB1ENR_I2C1EN |\
149 RCC_APB1ENR_I2C2EN)
150
151 #elif defined(STM32WB05) || defined(STM32WB09)
152 #define LL_APB1_GRP1_PERIPH_ALL (RCC_APB1ENR_ADCDIGEN |\
153 RCC_APB1ENR_ADCANAEN |\
154 RCC_APB1ENR_LPUARTEN |\
155 RCC_APB1ENR_USARTEN |\
156 RCC_APB1ENR_SPI3EN |\
157 RCC_APB1ENR_I2C1EN)
158
159 #define LL_APB1_GRP1_RESET_PERIPH_ALL (RCC_APB1ENR_ADCDIGEN |\
160 RCC_APB1ENR_LPUARTEN |\
161 RCC_APB1ENR_USARTEN |\
162 RCC_APB1ENR_SPI3EN |\
163 RCC_APB1ENR_I2C1EN)
164 #endif
165 #if defined(SPI1)
166 #define LL_APB1_GRP1_PERIPH_SPI1 RCC_APB1ENR_SPI1EN
167 #endif
168 #define LL_APB1_GRP1_PERIPH_ADCDIG RCC_APB1ENR_ADCDIGEN
169 #define LL_APB1_GRP1_PERIPH_ADCANA RCC_APB1ENR_ADCANAEN
170 #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUARTEN
171 #define LL_APB1_GRP1_PERIPH_USART1 RCC_APB1ENR_USARTEN
172 #if defined(SPI2)
173 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
174 #endif
175 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
176 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
177 #if defined(I2C2)
178 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
179 #endif
180 /**
181 * @}
182 */
183
184 /** @defgroup BUS_LL_APB2_GRP1_PERIPH APB2 PERIPH
185 * @{
186 */
187 #if defined(BLUE)
188 #define LL_APB2_GRP1_PERIPH_ALL (RCC_APB2ENR_MRBLEEN)
189 #define LL_APB2_GRP1_PERIPH_MRBLE RCC_APB2ENR_MRBLEEN
190 #endif
191 /**
192 * @}
193 */
194
195 /**
196 * @}
197 */
198
199 /* Exported macro ------------------------------------------------------------*/
200
201 /* Exported functions --------------------------------------------------------*/
202
203 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
204 * @{
205 */
206
207 /** @defgroup BUS_LL_EF_AHB AHB
208 * @{
209 */
210
211 /**
212 * @brief Enable AHB peripherals clock.
213 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock
214 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock
215 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock
216 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock
217 * AHBENR PKAEN LL_AHB1_GRP1_EnableClock
218 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock
219 * @param Periphs This parameter can be a combination of the following values:
220 * @arg LL_AHB1_GRP1_PERIPH_DMA
221 * @arg LL_AHB1_GRP1_PERIPH_GPIOA
222 * @arg LL_AHB1_GRP1_PERIPH_GPIOB
223 * @arg LL_AHB1_GRP1_PERIPH_CRC
224 * @arg LL_AHB1_GRP1_PERIPH_PKA
225 * @arg LL_AHB1_GRP1_PERIPH_RNG
226 * @retval None
227 * @note LL_AHB1_GRP1_PERIPH_PKA
228 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)229 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
230 {
231 __IO uint32_t tmpreg;
232 SET_BIT(RCC->AHBENR, Periphs);
233 /* Delay after an RCC peripheral clock enabling */
234 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
235 (void)tmpreg;
236 }
237
238 /**
239 * @brief Check if AHB peripheral clock is enabled or not
240 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock
241 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock
242 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock
243 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock
244 * AHBENR PAKAEN LL_AHB1_GRP1_IsEnabledClock
245 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock
246 * @param Periphs This parameter can be a combination of the following values:
247 * @arg LL_AHB1_GRP1_PERIPH_DMA
248 * @arg LL_AHB1_GRP1_PERIPH_GPIOA
249 * @arg LL_AHB1_GRP1_PERIPH_GPIOB
250 * @arg LL_AHB1_GRP1_PERIPH_CRC
251 * @arg LL_AHB1_GRP1_PERIPH_PKA
252 * @arg LL_AHB1_GRP1_PERIPH_RNG
253 * @retval uint32_t
254 * @note LL_AHB1_GRP1_PERIPH_PKA
255 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)256 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
257 {
258 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
259 }
260
261 /**
262 * @brief Disable AHB peripherals clock.
263 * @rmtoll AHBENR DMAENN LL_AHB1_GRP1_DisableClock
264 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock
265 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock
266 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock
267 * AHBENR PKAEN LL_AHB1_GRP1_DisableClock
268 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock
269 * @param Periphs This parameter can be a combination of the following values:
270 * @arg LL_AHB1_GRP1_PERIPH_DMA
271 * @arg LL_AHB1_GRP1_PERIPH_GPIOA
272 * @arg LL_AHB1_GRP1_PERIPH_GPIOB
273 * @arg LL_AHB1_GRP1_PERIPH_CRC
274 * @arg LL_AHB1_GRP1_PERIPH_PKA
275 * @arg LL_AHB1_GRP1_PERIPH_RNG
276 * @retval None
277 * @note LL_AHB1_GRP1_PERIPH_PKA
278 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)279 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
280 {
281 CLEAR_BIT(RCC->AHBENR, Periphs);
282 }
283
284 /**
285 * @brief Force AHB peripherals reset.
286 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset
287 * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset
288 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset
289 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset
290 * AHBRSTR PKARST LL_AHB1_GRP1_ForceReset
291 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset
292 * @param Periphs This parameter can be a combination of the following values:
293 * @arg LL_AHB1_GRP1_PERIPH_DMA
294 * @arg LL_AHB1_GRP1_PERIPH_GPIOA
295 * @arg LL_AHB1_GRP1_PERIPH_GPIOB
296 * @arg LL_AHB1_GRP1_PERIPH_CRC
297 * @arg LL_AHB1_GRP1_PERIPH_PKA
298 * @arg LL_AHB1_GRP1_PERIPH_RNG
299 * @retval None
300 * @note LL_AHB1_GRP1_PERIPH_PKA
301 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)302 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
303 {
304 SET_BIT(RCC->AHBRSTR, Periphs);
305 }
306
307 /**
308 * @brief Release AHB peripherals reset.
309 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset
310 * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset
311 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset
312 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset
313 * AHBRSTR PKARST LL_AHB1_GRP1_ReleaseReset
314 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset
315 * @param Periphs This parameter can be a combination of the following values:
316 * @arg LL_AHB1_GRP1_PERIPH_DMA
317 * @arg LL_AHB1_GRP1_PERIPH_GPIOA
318 * @arg LL_AHB1_GRP1_PERIPH_GPIOB
319 * @arg LL_AHB1_GRP1_PERIPH_CRC
320 * @arg LL_AHB1_GRP1_PERIPH_PKA
321 * @arg LL_AHB1_GRP1_PERIPH_RNG
322 * @retval None
323 * @note LL_AHB1_GRP1_PERIPH_PKA
324 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)325 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
326 {
327 CLEAR_BIT(RCC->AHBRSTR, Periphs);
328 }
329 /**
330 * @}
331 */
332
333 /** @defgroup BUS_LL_EF_APB0 APB0
334 * @{
335 */
336
337 /**
338 * @brief Enable APB0 peripherals clock.
339 * @rmtoll APB0ENR TIM1EN LL_APB0_GRP1_EnableClock
340 * APB0ENR TIM2EN LL_APB0_GRP1_EnableClock
341 * APB0ENR TIM16EN LL_APB0_GRP1_EnableClock
342 * APB0ENR TIM17EN LL_APB0_GRP1_EnableClock
343 * APB0ENR SYSCFGEN LL_APB0_GRP1_EnableClock
344 * APB0ENR RTCEN LL_APB0_GRP1_EnableClock
345 * APB0ENR WDGEN LL_APB0_GRP1_EnableClock
346 * @param Periphs This parameter can be a combination of the following values:
347 * @arg LL_APB0_GRP1_PERIPH_TIM1
348 * @arg LL_APB0_GRP1_PERIPH_TIM2
349 * @arg LL_APB0_GRP1_PERIPH_TIM16
350 * @arg LL_APB0_GRP1_PERIPH_TIM17
351 * @arg LL_APB0_GRP1_PERIPH_SYSCFG
352 * @arg LL_APB0_GRP1_PERIPH_RTC
353 * @arg LL_APB0_GRP1_PERIPH_WDG
354 * @retval None
355 * @note LL_APB0_GRP1_PERIPH_TIM1 is valid only for STM32WB06 and STM32WB07
356 * @note LL_APB0_GRP1_PERIPH_TIM2, LL_APB0_GRP1_PERIPH_TIM16 and LL_APB0_GRP1_PERIPH_TIM17 are valid for STM32WB05 and STM32WB09
357 */
LL_APB0_GRP1_EnableClock(uint32_t Periphs)358 __STATIC_INLINE void LL_APB0_GRP1_EnableClock(uint32_t Periphs)
359 {
360 __IO uint32_t tmpreg;
361 SET_BIT(RCC->APB0ENR, Periphs);
362 /* Delay after an RCC peripheral clock enabling */
363 tmpreg = READ_BIT(RCC->APB0ENR, Periphs);
364 (void)tmpreg;
365 }
366
367 /**
368 * @brief Check if APB0 peripheral clock is enabled or not
369 * @rmtoll APB0ENR TIM1EN LL_APB0_GRP1_IsEnabledClock
370 * APB0ENR TIM2EN LL_APB0_GRP1_IsEnabledClock
371 * APB0ENR TIM16EN LL_APB0_GRP1_IsEnabledClock
372 * APB0ENR TIM17EN LL_APB0_GRP1_IsEnabledClock
373 * APB0ENR SYSCFGEN LL_APB0_GRP1_IsEnabledClock
374 * APB0ENR RTCEN LL_APB0_GRP1_IsEnabledClock
375 * APB0ENR WDGEN LL_APB0_GRP1_IsEnabledClock
376 * @param Periphs This parameter can be a combination of the following values:
377 * @arg LL_APB0_GRP1_PERIPH_TIM1
378 * @arg LL_APB0_GRP1_PERIPH_TIM2
379 * @arg LL_APB0_GRP1_PERIPH_TIM16
380 * @arg LL_APB0_GRP1_PERIPH_TIM17
381 * @arg LL_APB0_GRP1_PERIPH_SYSCFG
382 * @arg LL_APB0_GRP1_PERIPH_RTC
383 * @arg LL_APB0_GRP1_PERIPH_WDG
384 * @retval uint32_t
385 * @note LL_APB0_GRP1_PERIPH_TIM1 is valid only for STM32WB06 and STM32WB07
386 * @note LL_APB0_GRP1_PERIPH_TIM2, LL_APB0_GRP1_PERIPH_TIM16 and LL_APB0_GRP1_PERIPH_TIM17 are valid for STM32WB05 and STM32WB09
387 */
LL_APB0_GRP1_IsEnabledClock(uint32_t Periphs)388 __STATIC_INLINE uint32_t LL_APB0_GRP1_IsEnabledClock(uint32_t Periphs)
389 {
390 return ((READ_BIT(RCC->APB0ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
391 }
392
393 /**
394 * @brief Disable APB0 peripherals clock.
395 * @rmtoll APB0ENR TIM1EN LL_APB0_GRP1_DisableClock
396 * APB0ENR TIM2EN LL_APB0_GRP1_DisableClock
397 * APB0ENR TIM16EN LL_APB0_GRP1_DisableClock
398 * APB0ENR TIM17EN LL_APB0_GRP1_DisableClock
399 * APB0ENR SYSCFGEN LL_APB0_GRP1_DisableClock
400 * APB0ENR RTCEN LL_APB0_GRP1_DisableClock
401 * APB0ENR WDGEN LL_APB0_GRP1_DisableClock
402 * @param Periphs This parameter can be a combination of the following values:
403 * @arg LL_APB0_GRP1_PERIPH_TIM1
404 * @arg LL_APB0_GRP1_PERIPH_TIM2
405 * @arg LL_APB0_GRP1_PERIPH_TIM16
406 * @arg LL_APB0_GRP1_PERIPH_TIM17
407 * @arg LL_APB0_GRP1_PERIPH_SYSCFG
408 * @arg LL_APB0_GRP1_PERIPH_RTC
409 * @arg LL_APB0_GRP1_PERIPH_WDG
410 * @retval None
411 * @note LL_APB0_GRP1_PERIPH_TIM1 is valid only for STM32WB06 and STM32WB07
412 * @note LL_APB0_GRP1_PERIPH_TIM2, LL_APB0_GRP1_PERIPH_TIM16 and LL_APB0_GRP1_PERIPH_TIM17 are valid for STM32WB05 and STM32WB09
413 */
LL_APB0_GRP1_DisableClock(uint32_t Periphs)414 __STATIC_INLINE void LL_APB0_GRP1_DisableClock(uint32_t Periphs)
415 {
416 CLEAR_BIT(RCC->APB0ENR, Periphs);
417 }
418
419 /**
420 * @brief Force APB0 peripherals reset.
421 * @rmtoll APB0RSTR TIM1RST LL_APB0_GRP1_ForceReset
422 * APB0RSTR TIM2RST LL_APB0_GRP1_ForceReset
423 * APB0RSTR TIM16RST LL_APB0_GRP1_ForceReset
424 * APB0RSTR TIM17RST LL_APB0_GRP1_ForceReset
425 * APB0RSTR SYSCFGRST LL_APB0_GRP1_ForceReset
426 * APB0RSTR DACRST LL_APB0_GRP1_ForceReset
427 * APB0RSTR RTCRST LL_APB0_GRP1_ForceReset
428 * APB0RSTR WDGRST LL_APB0_GRP1_ForceReset
429 * @param Periphs This parameter can be a combination of the following values:
430 * @arg LL_APB0_GRP1_PERIPH_TIM1
431 * @arg LL_APB0_GRP1_PERIPH_TIM2
432 * @arg LL_APB0_GRP1_PERIPH_TIM16
433 * @arg LL_APB0_GRP1_PERIPH_TIM17
434 * @arg LL_APB0_GRP1_PERIPH_SYSCFG
435 * @arg LL_APB0_GRP1_PERIPH_RTC
436 * @arg LL_APB0_GRP1_PERIPH_WDG
437 * @retval None
438 * @note LL_APB0_GRP1_PERIPH_TIM1 is valid only for STM32WB06 and STM32WB07
439 * @note LL_APB0_GRP1_PERIPH_TIM2, LL_APB0_GRP1_PERIPH_TIM16 and LL_APB0_GRP1_PERIPH_TIM17 are valid for STM32WB05 and STM32WB09
440 */
LL_APB0_GRP1_ForceReset(uint32_t Periphs)441 __STATIC_INLINE void LL_APB0_GRP1_ForceReset(uint32_t Periphs)
442 {
443 SET_BIT(RCC->APB0RSTR, Periphs);
444 }
445
446 /**
447 * @brief Release APB0 peripherals reset.
448 * @rmtoll APB0RSTR TIM1RST LL_APB0_GRP1_ReleaseReset
449 * APB0RSTR TIM2RST LL_APB0_GRP1_ReleaseReset
450 * APB0RSTR TIM16RST LL_APB0_GRP1_ReleaseReset
451 * APB0RSTR TIM17RST LL_APB0_GRP1_ReleaseReset
452 * APB0RSTR SYSCFGRST LL_APB0_GRP1_ReleaseReset
453 * APB0RSTR DACRST LL_APB0_GRP1_ReleaseReset
454 * APB0RSTR RTCRST LL_APB0_GRP1_ReleaseReset
455 * APB0RSTR WDGRST LL_APB0_GRP1_ReleaseReset
456 * @param Periphs This parameter can be a combination of the following values:
457 * @arg LL_APB0_GRP1_PERIPH_TIM1
458 * @arg LL_APB0_GRP1_PERIPH_TIM2
459 * @arg LL_APB0_GRP1_PERIPH_TIM16
460 * @arg LL_APB0_GRP1_PERIPH_TIM17
461 * @arg LL_APB0_GRP1_PERIPH_SYSCFG
462 * @arg LL_APB0_GRP1_PERIPH_RTC
463 * @arg LL_APB0_GRP1_PERIPH_WDG
464 * @retval None
465 * @note LL_APB0_GRP1_PERIPH_TIM1 is valid only for STM32WB06 and STM32WB07
466 * @note LL_APB0_GRP1_PERIPH_TIM2, LL_APB0_GRP1_PERIPH_TIM16 and LL_APB0_GRP1_PERIPH_TIM17 are valid for STM32WB05 and STM32WB09
467 */
LL_APB0_GRP1_ReleaseReset(uint32_t Periphs)468 __STATIC_INLINE void LL_APB0_GRP1_ReleaseReset(uint32_t Periphs)
469 {
470 CLEAR_BIT(RCC->APB0RSTR, Periphs);
471 }
472 /**
473 * @}
474 */
475
476 /** @defgroup BUS_LL_EF_APB1 APB1
477 * @{
478 */
479
480 /**
481 * @brief Enable APB1 peripherals clock.
482 * @rmtoll APB1ENR SPI1EN LL_APB1_GRP1_EnableClock
483 * APB1ENR ADCDIGEN LL_APB1_GRP1_EnableClock
484 * APB1ENR ADCANAEN LL_APB1_GRP1_EnableClock
485 * APB1ENR LPUARTEN LL_APB1_GRP1_EnableClock
486 * APB1ENR USARTEN LL_APB1_GRP1_EnableClock
487 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock
488 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock
489 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock
490 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock
491 * @param Periphs This parameter can be a combination of the following values:
492 * @arg LL_APB1_GRP1_PERIPH_SPI1
493 * @arg LL_APB1_GRP1_PERIPH_ADCDIG
494 * @arg LL_APB1_GRP1_PERIPH_ADCANA
495 * @arg LL_APB1_GRP1_PERIPH_LPUART1
496 * @arg LL_APB1_GRP1_PERIPH_USART1
497 * @arg LL_APB1_GRP1_PERIPH_SPI2
498 * @arg LL_APB1_GRP1_PERIPH_SPI3
499 * @arg LL_APB1_GRP1_PERIPH_I2C1
500 * @arg LL_APB1_GRP1_PERIPH_I2C2
501 * @retval None
502 * @note LL_APB1_GRP1_PERIPH_SPI1, LL_APB1_GRP1_PERIPH_SPI2 and LL_APB1_GRP1_PERIPH_I2C2 are valid for STM32WB06 and STM32WB07
503 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)504 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
505 {
506 __IO uint32_t tmpreg;
507 SET_BIT(RCC->APB1ENR, Periphs);
508 /* Delay after an RCC peripheral clock enabling */
509 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
510 (void)tmpreg;
511 }
512
513 /**
514 * @brief Check if APB1 peripheral clock is enabled or not
515 * @rmtoll APB1ENR SPI1EN LL_APB1_GRP1_IsEnabledClock
516 * APB1ENR ADCDIGEN LL_APB1_GRP1_IsEnabledClock
517 * APB1ENR ADCANAEN LL_APB1_GRP1_IsEnabledClock
518 * APB1ENR LPUARTEN LL_APB1_GRP1_IsEnabledClock
519 * APB1ENR USARTEN LL_APB1_GRP1_IsEnabledClock
520 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock
521 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock
522 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock
523 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock
524 * @param Periphs This parameter can be a combination of the following values:
525 * @arg LL_APB1_GRP1_PERIPH_SPI1
526 * @arg LL_APB1_GRP1_PERIPH_ADCDIG
527 * @arg LL_APB1_GRP1_PERIPH_ADCANA
528 * @arg LL_APB1_GRP1_PERIPH_LPUART1
529 * @arg LL_APB1_GRP1_PERIPH_USART1
530 * @arg LL_APB1_GRP1_PERIPH_SPI2
531 * @arg LL_APB1_GRP1_PERIPH_SPI3
532 * @arg LL_APB1_GRP1_PERIPH_I2C1
533 * @arg LL_APB1_GRP1_PERIPH_I2C2
534 * @retval uint32_t
535 * @note LL_APB1_GRP1_PERIPH_SPI1, LL_APB1_GRP1_PERIPH_SPI2 and LL_APB1_GRP1_PERIPH_I2C2 are valid for STM32WB06 and STM32WB07
536 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)537 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
538 {
539 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
540 }
541
542 /**
543 * @brief Disable APB1 peripherals clock.
544 * @rmtoll APB1ENR SPI1EN LL_APB1_GRP1_IsEnabledClock
545 * APB1ENR ADCDIGEN LL_APB1_GRP1_DisableClock
546 * APB1ENR ADCANAEN LL_APB1_GRP1_DisableClock
547 * APB1ENR LPUARTEN LL_APB1_GRP1_DisableClock
548 * APB1ENR USARTEN LL_APB1_GRP1_DisableClock
549 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock
550 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock
551 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock
552 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock
553 * @param Periphs This parameter can be a combination of the following values:
554 * @arg LL_APB1_GRP1_PERIPH_SPI1
555 * @arg LL_APB1_GRP1_PERIPH_ADCDIG
556 * @arg LL_APB1_GRP1_PERIPH_ADCANA
557 * @arg LL_APB1_GRP1_PERIPH_LPUART1
558 * @arg LL_APB1_GRP1_PERIPH_USART1
559 * @arg LL_APB1_GRP1_PERIPH_SPI2
560 * @arg LL_APB1_GRP1_PERIPH_SPI3
561 * @arg LL_APB1_GRP1_PERIPH_I2C1
562 * @arg LL_APB1_GRP1_PERIPH_I2C2
563 * @retval None
564 * @note LL_APB1_GRP1_PERIPH_SPI1, LL_APB1_GRP1_PERIPH_SPI2 and LL_APB1_GRP1_PERIPH_I2C2 are valid for STM32WB06 and STM32WB07
565 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)566 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
567 {
568 CLEAR_BIT(RCC->APB1ENR, Periphs);
569 }
570
571 /**
572 * @brief Force APB1 peripherals reset.
573 * @rmtoll APB1RSTR SPI1RST LL_APB1_GRP1_ForceReset
574 * APB1RSTR ADCRST LL_APB1_GRP1_ForceReset
575 * APB1RSTR LPUARTRST LL_APB1_GRP1_ForceReset
576 * APB1RSTR USARTRST LL_APB1_GRP1_ForceReset
577 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset
578 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset
579 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset
580 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset
581 * @param Periphs This parameter can be a combination of the following values:
582 * @arg LL_APB1_GRP1_PERIPH_ALL
583 * @arg LL_APB1_GRP1_PERIPH_SPI1
584 * @arg LL_APB1_GRP1_PERIPH_ADCDIG
585 * @arg LL_APB1_GRP1_PERIPH_LPUART1
586 * @arg LL_APB1_GRP1_PERIPH_USART1
587 * @arg LL_APB1_GRP1_PERIPH_SPI2
588 * @arg LL_APB1_GRP1_PERIPH_SPI3
589 * @arg LL_APB1_GRP1_PERIPH_I2C1
590 * @arg LL_APB1_GRP1_PERIPH_I2C2
591 * @retval None
592 * @note LL_APB1_GRP1_PERIPH_SPI1, LL_APB1_GRP1_PERIPH_SPI2 and LL_APB1_GRP1_PERIPH_I2C2 are valid for STM32WB06 and STM32WB07
593 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)594 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
595 {
596 SET_BIT(RCC->APB1RSTR, Periphs);
597 }
598
599 /**
600 * @brief Release APB1 peripherals reset.
601 * @rmtoll APB1RSTR SPI1RST LL_APB1_GRP1_ReleaseReset
602 * APB1RSTR ADCRST LL_APB1_GRP1_ReleaseReset
603 * APB1RSTR LPUARTRST LL_APB1_GRP1_ReleaseReset
604 * APB1RSTR USARTRST LL_APB1_GRP1_ReleaseReset
605 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset
606 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset
607 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset
608 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset
609 * @param Periphs This parameter can be a combination of the following values:
610 * @arg LL_APB1_GRP1_PERIPH_ALL
611 * @arg LL_APB1_GRP1_PERIPH_SPI1
612 * @arg LL_APB1_GRP1_PERIPH_ADCDIG
613 * @arg LL_APB1_GRP1_PERIPH_LPUART1
614 * @arg LL_APB1_GRP1_PERIPH_USART1
615 * @arg LL_APB1_GRP1_PERIPH_SPI2
616 * @arg LL_APB1_GRP1_PERIPH_SPI3
617 * @arg LL_APB1_GRP1_PERIPH_I2C1
618 * @arg LL_APB1_GRP1_PERIPH_I2C2
619 * @retval None
620 * @note LL_APB1_GRP1_PERIPH_SPI1, LL_APB1_GRP1_PERIPH_SPI2 and LL_APB1_GRP1_PERIPH_I2C2 are valid for STM32WB06 and STM32WB07
621 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)622 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
623 {
624 CLEAR_BIT(RCC->APB1RSTR, Periphs);
625 }
626 /**
627 * @}
628 */
629
630 /** @defgroup BUS_LL_EF_APB2 APB2
631 * @{
632 */
633
634 /**
635 * @brief Enable APB2 peripherals clock.
636 * @rmtoll APB2ENR MRBLEEN LL_APB2_GRP1_EnableClock
637 * @param Periphs This parameter can be a combination of the following values:
638 * @arg LL_APB2_GRP1_PERIPH_MRBLE
639 * @retval None
640 * @note LL_APB2_GRP1_PERIPH_MRBLE
641 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)642 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
643 {
644 __IO uint32_t tmpreg;
645 SET_BIT(RCC->APB2ENR, Periphs);
646 /* Delay after an RCC peripheral clock enabling */
647 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
648 (void)tmpreg;
649 }
650
651 /**
652 * @brief Check if APB2 peripheral clock is enabled or not
653 * @rmtoll APB2ENR MRBLEEN LL_APB2_GRP1_IsEnabledClock
654 * @param Periphs This parameter can be a combination of the following values:
655 * @arg LL_APB2_GRP1_PERIPH_MRBLE
656 * @retval uint32_t
657 * @note LL_APB2_GRP1_PERIPH_MRBLE
658 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)659 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
660 {
661 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
662 }
663
664 /**
665 * @brief Disable APB2 peripherals clock.
666 * @rmtoll APB2ENR MRBLEEN LL_APB2_GRP1_DisableClock
667 * @param Periphs This parameter can be a combination of the following values:
668 * @arg LL_APB2_GRP1_PERIPH_MRBLE
669 * @retval None
670 * @note LL_APB2_GRP1_PERIPH_MRBLE
671 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)672 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
673 {
674 CLEAR_BIT(RCC->APB2ENR, Periphs);
675 }
676
677 /**
678 * @brief Force APB2 peripherals reset.
679 * @rmtoll APB2RSTR MRBLERST LL_APB2_GRP1_ForceReset
680 * @param Periphs This parameter can be a combination of the following values:
681 * @arg LL_APB2_GRP1_PERIPH_MRBLE
682 * @retval None
683 * @note LL_APB2_GRP1_PERIPH_MRBLE
684 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)685 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
686 {
687 SET_BIT(RCC->APB2RSTR, Periphs);
688 }
689
690 /**
691 * @brief Release APB2 peripherals reset.
692 * @rmtoll APB2RSTR MRBLERST LL_APB2_GRP1_ReleaseReset
693 * @param Periphs This parameter can be a combination of the following values:
694 * @arg LL_APB2_GRP1_PERIPH_MRBLE
695 * @retval None
696 * @note LL_APB2_GRP1_PERIPH_MRBLE
697 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)698 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
699 {
700 CLEAR_BIT(RCC->APB2RSTR, Periphs);
701 }
702
703 /**
704 * @}
705 */
706
707 /**
708 * @}
709 */
710
711 /**
712 * @}
713 */
714
715 #endif /* defined(RCC) */
716
717 /**
718 * @}
719 */
720
721 #ifdef __cplusplus
722 }
723 #endif /* __cplusplus */
724
725 #endif /* STM32WB0x_LL_BUS_H */
726
