1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32L1xx_HAL_RCC_EX_H 20 #define __STM32L1xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l1xx_hal_def.h" 28 29 /** @addtogroup STM32L1xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx_Private_Constants 38 * @{ 39 */ 40 41 #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ 42 || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 43 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 44 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 45 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ 46 || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 47 48 /* Alias word address of LSECSSON bit */ 49 #define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos 50 #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U))) 51 52 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ 53 54 /** 55 * @} 56 */ 57 58 /** @addtogroup RCCEx_Private_Macros 59 * @{ 60 */ 61 #if defined(LCD) 62 63 #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) 64 65 #else /* Not LCD LINE */ 66 67 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) 68 69 #endif /* LCD */ 70 71 /** 72 * @} 73 */ 74 75 /* Exported types ------------------------------------------------------------*/ 76 77 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 78 * @{ 79 */ 80 81 /** 82 * @brief RCC extended clocks structure definition 83 */ 84 typedef struct 85 { 86 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 87 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 88 89 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 90 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 91 92 #if defined(LCD) 93 94 uint32_t LCDClockSelection; /*!< specifies the LCD clock source. 95 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 96 97 #endif /* LCD */ 98 } RCC_PeriphCLKInitTypeDef; 99 100 /** 101 * @} 102 */ 103 104 /* Exported constants --------------------------------------------------------*/ 105 106 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 107 * @{ 108 */ 109 110 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 111 * @{ 112 */ 113 #define RCC_PERIPHCLK_RTC (0x00000001U) 114 115 #if defined(LCD) 116 117 #define RCC_PERIPHCLK_LCD (0x00000002U) 118 119 #endif /* LCD */ 120 121 /** 122 * @} 123 */ 124 125 #if defined(RCC_LSECSS_SUPPORT) 126 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 127 * @{ 128 */ 129 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 130 /** 131 * @} 132 */ 133 #endif /* RCC_LSECSS_SUPPORT */ 134 135 /** 136 * @} 137 */ 138 139 /* Exported macro ------------------------------------------------------------*/ 140 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 141 * @{ 142 */ 143 144 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable 145 * @brief Enables or disables the AHB1 peripheral clock. 146 * @note After reset, the peripheral clock (used for registers read/write access) 147 * is disabled and the application software has to enable this clock before 148 * using it. 149 * @{ 150 */ 151 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ 152 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ 153 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 154 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 155 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 156 || defined(STM32L162xE) || defined(STM32L162xDX) 157 158 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 159 __IO uint32_t tmpreg; \ 160 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 161 /* Delay after an RCC peripheral clock enabling */ \ 162 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 163 UNUSED(tmpreg); \ 164 } while(0U) 165 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) 166 167 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 168 169 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 170 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 171 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 172 173 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 174 __IO uint32_t tmpreg; \ 175 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 176 /* Delay after an RCC peripheral clock enabling */ \ 177 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 178 UNUSED(tmpreg); \ 179 } while(0U) 180 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 181 __IO uint32_t tmpreg; \ 182 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ 183 /* Delay after an RCC peripheral clock enabling */ \ 184 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ 185 UNUSED(tmpreg); \ 186 } while(0U) 187 188 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) 189 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) 190 191 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 192 193 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 194 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 195 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 196 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 197 || defined(STM32L162xE) || defined(STM32L162xDX) 198 199 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 200 __IO uint32_t tmpreg; \ 201 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 202 /* Delay after an RCC peripheral clock enabling */ \ 203 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 204 UNUSED(tmpreg); \ 205 } while(0U) 206 207 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 208 209 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 210 211 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ 212 || defined(STM32L162xE) || defined(STM32L162xDX) 213 214 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 215 __IO uint32_t tmpreg; \ 216 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ 217 /* Delay after an RCC peripheral clock enabling */ \ 218 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ 219 UNUSED(tmpreg); \ 220 } while(0U) 221 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) 222 223 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ 224 225 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 226 227 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 228 __IO uint32_t tmpreg; \ 229 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 230 /* Delay after an RCC peripheral clock enabling */ \ 231 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 232 UNUSED(tmpreg); \ 233 } while(0U) 234 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 235 236 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 237 238 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ 239 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ 240 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ 241 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ 242 || defined(STM32L162xE) || defined(STM32L162xDX) 243 244 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 245 __IO uint32_t tmpreg; \ 246 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ 247 /* Delay after an RCC peripheral clock enabling */ \ 248 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ 249 UNUSED(tmpreg); \ 250 } while(0U) 251 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) 252 253 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 254 255 /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. 256 * @note After reset, the peripheral clock (used for registers read/write access) 257 * is disabled and the application software has to enable this clock before 258 * using it. 259 */ 260 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ 261 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 262 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 263 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 264 265 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 266 __IO uint32_t tmpreg; \ 267 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 268 /* Delay after an RCC peripheral clock enabling */ \ 269 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 270 UNUSED(tmpreg); \ 271 } while(0U) 272 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 273 274 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 275 276 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 277 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 278 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 279 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 280 || defined(STM32L162xE) || defined(STM32L162xDX) 281 282 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 283 __IO uint32_t tmpreg; \ 284 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 285 /* Delay after an RCC peripheral clock enabling */ \ 286 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 287 UNUSED(tmpreg); \ 288 } while(0U) 289 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 290 291 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 292 293 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ 294 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 295 296 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 297 __IO uint32_t tmpreg; \ 298 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 299 /* Delay after an RCC peripheral clock enabling */ \ 300 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 301 UNUSED(tmpreg); \ 302 } while(0U) 303 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 304 __IO uint32_t tmpreg; \ 305 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 306 /* Delay after an RCC peripheral clock enabling */ \ 307 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 308 UNUSED(tmpreg); \ 309 } while(0U) 310 311 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 312 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 313 314 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ 315 316 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 317 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 318 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\ 319 || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ 320 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) 321 322 #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ 323 #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ 324 325 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ 326 327 /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. 328 * @note After reset, the peripheral clock (used for registers read/write access) 329 * is disabled and the application software has to enable this clock before 330 * using it. 331 */ 332 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 333 334 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 335 __IO uint32_t tmpreg; \ 336 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 337 /* Delay after an RCC peripheral clock enabling */ \ 338 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 339 UNUSED(tmpreg); \ 340 } while(0U) 341 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 342 343 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 344 345 /** 346 * @} 347 */ 348 349 350 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset 351 * @brief Forces or releases AHB peripheral reset. 352 * @{ 353 */ 354 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ 355 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ 356 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 357 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 358 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 359 || defined(STM32L162xE) || defined(STM32L162xDX) 360 361 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) 362 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) 363 364 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 365 366 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 367 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 368 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 369 370 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) 371 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) 372 373 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) 374 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) 375 376 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 377 378 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 379 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 380 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 381 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 382 || defined(STM32L162xE) || defined(STM32L162xDX) 383 384 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) 385 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) 386 387 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 388 389 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ 390 || defined(STM32L162xE) || defined(STM32L162xDX) 391 392 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) 393 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) 394 395 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ 396 397 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 398 399 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) 400 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) 401 402 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 403 404 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ 405 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ 406 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ 407 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ 408 || defined(STM32L162xE) || defined(STM32L162xDX) 409 410 #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) 411 #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) 412 413 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 414 415 /** @brief Forces or releases APB1 peripheral reset. 416 */ 417 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ 418 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 419 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 420 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 421 422 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 423 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 424 425 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 426 427 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 428 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 429 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 430 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 431 || defined(STM32L162xE) || defined(STM32L162xDX) 432 433 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 434 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 435 436 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 437 438 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ 439 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 440 441 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 442 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 443 444 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 445 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 446 447 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 448 449 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 450 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 451 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ 452 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) 453 454 #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ 455 #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ 456 457 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ 458 459 /** @brief Forces or releases APB2 peripheral reset. 460 */ 461 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 462 463 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 464 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 465 466 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 467 468 /** 469 * @} 470 */ 471 472 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable 473 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. 474 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 475 * power consumption. 476 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 477 * @note By default, all peripheral clocks are enabled during SLEEP mode. 478 * @{ 479 */ 480 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ 481 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ 482 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 483 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 484 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 485 || defined(STM32L162xE) || defined(STM32L162xDX) 486 487 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) 488 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) 489 490 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 491 492 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 493 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 494 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 495 496 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) 497 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) 498 499 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) 500 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) 501 502 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 503 504 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 505 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 506 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 507 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 508 || defined(STM32L162xE) || defined(STM32L162xDX) 509 510 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) 511 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) 512 513 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 514 515 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) 516 517 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) 518 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) 519 520 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ 521 522 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 523 524 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) 525 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) 526 527 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 528 529 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ 530 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ 531 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ 532 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ 533 || defined(STM32L162xE) || defined(STM32L162xDX) 534 535 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) 536 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) 537 538 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 539 540 /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. 541 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 542 * power consumption. 543 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 544 * @note By default, all peripheral clocks are enabled during SLEEP mode. 545 */ 546 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ 547 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 548 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 549 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 550 551 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 552 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 553 554 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 555 556 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 557 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 558 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 559 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 560 || defined(STM32L162xE) || defined(STM32L162xDX) 561 562 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 563 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 564 565 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 566 567 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ 568 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 569 570 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 571 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 572 573 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 574 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 575 576 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 577 578 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 579 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 580 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ 581 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) 582 583 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ 584 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ 585 586 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ 587 588 /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. 589 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 590 * power consumption. 591 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 592 * @note By default, all peripheral clocks are enabled during SLEEP mode. 593 */ 594 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 595 596 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 597 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 598 599 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 600 601 /** 602 * @} 603 */ 604 605 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status 606 * @brief Get the enable or disable status of peripheral clock. 607 * @note After reset, the peripheral clock (used for registers read/write access) 608 * is disabled and the application software has to enable this clock before 609 * using it. 610 * @{ 611 */ 612 613 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ 614 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ 615 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 616 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 617 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 618 || defined(STM32L162xE) || defined(STM32L162xDX) 619 620 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U) 621 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U) 622 623 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 624 625 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 626 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 627 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 628 629 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U) 630 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U) 631 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U) 632 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U) 633 634 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 635 636 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 637 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 638 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 639 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 640 || defined(STM32L162xE) || defined(STM32L162xDX) 641 642 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U) 643 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U) 644 645 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 646 647 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ 648 || defined(STM32L162xE) || defined(STM32L162xDX) 649 650 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U) 651 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U) 652 653 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ 654 655 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 656 657 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U) 658 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U) 659 660 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 661 662 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ 663 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ 664 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ 665 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ 666 || defined(STM32L162xE) || defined(STM32L162xDX) 667 668 #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U) 669 #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U) 670 671 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 672 673 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ 674 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 675 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 676 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 677 678 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U) 679 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U) 680 681 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 682 683 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 684 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 685 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 686 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 687 || defined(STM32L162xE) || defined(STM32L162xDX) 688 689 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U) 690 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U) 691 692 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 693 694 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ 695 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 696 697 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U) 698 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U) 699 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U) 700 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U) 701 702 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 703 704 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 705 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 706 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ 707 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) 708 709 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED() 710 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED() 711 712 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ 713 714 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 715 716 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U) 717 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U) 718 719 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 720 721 /** 722 * @} 723 */ 724 725 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status 726 * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode. 727 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 728 * power consumption. 729 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 730 * @note By default, all peripheral clocks are enabled during SLEEP mode. 731 * @{ 732 */ 733 734 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ 735 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ 736 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 737 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 738 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 739 || defined(STM32L162xE) || defined(STM32L162xDX) 740 741 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U) 742 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U) 743 744 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 745 746 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 747 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 748 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 749 750 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U) 751 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U) 752 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U) 753 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U) 754 755 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 756 757 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 758 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 759 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 760 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 761 || defined(STM32L162xE) || defined(STM32L162xDX) 762 763 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U) 764 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U) 765 766 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 767 768 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ 769 || defined(STM32L162xE) || defined(STM32L162xDX) 770 771 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U) 772 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U) 773 774 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ 775 776 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 777 778 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U) 779 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U) 780 781 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 782 783 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ 784 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ 785 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ 786 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ 787 || defined(STM32L162xE) || defined(STM32L162xDX) 788 789 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U) 790 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U) 791 792 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 793 794 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ 795 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 796 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 797 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 798 799 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U) 800 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U) 801 802 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 803 804 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ 805 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ 806 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ 807 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ 808 || defined(STM32L162xE) || defined(STM32L162xDX) 809 810 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U) 811 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U) 812 813 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 814 815 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ 816 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) 817 818 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U) 819 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U) 820 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U) 821 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U) 822 823 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 824 825 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ 826 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ 827 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ 828 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) 829 830 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() 831 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() 832 833 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ 834 835 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 836 837 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U) 838 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U) 839 840 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 841 842 /** 843 * @} 844 */ 845 846 847 #if defined(RCC_LSECSS_SUPPORT) 848 849 /** 850 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. 851 * @retval None 852 */ 853 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 854 855 /** 856 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. 857 * @retval None 858 */ 859 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 860 861 /** 862 * @brief Enable event on RCC LSE CSS EXTI Line 19. 863 * @retval None. 864 */ 865 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 866 867 /** 868 * @brief Disable event on RCC LSE CSS EXTI Line 19. 869 * @retval None. 870 */ 871 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 872 873 874 /** 875 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. 876 * @retval None. 877 */ 878 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 879 880 881 /** 882 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 883 * @retval None. 884 */ 885 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 886 887 888 /** 889 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. 890 * @retval None. 891 */ 892 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 893 894 /** 895 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 896 * @retval None. 897 */ 898 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 899 900 /** 901 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. 902 * @retval None. 903 */ 904 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 905 do { \ 906 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 907 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 908 } while(0U) 909 910 /** 911 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 912 * @retval None. 913 */ 914 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 915 do { \ 916 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 917 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 918 } while(0U) 919 920 /** 921 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 922 * @retval EXTI RCC LSE CSS Line Status. 923 */ 924 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) 925 926 /** 927 * @brief Clear the RCC LSE CSS EXTI flag. 928 * @retval None. 929 */ 930 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) 931 932 /** 933 * @brief Generate a Software interrupt on selected EXTI line. 934 * @retval None. 935 */ 936 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) 937 938 #endif /* RCC_LSECSS_SUPPORT */ 939 940 #if defined(LCD) 941 942 /** @defgroup RCCEx_LCD_Configuration LCD Configuration 943 * @brief Macros to configure clock source of LCD peripherals. 944 * @{ 945 */ 946 947 /** @brief Macro to configures LCD clock (LCDCLK). 948 * @note LCD and RTC use the same configuration 949 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the 950 * LCD clock source. 951 * 952 * @param __LCD_CLKSOURCE__ specifies the LCD clock source. 953 * This parameter can be one of the following values: 954 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock 955 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock 956 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock 957 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock 958 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock 959 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock 960 */ 961 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) 962 963 /** @brief Macro to get the LCD clock source. 964 */ 965 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() 966 967 /** @brief Macro to get the LCD clock pre-scaler. 968 */ 969 #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() 970 971 /** 972 * @} 973 */ 974 975 #endif /* LCD */ 976 977 978 /** 979 * @} 980 */ 981 982 /* Exported functions --------------------------------------------------------*/ 983 /** @addtogroup RCCEx_Exported_Functions 984 * @{ 985 */ 986 987 /** @addtogroup RCCEx_Exported_Functions_Group1 988 * @{ 989 */ 990 991 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 992 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 993 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 994 995 #if defined(RCC_LSECSS_SUPPORT) 996 997 void HAL_RCCEx_EnableLSECSS(void); 998 void HAL_RCCEx_DisableLSECSS(void); 999 void HAL_RCCEx_EnableLSECSS_IT(void); 1000 void HAL_RCCEx_LSECSS_IRQHandler(void); 1001 void HAL_RCCEx_LSECSS_Callback(void); 1002 1003 #endif /* RCC_LSECSS_SUPPORT */ 1004 1005 /** 1006 * @} 1007 */ 1008 1009 /** 1010 * @} 1011 */ 1012 1013 /** 1014 * @} 1015 */ 1016 1017 /** 1018 * @} 1019 */ 1020 1021 #ifdef __cplusplus 1022 } 1023 #endif 1024 1025 #endif /* __STM32L1xx_HAL_RCC_EX_H */ 1026 1027 1028
