Home
last modified time | relevance | path

Searched refs:ADC_CSR_EOC_SLV_Pos (Results 1 – 25 of 106) sorted by relevance

12345

/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h1898 #define ADC_CSR_EOC_SLV_Pos (18U) macro
1899 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f318xx.h1899 #define ADC_CSR_EOC_SLV_Pos (18U) macro
1900 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f302x8.h2007 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2008 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f328xx.h1958 #define ADC_CSR_EOC_SLV_Pos (18U) macro
1959 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f302xc.h2042 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2043 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f303x8.h1959 #define ADC_CSR_EOC_SLV_Pos (18U) macro
1960 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f358xx.h2184 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2185 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f303xc.h2226 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2227 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f302xe.h2133 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2134 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f303xe.h2337 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2338 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f398xx.h2293 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2294 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32f334x8.h2144 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2145 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h1982 #define ADC_CSR_EOC_SLV_Pos (18U) macro
1983 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g411xc.h2019 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2020 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g441xx.h2140 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2141 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32gbk1cb.h2092 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2093 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g431xx.h2106 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2107 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g4a1xx.h2220 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2221 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g491xx.h2186 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2187 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g473xx.h2275 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2276 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g471xx.h2197 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2198 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32g483xx.h2309 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2310 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h2103 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2104 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
Dstm32l412xx.h2068 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2069 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h2583 #define ADC_CSR_EOC_SLV_Pos (18U) macro
2584 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */

12345