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Searched refs:ADC_CSR_AWD3_SLV_Pos (Results 1 – 25 of 106) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h1919 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
1920 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f318xx.h1920 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
1921 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f302x8.h2028 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2029 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f328xx.h1979 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
1980 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f302xc.h2063 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2064 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f303x8.h1980 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
1981 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f358xx.h2205 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2206 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f303xc.h2247 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2248 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f302xe.h2154 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2155 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f303xe.h2358 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2359 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f398xx.h2314 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2315 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32f334x8.h2165 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2166 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h2003 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2004 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g411xc.h2040 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2041 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g441xx.h2161 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2162 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32gbk1cb.h2113 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2114 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g431xx.h2127 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2128 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g4a1xx.h2241 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2242 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g491xx.h2207 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2208 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g473xx.h2296 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2297 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g471xx.h2218 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2219 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32g483xx.h2330 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2331 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h2124 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2125 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
Dstm32l412xx.h2089 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2090 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h2604 #define ADC_CSR_AWD3_SLV_Pos (25U) macro
2605 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */

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