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Searched refs:ADC_CSR_AWD2_SLV_Pos (Results 1 – 25 of 106) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h1916 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
1917 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f318xx.h1917 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
1918 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f302x8.h2025 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2026 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f328xx.h1976 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
1977 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f302xc.h2060 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2061 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f303x8.h1977 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
1978 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f358xx.h2202 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2203 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f303xc.h2244 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2245 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f302xe.h2151 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2152 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f303xe.h2355 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2356 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f398xx.h2311 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2312 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32f334x8.h2162 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2163 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h2000 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2001 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g411xc.h2037 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2038 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g441xx.h2158 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2159 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32gbk1cb.h2110 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2111 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g431xx.h2124 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2125 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g4a1xx.h2238 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2239 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g491xx.h2204 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2205 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g473xx.h2293 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2294 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g471xx.h2215 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2216 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32g483xx.h2327 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2328 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h2121 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2122 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
Dstm32l412xx.h2086 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2087 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h2601 #define ADC_CSR_AWD2_SLV_Pos (24U) macro
2602 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */

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