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Searched refs:ADC_CSR_AWD1_SLV_Pos (Results 1 – 25 of 106) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h1913 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
1914 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f318xx.h1914 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
1915 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f302x8.h2022 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2023 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f328xx.h1973 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
1974 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f302xc.h2057 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2058 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f303x8.h1974 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
1975 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f358xx.h2199 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2200 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f303xc.h2241 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2242 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f302xe.h2148 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2149 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f303xe.h2352 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2353 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f398xx.h2308 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2309 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32f334x8.h2159 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2160 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h1997 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
1998 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g411xc.h2034 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2035 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g441xx.h2155 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2156 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32gbk1cb.h2107 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2108 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g431xx.h2121 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2122 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g4a1xx.h2235 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2236 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g491xx.h2201 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2202 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g473xx.h2290 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2291 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g471xx.h2212 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2213 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32g483xx.h2324 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2325 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h2118 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2119 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
Dstm32l412xx.h2083 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2084 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h2598 #define ADC_CSR_AWD1_SLV_Pos (23U) macro
2599 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */

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