__HCLK__ (reference) in projects: hal_stm32-3.5.0

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Searched refs:__HCLK__ (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/include/
D	stm32wlxx_hal_rcc.h	175 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2… argument 176 … ((__HCLK__) == RCC_SYSCLK_DIV3) \|\| ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| \ 177 … ((__HCLK__) == RCC_SYSCLK_DIV5) \|\| ((__HCLK__) == RCC_SYSCLK_DIV6) \|\| \ 178 … ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| ((__HCLK__) == RCC_SYSCLK_DIV10) \|\| \ 179 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV32) \|\| \ 180 … ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| \ 181 … ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| ((__HCLK__) == RCC_SYSCLK_DIV512))
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/include/
D	stm32f1xx_hal_rcc.h	`1344 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… argument 1345 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 1346 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 1347 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 1348 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32l0xx/drivers/include/
D	stm32l0xx_hal_rcc.h	`167 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… argument 168 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 169 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 170 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 171 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32f0xx/drivers/include/
D	stm32f0xx_hal_rcc.h	`160 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… argument 161 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 162 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 163 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 164 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/include/
D	stm32f3xx_hal_rcc.h	`208 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… argument 209 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 210 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 211 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 212 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
D	stm32u5xx_hal_rcc.c	`138 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 139 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 140 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 141 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 142 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/include/
D	stm32wbxx_hal_rcc.h	173 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2… argument 174 …((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV5) \|\| ((__HCLK__) == RCC_SYSCL… 175 …((__HCLK__) == RCC_SYSCLK_DIV8) \|\| ((__HCLK__) == RCC_SYSCLK_DIV10) \|\| ((__HCLK__) == RCC_SYSCL… 176 …((__HCLK__) == RCC_SYSCLK_DIV32) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| ((__HCLK__) == RCC_SYSCL… 177 … ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| ((__HCLK__) == RCC_SYSCLK_DIV512))
/hal_stm32-3.5.0/stm32cube/stm32l1xx/drivers/include/
D	stm32l1xx_hal_rcc.h	`195 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… argument 196 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 197 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 198 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 199 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
D	stm32g4xx_hal_rcc.h	`3303 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 3304 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 3305 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 3306 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 3307 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32g0xx/drivers/include/
D	stm32g0xx_hal_rcc.h	`132 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 133 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 134 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 135 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 136 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_hal_rcc.h	`3457 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 3458 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 3459 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 3460 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 3461 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_hal_rcc.h	`2255 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) =… argument 2256 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 2257 ((__HCLK__) == RCC_SYSCLK_DIV16))`
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_hal_rcc.h	`4768 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 4769 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 4770 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 4771 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 4772 ((__HCLK__) == RCC_SYSCLK_DIV512))`
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_hal_rcc.h	`4974 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)… argument 4975 … ((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \ 4976 … ((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \ 4977 … ((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \ 4978 ((__HCLK__) == RCC_SYSCLK_DIV512))`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
canopennode-3.5.0-3.4.0
chre-3.4.0
civetweb-2.7.6
cmsis-2.7.6
cmsis-3.4.0
cmsis-3.5.0
cmsis-3.7.0-3.6.0
cmsis-dsp-3.5.0
cmsis-dsp-3.7.0-3.6.0
cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
fatfs-3.7.0-3.6.0-3.5.0-3.4.0
hal_adi-3.7.0
hal_altera-2.7.6
hal_altera-3.6.0-3.5.0-3.4.0
hal_altera-3.7.0
hal_ambiq-3.5.0
hal_ambiq-3.6.0
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hal_atmel-2.7.6
hal_atmel-3.5.0-3.4.0
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hal_espressif-3.7.0
hal_ethos_u-3.6.0-3.5.0-3.4.0
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hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0
hal_infineon-2.7.6
hal_infineon-3.4.0
hal_infineon-3.5.0
hal_infineon-3.6.0
hal_infineon-3.7.0
hal_intel-3.5.0
hal_intel-3.6.0
hal_intel-3.7.0
hal_microchip-2.7.6
hal_microchip-3.6.0-3.5.0-3.4.0
hal_microchip-3.7.0
hal_nordic-2.7.6
hal_nordic-3.4.0
hal_nordic-3.5.0
hal_nordic-3.6.0
hal_nordic-3.7.0
hal_nuvoton-2.7.6
hal_nuvoton-3.4.0
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hal_nuvoton-3.6.0
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hal_nxp-2.7.6
hal_nxp-3.4.0
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hal_openisa-2.7.6
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hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
hal_renesas-3.4.0
hal_renesas-3.5.0
hal_renesas-3.6.0
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hal_rpi_pico-3.4.0
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hal_silabs-3.4.0
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hal_st-3.7.0
hal_stm32-2.7.6
hal_stm32-3.4.0
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hal_telink-2.7.6
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hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
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hostap-3.6.0
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liblc3-3.5.0-3.4.0
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