1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G0xx_HAL_RCC_H 20 #define STM32G0xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g0xx_hal_def.h" 28 #include "stm32g0xx_ll_rcc.h" 29 30 /** @addtogroup STM32G0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Private constants ---------------------------------------------------------*/ 39 /** @addtogroup RCC_Private_Constants 40 * @{ 41 */ 42 /* Defines used for Flags */ 43 #define CR_REG_INDEX 1U 44 #define BDCR_REG_INDEX 2U 45 #define CSR_REG_INDEX 3U 46 #if defined(RCC_HSI48_SUPPORT) 47 #define CRRCR_REG_INDEX 4U 48 #endif /* RCC_HSI48_SUPPORT */ 49 50 #define RCC_FLAG_MASK 0x1FU 51 52 /* Define used for IS_RCC_CLOCKTYPE() */ 53 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ 54 /** 55 * @} 56 */ 57 58 /* Private macros ------------------------------------------------------------*/ 59 /** @addtogroup RCC_Private_Macros 60 * @{ 61 */ 62 63 #if defined(RCC_HSI48_SUPPORT) 64 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 65 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 66 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 67 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 68 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 69 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 70 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 71 #else 72 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ 73 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 74 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 75 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 76 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 77 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 78 #endif /* RCC_HSI48_SUPPORT */ 79 80 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 81 ((__HSE__) == RCC_HSE_BYPASS)) 82 83 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 84 ((__LSE__) == RCC_LSE_BYPASS)) 85 86 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 87 88 #if defined(RCC_HSI48_SUPPORT) 89 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 90 #endif /* RCC_HSI48_SUPPORT */ 91 92 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 93 94 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 95 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ 96 ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ 97 ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) 98 99 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 100 101 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 102 ((__PLL__) == RCC_PLL_ON)) 103 104 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 105 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 106 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 107 108 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \ 109 ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \ 110 ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \ 111 ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8)) 112 113 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 114 115 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 116 117 #if defined(RCC_PLLQ_SUPPORT) 118 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 119 #endif /* RCC_PLLQ_SUPPORT */ 120 121 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 122 123 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ 124 & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) 125 126 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 127 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 128 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ 129 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ 130 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 131 132 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 133 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 134 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 135 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 136 ((__HCLK__) == RCC_SYSCLK_DIV512)) 137 138 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 139 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 140 ((__PCLK__) == RCC_HCLK_DIV16)) 141 142 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 143 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 144 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 145 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 146 147 #if defined(RCC_MCO2_SUPPORT) 148 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) ) 149 #else 150 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 151 #endif /* RCC_MCO2_SUPPORT */ 152 153 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) 154 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 155 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 156 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 157 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ 158 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 159 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 160 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 161 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 162 ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ 163 ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ 164 ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ 165 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) 166 #elif defined(STM32G0B0xx) 167 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 168 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 169 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 170 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 171 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 172 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 173 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 174 ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ 175 ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ 176 ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ 177 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) 178 #else 179 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 180 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 181 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 182 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 183 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 184 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 185 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 186 #endif /* STM32G0C1xx || STM32G0B1xx */ 187 188 #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 189 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 190 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 191 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ 192 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \ 193 ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \ 194 ((__DIV__) == RCC_MCODIV_1024)) 195 #else 196 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 197 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 198 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ 199 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128)) 200 #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 201 202 #if defined(RCC_MCO2_SUPPORT) 203 #if defined(RCC_HSI48_SUPPORT) 204 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 205 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 206 ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ 207 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 208 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 209 ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ 210 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 211 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ 212 ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ 213 ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ 214 ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ 215 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) 216 #else 217 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 218 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 219 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 220 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 221 ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ 222 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 223 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ 224 ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ 225 ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ 226 ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ 227 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) 228 #endif /* RCC_HSI48_SUPPORT */ 229 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ 230 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ 231 ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \ 232 ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \ 233 ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \ 234 ((__DIV__) == RCC_MCO2DIV_1024)) 235 236 #endif /* RCC_MCO2_SUPPORT */ 237 238 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 239 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 240 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 241 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 242 243 /** 244 * @} 245 */ 246 247 /* Exported types ------------------------------------------------------------*/ 248 /** @defgroup RCC_Exported_Types RCC Exported Types 249 * @{ 250 */ 251 252 /** 253 * @brief RCC PLL configuration structure definition 254 */ 255 typedef struct 256 { 257 uint32_t PLLState; /*!< The new state of the PLL. 258 This parameter can be a value of @ref RCC_PLL_Config */ 259 260 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 261 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 262 263 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 264 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 265 266 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 267 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 268 269 uint32_t PLLP; /*!< PLLP: PLL Division factor. 270 User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. 271 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 272 273 #if defined(RCC_PLLQ_SUPPORT) 274 uint32_t PLLQ; /*!< PLLQ: PLL Division factor. 275 User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. 276 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 277 #endif /* RCC_PLLQ_SUPPORT */ 278 279 uint32_t PLLR; /*!< PLLR: PLL Division for the main system clock. 280 User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. 281 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 282 283 } RCC_PLLInitTypeDef; 284 285 /** 286 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 287 */ 288 typedef struct 289 { 290 uint32_t OscillatorType; /*!< The oscillators to be configured. 291 This parameter can be a value of @ref RCC_Oscillator_Type */ 292 293 uint32_t HSEState; /*!< The new state of the HSE. 294 This parameter can be a value of @ref RCC_HSE_Config */ 295 296 uint32_t LSEState; /*!< The new state of the LSE. 297 This parameter can be a value of @ref RCC_LSE_Config */ 298 299 uint32_t HSIState; /*!< The new state of the HSI. 300 This parameter can be a value of @ref RCC_HSI_Config */ 301 302 uint32_t HSIDiv; /*!< The division factor of the HSI16. 303 This parameter can be a value of @ref RCC_HSI_Div */ 304 305 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 306 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 307 308 uint32_t LSIState; /*!< The new state of the LSI. 309 This parameter can be a value of @ref RCC_LSI_Config */ 310 311 #if defined(RCC_HSI48_SUPPORT) 312 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices). 313 This parameter can be a value of @ref RCC_HSI48_Config */ 314 315 #endif /* RCC_HSI48_SUPPORT */ 316 317 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 318 319 } RCC_OscInitTypeDef; 320 321 /** 322 * @brief RCC System, AHB and APB buses clock configuration structure definition 323 */ 324 typedef struct 325 { 326 uint32_t ClockType; /*!< The clock to be configured. 327 This parameter can be a combination of @ref RCC_System_Clock_Type */ 328 329 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 330 This parameter can be a value of @ref RCC_System_Clock_Source */ 331 332 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 333 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 334 335 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 336 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 337 338 339 } RCC_ClkInitTypeDef; 340 341 /** 342 * @} 343 */ 344 345 /* Exported constants --------------------------------------------------------*/ 346 /** @defgroup RCC_Exported_Constants RCC Exported Constants 347 * @{ 348 */ 349 350 /** @defgroup RCC_Timeout_Value Timeout Values 351 * @{ 352 */ 353 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 354 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup RCC_Oscillator_Type Oscillator Type 360 * @{ 361 */ 362 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 363 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 364 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 365 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 366 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 367 #if defined(RCC_HSI48_SUPPORT) 368 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 369 #endif /* RCC_HSI48_SUPPORT */ 370 371 /** 372 * @} 373 */ 374 375 /** @defgroup RCC_HSE_Config HSE Config 376 * @{ 377 */ 378 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 379 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 380 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup RCC_LSE_Config LSE Config 386 * @{ 387 */ 388 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 389 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 390 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 391 /** 392 * @} 393 */ 394 395 /** @defgroup RCC_HSI_Config HSI Config 396 * @{ 397 */ 398 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 399 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 400 401 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCC_HSI_Div HSI Div 407 * @{ 408 */ 409 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 410 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 411 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 412 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 413 #define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ 414 #define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ 415 #define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ 416 #define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCC_LSI_Config LSI Config 422 * @{ 423 */ 424 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 425 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 426 /** 427 * @} 428 */ 429 430 #if defined(RCC_HSI48_SUPPORT) 431 /** @defgroup RCC_HSI48_Config HSI48 Config 432 * @{ 433 */ 434 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 435 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 436 /** 437 * @} 438 */ 439 #endif /* RCC_HSI48_SUPPORT */ 440 441 /** @defgroup RCC_PLL_Config PLL Config 442 * @{ 443 */ 444 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 445 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 446 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 452 * @{ 453 */ 454 #define RCC_PLLM_DIV1 0x00000000U /*!< PLLM division factor = 8 */ 455 #define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0 /*!< PLLM division factor = 2 */ 456 #define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1 /*!< PLLM division factor = 3 */ 457 #define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 4 */ 458 #define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2 /*!< PLLM division factor = 5 */ 459 #define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 6 */ 460 #define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLLM division factor = 7 */ 461 #define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 8 */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 467 * @{ 468 */ 469 #define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0 /*!< PLLP division factor = 2 */ 470 #define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1 /*!< PLLP division factor = 3 */ 471 #define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 4 */ 472 #define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2 /*!< PLLP division factor = 5 */ 473 #define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 6 */ 474 #define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 7 */ 475 #define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 8 */ 476 #define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3 /*!< PLLP division factor = 9 */ 477 #define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 10 */ 478 #define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 11 */ 479 #define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 12 */ 480 #define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 13 */ 481 #define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 14 */ 482 #define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 15 */ 483 #define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 16 */ 484 #define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4 /*!< PLLP division factor = 17 */ 485 #define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 18 */ 486 #define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 19 */ 487 #define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 20 */ 488 #define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 21 */ 489 #define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 22 */ 490 #define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 23 */ 491 #define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 24 */ 492 #define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3) /*!< PLLP division factor = 25 */ 493 #define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 26 */ 494 #define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 27 */ 495 #define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 28 */ 496 #define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 29 */ 497 #define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 30 */ 498 #define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 31 */ 499 #define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */ 500 /** 501 * @} 502 */ 503 504 #if defined(RCC_PLLQ_SUPPORT) 505 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 506 * @{ 507 */ 508 #define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0 /*!< PLLQ division factor = 2 */ 509 #define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1 /*!< PLLQ division factor = 3 */ 510 #define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 4 */ 511 #define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2 /*!< PLLQ division factor = 5 */ 512 #define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 6 */ 513 #define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< PLLQ division factor = 7 */ 514 #define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 8 */ 515 /** * @} 516 */ 517 #endif /* RCC_PLLQ_SUPPORT */ 518 519 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 520 * @{ 521 */ 522 #define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0 /*!< PLLR division factor = 2 */ 523 #define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1 /*!< PLLR division factor = 3 */ 524 #define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 4 */ 525 #define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2 /*!< PLLR division factor = 5 */ 526 #define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 6 */ 527 #define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< PLLR division factor = 7 */ 528 #define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */ 529 /** * @} 530 */ 531 532 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 533 * @{ 534 */ 535 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 536 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 537 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 543 * @{ 544 */ 545 #define RCC_PLLPCLK RCC_PLLCFGR_PLLPEN /*!< PLLPCLK selection from main PLL */ 546 #if defined(RCC_PLLQ_SUPPORT) 547 #define RCC_PLLQCLK RCC_PLLCFGR_PLLQEN /*!< PLLQCLK selection from main PLL */ 548 #endif /* RCC_PLLQ_SUPPORT */ 549 #define RCC_PLLRCLK RCC_PLLCFGR_PLLREN /*!< PLLRCLK selection from main PLL */ 550 551 /** 552 * @} 553 */ 554 555 /** @defgroup RCC_System_Clock_Type System Clock Type 556 * @{ 557 */ 558 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 559 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 560 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup RCC_System_Clock_Source System Clock Source 566 * @{ 567 */ 568 #define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ 569 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ 570 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1 /*!< PLL selection as system clock */ 571 #define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ 572 #define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ 573 /** 574 * @} 575 */ 576 577 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 578 * @{ 579 */ 580 #define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ 581 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ 582 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1 /*!< PLL used as system clock */ 583 #define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ 584 #define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 590 * @{ 591 */ 592 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 593 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ 594 #define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ 595 #define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ 596 #define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ 597 #define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ 598 #define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ 599 #define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ 600 #define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup RCC_APB1_Clock_Source APB Clock Source 606 * @{ 607 */ 608 #define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ 609 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ 610 #define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ 611 #define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ 612 #define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 618 * @{ 619 */ 620 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ 621 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 622 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 623 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup RCC_MCO_Index MCO Index 629 * @{ 630 */ 631 #define RCC_MCO1 0x00000000U 632 #if defined(RCC_MCO2_SUPPORT) 633 #define RCC_MCO2 0x00000001U /*!< MCO2 index */ 634 #endif /* RCC_MCO2_SUPPORT */ 635 636 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 637 /** 638 * @} 639 */ 640 641 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 642 * @{ 643 */ 644 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 645 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 646 #if defined(RCC_HSI48_SUPPORT) 647 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */ 648 #endif /* RCC_HSI48_SUPPORT */ 649 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 650 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 651 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 652 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 653 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 654 #if defined(RCC_CFGR_MCOSEL_3) 655 #define RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */ 656 #define RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */ 657 #define RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */ 658 #define RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */ 659 #endif /* RCC_CFGR_MCOSEL_3 */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler 665 * @{ 666 */ 667 #define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ 668 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ 669 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ 670 #define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ 671 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ 672 #define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ 673 #define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ 674 #define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ 675 #if defined(RCC_CFGR_MCOPRE_3) 676 #define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ 677 #define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ 678 #define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */ 679 #endif /* RCC_CFGR_MCOSEL_3 */ 680 /** 681 * @} 682 */ 683 684 #if defined(RCC_MCO2_SUPPORT) 685 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 686 * @{ 687 */ 688 #define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ 689 #define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ 690 #if defined(RCC_HSI48_SUPPORT) 691 #define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */ 692 #endif /* RCC_HSI48_SUPPORT */ 693 #define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0) /*!< HSI selection as MCO2 source */ 694 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ 695 #define RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0) /*!< PLLCLK selection as MCO2 source */ 696 #define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */ 697 #define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */ 698 #define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */ 699 #define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */ 700 #define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */ 701 #define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */ 702 /** 703 * @} 704 */ 705 706 /** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler 707 * @{ 708 */ 709 #define RCC_MCO2DIV_1 0x00000000U /*!< MCO2 not divided */ 710 #define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ 711 #define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ 712 #define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ 713 #define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ 714 #define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ 715 #define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ 716 #define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ 717 #define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */ 718 #define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */ 719 #define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */ 720 /** 721 * @} 722 */ 723 #endif /* RCC_MCO2_SUPPORT */ 724 725 /** @defgroup RCC_Interrupt Interrupts 726 * @{ 727 */ 728 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 729 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 730 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 731 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 732 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 733 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 734 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 735 #if defined(RCC_HSI48_SUPPORT) 736 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 737 #endif /* RCC_HSI48_SUPPORT */ 738 /** 739 * @} 740 */ 741 742 /** @defgroup RCC_Flag Flags 743 * Elements values convention: XXXYYYYYb 744 * - YYYYY : Flag position in the register 745 * - XXX : Register index 746 * - 001: CR register 747 * - 010: BDCR register 748 * - 011: CSR register 749 * @{ 750 */ 751 /* Flags in the CR register */ 752 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 753 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 754 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 755 756 #if defined(RCC_HSI48_SUPPORT) 757 /* Flags in the CR register */ 758 #define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 759 #endif /* RCC_HSI48_SUPPORT */ 760 761 /* Flags in the BDCR register */ 762 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 763 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 764 765 /* Flags in the CSR register */ 766 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 767 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 768 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 769 #define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ 770 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 771 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 772 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 773 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 774 775 /** 776 * @} 777 */ 778 779 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 780 * @{ 781 */ 782 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 783 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 784 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 785 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 786 /** 787 * @} 788 */ 789 790 /** @defgroup RCC_Reset_Flag Reset Flag 791 * @{ 792 */ 793 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 794 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 795 #define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ 796 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 797 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 798 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 799 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 800 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 801 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 802 RCC_RESET_FLAG_LPWR) 803 /** 804 * @} 805 */ 806 807 /** 808 * @} 809 */ 810 811 /* Exported macros -----------------------------------------------------------*/ 812 813 /** @defgroup RCC_Exported_Macros RCC Exported Macros 814 * @{ 815 */ 816 817 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 818 * @brief Enable or disable the AHB peripheral clock. 819 * @note After reset, the peripheral clock (used for registers read/write access) 820 * is disabled and the application software has to enable this clock before 821 * using it. 822 * @{ 823 */ 824 825 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 826 __IO uint32_t tmpreg; \ 827 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 828 /* Delay after an RCC peripheral clock enabling */ \ 829 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 830 UNUSED(tmpreg); \ 831 } while(0U) 832 833 #if defined(DMA2) 834 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 835 __IO uint32_t tmpreg; \ 836 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 837 /* Delay after an RCC peripheral clock enabling */ \ 838 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 839 UNUSED(tmpreg); \ 840 } while(0U) 841 842 #endif /* DMA2 */ 843 844 845 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 846 __IO uint32_t tmpreg; \ 847 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 848 /* Delay after an RCC peripheral clock enabling */ \ 849 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 850 UNUSED(tmpreg); \ 851 } while(0U) 852 853 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 854 __IO uint32_t tmpreg; \ 855 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 856 /* Delay after an RCC peripheral clock enabling */ \ 857 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 858 UNUSED(tmpreg); \ 859 } while(0U) 860 861 #if defined(RNG) 862 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 863 __IO uint32_t tmpreg; \ 864 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 865 /* Delay after an RCC peripheral clock enabling */ \ 866 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 867 UNUSED(tmpreg); \ 868 } while(0U) 869 #endif /* RNG */ 870 871 #if defined(AES) 872 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 873 __IO uint32_t tmpreg; \ 874 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 875 /* Delay after an RCC peripheral clock enabling */ \ 876 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 877 UNUSED(tmpreg); \ 878 } while(0U) 879 #endif /* AES */ 880 881 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 882 #if defined(DMA2) 883 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) 884 #endif /* DMA2 */ 885 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) 886 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 887 #if defined(RNG) 888 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) 889 #endif /* RNG */ 890 #if defined(AES) 891 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) 892 #endif /* AES */ 893 /** 894 * @} 895 */ 896 897 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable 898 * @brief Enable or disable the IO Ports clock. 899 * @note After reset, the IO ports clock (used for registers read/write access) 900 * is disabled and the application software has to enable this clock before 901 * using it. 902 * @{ 903 */ 904 905 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 906 __IO uint32_t tmpreg; \ 907 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 908 /* Delay after an RCC peripheral clock enabling */ \ 909 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 910 UNUSED(tmpreg); \ 911 } while(0U) 912 913 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 914 __IO uint32_t tmpreg; \ 915 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 916 /* Delay after an RCC peripheral clock enabling */ \ 917 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 918 UNUSED(tmpreg); \ 919 } while(0U) 920 921 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 922 __IO uint32_t tmpreg; \ 923 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 924 /* Delay after an RCC peripheral clock enabling */ \ 925 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 926 UNUSED(tmpreg); \ 927 } while(0U) 928 929 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 930 __IO uint32_t tmpreg; \ 931 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 932 /* Delay after an RCC peripheral clock enabling */ \ 933 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 934 UNUSED(tmpreg); \ 935 } while(0U) 936 937 #if defined(GPIOE) 938 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 939 __IO uint32_t tmpreg; \ 940 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ 941 /* Delay after an RCC peripheral clock enabling */ \ 942 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ 943 UNUSED(tmpreg); \ 944 } while(0U) 945 #endif /* GPIOE */ 946 947 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 948 __IO uint32_t tmpreg; \ 949 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 950 /* Delay after an RCC peripheral clock enabling */ \ 951 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 952 UNUSED(tmpreg); \ 953 } while(0U) 954 955 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 956 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 957 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 958 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) 959 #if defined(GPIOE) 960 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) 961 #endif /* GPIOE */ 962 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) 963 964 /** 965 * @} 966 */ 967 968 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 969 * @brief Enable or disable the APB1 peripheral clock. 970 * @note After reset, the peripheral clock (used for registers read/write access) 971 * is disabled and the application software has to enable this clock before 972 * using it. 973 * @{ 974 */ 975 #if defined(TIM2) 976 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 977 __IO uint32_t tmpreg; \ 978 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 979 /* Delay after an RCC peripheral clock enabling */ \ 980 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 981 UNUSED(tmpreg); \ 982 } while(0U) 983 #endif /* TIM2 */ 984 985 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 986 __IO uint32_t tmpreg; \ 987 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 988 /* Delay after an RCC peripheral clock enabling */ \ 989 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 990 UNUSED(tmpreg); \ 991 } while(0U) 992 993 #if defined(TIM4) 994 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 995 __IO uint32_t tmpreg; \ 996 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ 997 /* Delay after an RCC peripheral clock enabling */ \ 998 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ 999 UNUSED(tmpreg); \ 1000 } while(0U) 1001 #endif /* TIM4 */ 1002 1003 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1004 __IO uint32_t tmpreg; \ 1005 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ 1006 /* Delay after an RCC peripheral clock enabling */ \ 1007 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ 1008 UNUSED(tmpreg); \ 1009 } while(0U) 1010 1011 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1012 __IO uint32_t tmpreg; \ 1013 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ 1014 /* Delay after an RCC peripheral clock enabling */ \ 1015 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ 1016 UNUSED(tmpreg); \ 1017 } while(0U) 1018 1019 #if defined(CRS) 1020 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1021 __IO uint32_t tmpreg; \ 1022 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 1023 /* Delay after an RCC peripheral clock enabling */ \ 1024 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ 1025 UNUSED(tmpreg); \ 1026 } while(0) 1027 #endif /* CRS */ 1028 1029 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1030 __IO uint32_t tmpreg; \ 1031 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 1032 /* Delay after an RCC peripheral clock enabling */ \ 1033 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 1034 UNUSED(tmpreg); \ 1035 } while(0U) 1036 1037 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1038 __IO uint32_t tmpreg; \ 1039 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 1040 /* Delay after an RCC peripheral clock enabling */ \ 1041 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 1042 UNUSED(tmpreg); \ 1043 } while(0U) 1044 1045 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1046 __IO uint32_t tmpreg; \ 1047 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 1048 /* Delay after an RCC peripheral clock enabling */ \ 1049 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ 1050 UNUSED(tmpreg); \ 1051 } while(0U) 1052 #if defined(SPI3) 1053 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1054 __IO uint32_t tmpreg; \ 1055 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ 1056 /* Delay after an RCC peripheral clock enabling */ \ 1057 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ 1058 UNUSED(tmpreg); \ 1059 } while(0U) 1060 #endif /* SPI3 */ 1061 1062 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1063 __IO uint32_t tmpreg; \ 1064 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 1065 /* Delay after an RCC peripheral clock enabling */ \ 1066 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 1067 UNUSED(tmpreg); \ 1068 } while(0U) 1069 1070 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1071 __IO uint32_t tmpreg; \ 1072 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ 1073 /* Delay after an RCC peripheral clock enabling */ \ 1074 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ 1075 UNUSED(tmpreg); \ 1076 } while(0U) 1077 1078 #define __HAL_RCC_USART4_CLK_ENABLE() do { \ 1079 __IO uint32_t tmpreg; \ 1080 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ 1081 /* Delay after an RCC peripheral clock enabling */ \ 1082 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ 1083 UNUSED(tmpreg); \ 1084 } while(0U) 1085 1086 #if defined(USART5) 1087 #define __HAL_RCC_USART5_CLK_ENABLE() do { \ 1088 __IO uint32_t tmpreg; \ 1089 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ 1090 /* Delay after an RCC peripheral clock enabling */ \ 1091 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ 1092 UNUSED(tmpreg); \ 1093 } while(0U) 1094 #endif /* USART5 */ 1095 1096 #if defined(USART6) 1097 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1098 __IO uint32_t tmpreg; \ 1099 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ 1100 /* Delay after an RCC peripheral clock enabling */ \ 1101 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ 1102 UNUSED(tmpreg); \ 1103 } while(0U) 1104 #endif /* USART6 */ 1105 1106 #if defined(LPUART1) 1107 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1108 __IO uint32_t tmpreg; \ 1109 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ 1110 /* Delay after an RCC peripheral clock enabling */ \ 1111 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ 1112 UNUSED(tmpreg); \ 1113 } while(0U) 1114 #endif /* LPUART1 */ 1115 1116 #if defined(LPUART2) 1117 #define __HAL_RCC_LPUART2_CLK_ENABLE() do { \ 1118 __IO uint32_t tmpreg; \ 1119 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ 1120 /* Delay after an RCC peripheral clock enabling */ \ 1121 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ 1122 UNUSED(tmpreg); \ 1123 } while(0U) 1124 #endif /* LPUART2 */ 1125 1126 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1127 __IO uint32_t tmpreg; \ 1128 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 1129 /* Delay after an RCC peripheral clock enabling */ \ 1130 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 1131 UNUSED(tmpreg); \ 1132 } while(0U) 1133 1134 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1135 __IO uint32_t tmpreg; \ 1136 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 1137 /* Delay after an RCC peripheral clock enabling */ \ 1138 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ 1139 UNUSED(tmpreg); \ 1140 } while(0U) 1141 1142 #if defined(I2C3) 1143 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1144 __IO uint32_t tmpreg; \ 1145 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ 1146 /* Delay after an RCC peripheral clock enabling */ \ 1147 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ 1148 UNUSED(tmpreg); \ 1149 } while(0U) 1150 #endif /* I2C3 */ 1151 1152 #if defined(CEC) 1153 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1154 __IO uint32_t tmpreg; \ 1155 SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ 1156 /* Delay after an RCC peripheral clock enabling */ \ 1157 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ 1158 UNUSED(tmpreg); \ 1159 } while(0U) 1160 #endif /* CEC */ 1161 1162 #if defined(UCPD1) 1163 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1164 __IO uint32_t tmpreg; \ 1165 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ 1166 /* Delay after an RCC peripheral clock enabling */ \ 1167 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ 1168 UNUSED(tmpreg); \ 1169 } while(0U) 1170 #endif /* UCPD1 */ 1171 1172 #if defined(UCPD2) 1173 #define __HAL_RCC_UCPD2_CLK_ENABLE() do { \ 1174 __IO uint32_t tmpreg; \ 1175 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ 1176 /* Delay after an RCC peripheral clock enabling */ \ 1177 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ 1178 UNUSED(tmpreg); \ 1179 } while(0U) 1180 #endif /* UCPD2 */ 1181 1182 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1183 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1184 __IO uint32_t tmpreg; \ 1185 SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 1186 /* Delay after an RCC peripheral clock enabling */ \ 1187 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ 1188 UNUSED(tmpreg); \ 1189 } while(0U) 1190 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1191 1192 #if defined(FDCAN1) || defined(FDCAN2) 1193 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 1194 __IO uint32_t tmpreg; \ 1195 SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ 1196 /* Delay after an RCC peripheral clock enabling */ \ 1197 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ 1198 UNUSED(tmpreg); \ 1199 } while(0) 1200 #endif /* FDCAN1 || FDCAN2 */ 1201 1202 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ 1203 __IO uint32_t tmpreg; \ 1204 SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 1205 /* Delay after an RCC peripheral clock enabling */ \ 1206 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 1207 UNUSED(tmpreg); \ 1208 } while(0U) 1209 1210 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1211 __IO uint32_t tmpreg; \ 1212 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 1213 /* Delay after an RCC peripheral clock enabling */ \ 1214 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 1215 UNUSED(tmpreg); \ 1216 } while(0U) 1217 1218 #if defined(DAC1) 1219 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1220 __IO uint32_t tmpreg; \ 1221 SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ 1222 /* Delay after an RCC peripheral clock enabling */ \ 1223 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ 1224 UNUSED(tmpreg); \ 1225 } while(0U) 1226 #endif /* DAC1 */ 1227 1228 #if defined(LPTIM2) 1229 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1230 __IO uint32_t tmpreg; \ 1231 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ 1232 /* Delay after an RCC peripheral clock enabling */ \ 1233 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ 1234 UNUSED(tmpreg); \ 1235 } while(0U) 1236 #endif /* LPTIM2 */ 1237 1238 #if defined(LPTIM1) 1239 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1240 __IO uint32_t tmpreg; \ 1241 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ 1242 /* Delay after an RCC peripheral clock enabling */ \ 1243 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ 1244 UNUSED(tmpreg); \ 1245 } while(0U) 1246 #endif /* LPTIM1 */ 1247 1248 /** 1249 * @} 1250 */ 1251 1252 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1253 * @brief Enable or disable the APB2 peripheral clock. 1254 * @note After reset, the peripheral clock (used for registers read/write access) 1255 * is disabled and the application software has to enable this clock before 1256 * using it. 1257 * @{ 1258 */ 1259 1260 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1261 __IO uint32_t tmpreg; \ 1262 SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 1263 /* Delay after an RCC peripheral clock enabling */ \ 1264 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 1265 UNUSED(tmpreg); \ 1266 } while(0U) 1267 1268 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1269 __IO uint32_t tmpreg; \ 1270 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 1271 /* Delay after an RCC peripheral clock enabling */ \ 1272 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 1273 UNUSED(tmpreg); \ 1274 } while(0U) 1275 1276 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1277 __IO uint32_t tmpreg; \ 1278 SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 1279 /* Delay after an RCC peripheral clock enabling */ \ 1280 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 1281 UNUSED(tmpreg); \ 1282 } while(0U) 1283 1284 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1285 __IO uint32_t tmpreg; \ 1286 SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 1287 /* Delay after an RCC peripheral clock enabling */ \ 1288 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 1289 UNUSED(tmpreg); \ 1290 } while(0U) 1291 1292 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1293 __IO uint32_t tmpreg; \ 1294 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 1295 /* Delay after an RCC peripheral clock enabling */ \ 1296 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 1297 UNUSED(tmpreg); \ 1298 } while(0U) 1299 1300 #if defined(TIM15) 1301 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1302 __IO uint32_t tmpreg; \ 1303 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ 1304 /* Delay after an RCC peripheral clock enabling */ \ 1305 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ 1306 UNUSED(tmpreg); \ 1307 } while(0U) 1308 #endif /* TIM15 */ 1309 1310 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1311 __IO uint32_t tmpreg; \ 1312 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 1313 /* Delay after an RCC peripheral clock enabling */ \ 1314 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 1315 UNUSED(tmpreg); \ 1316 } while(0U) 1317 1318 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1319 __IO uint32_t tmpreg; \ 1320 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 1321 /* Delay after an RCC peripheral clock enabling */ \ 1322 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 1323 UNUSED(tmpreg); \ 1324 } while(0U) 1325 1326 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 1327 __IO uint32_t tmpreg; \ 1328 SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 1329 /* Delay after an RCC peripheral clock enabling */ \ 1330 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 1331 UNUSED(tmpreg); \ 1332 } while(0U) 1333 1334 #if defined(TIM2) 1335 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) 1336 #endif /* TIM2 */ 1337 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) 1338 #if defined(TIM4) 1339 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) 1340 #endif /* TIM4 */ 1341 #if defined(TIM6) 1342 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) 1343 #endif /* TIM6 */ 1344 #if defined(TIM7) 1345 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) 1346 #endif /* TIM7 */ 1347 #if defined(CRS) 1348 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); 1349 #endif /* CRS */ 1350 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) 1351 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) 1352 #if defined(SPI3) 1353 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) 1354 #endif /* SPI3 */ 1355 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) 1356 #if defined(USART3) 1357 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) 1358 #endif /* USART3 */ 1359 #if defined(USART4) 1360 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) 1361 #endif /* USART4 */ 1362 #if defined(USART5) 1363 #define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) 1364 #endif /* USART5 */ 1365 #if defined(USART6) 1366 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) 1367 #endif /* USART6 */ 1368 #if defined(LPUART1) 1369 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) 1370 #endif /* LPUART1 */ 1371 #if defined(LPUART2) 1372 #define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) 1373 #endif /* LPUART2 */ 1374 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) 1375 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) 1376 #if defined(I2C3) 1377 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) 1378 #endif /* I2C3 */ 1379 #if defined(CEC) 1380 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) 1381 #endif /* CEC */ 1382 #if defined(UCPD1) 1383 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) 1384 #endif /* UCPD1 */ 1385 #if defined(UCPD2) 1386 #define __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) 1387 #endif /* UCPD2 */ 1388 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1389 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) 1390 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1391 #if defined(FDCAN1) || defined(FDCAN2) 1392 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) 1393 #endif /* FDCAN1 || FDCAN2 */ 1394 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) 1395 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) 1396 #if defined(DAC1) 1397 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) 1398 #endif /* DAC1 */ 1399 #if defined(LPTIM1) 1400 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) 1401 #endif /* LPTIM1 */ 1402 #if defined(LPTIM2) 1403 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) 1404 #endif /* LPTIM2 */ 1405 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) 1406 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) 1407 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) 1408 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) 1409 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) 1410 #if defined(TIM15) 1411 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) 1412 #endif /* TIM15 */ 1413 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) 1414 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) 1415 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) 1416 1417 /** 1418 * @} 1419 */ 1420 1421 /** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status 1422 * @brief Check whether the AHB peripheral clock is enabled or not. 1423 * @note After reset, the peripheral clock (used for registers read/write access) 1424 * is disabled and the application software has to enable this clock before 1425 * using it. 1426 * @{ 1427 */ 1428 1429 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET) 1430 #if defined(DMA2) 1431 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET) 1432 #endif /* DMA2 */ 1433 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET) 1434 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET) 1435 #if defined(RNG) 1436 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET) 1437 #endif /* RNG */ 1438 #if defined(AES) 1439 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET) 1440 #endif /* AES */ 1441 1442 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET) 1443 #if defined(DMA2) 1444 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET) 1445 #endif /* DMA2 */ 1446 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET) 1447 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET) 1448 #if defined(RNG) 1449 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET) 1450 #endif /* RNG */ 1451 #if defined(AES) 1452 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET) 1453 #endif /* AES */ 1454 /** 1455 * @} 1456 */ 1457 1458 /** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status 1459 * @brief Check whether the IO Port clock is enabled or not. 1460 * @note After reset, the peripheral clock (used for registers read/write access) 1461 * is disabled and the application software has to enable this clock before 1462 * using it. 1463 * @{ 1464 */ 1465 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET) 1466 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET) 1467 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET) 1468 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET) 1469 #if defined(GPIOE) 1470 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET) 1471 #endif /* GPIOE */ 1472 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET) 1473 1474 1475 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET) 1476 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET) 1477 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET) 1478 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET) 1479 #if defined(GPIOE) 1480 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET) 1481 #endif /* GPIOE */ 1482 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET) 1483 1484 /** 1485 * @} 1486 */ 1487 1488 /** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status 1489 * @brief Check whether the APB1 peripheral clock is enabled or not. 1490 * @note After reset, the peripheral clock (used for registers read/write access) 1491 * is disabled and the application software has to enable this clock before 1492 * using it. 1493 * @{ 1494 */ 1495 1496 #if defined(TIM2) 1497 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) 1498 #endif /* TIM2 */ 1499 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) 1500 #if defined(TIM4) 1501 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U) 1502 #endif /* TIM4 */ 1503 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U) 1504 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U) 1505 #if defined(CRS) 1506 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) 1507 #endif /* CRS */ 1508 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) 1509 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) 1510 #if defined(FDCAN1) || defined(FDCAN2) 1511 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U) 1512 #endif /* FDCAN1 || FDCAN2 */ 1513 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1514 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) 1515 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1516 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) 1517 #if defined(SPI3) 1518 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U) 1519 #endif /* SPI3 */ 1520 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) 1521 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) 1522 #define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) 1523 #if defined(USART5) 1524 #define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U) 1525 #endif /* USART5 */ 1526 #if defined(USART6) 1527 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U) 1528 #endif /* USART6 */ 1529 #if defined(LPUART1) 1530 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U) 1531 #endif /* LPUART1 */ 1532 #if defined(LPUART2) 1533 #define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U) 1534 #endif /* LPUART2 */ 1535 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) 1536 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) 1537 #if defined(I2C3) 1538 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U) 1539 #endif /* I2C3 */ 1540 #if defined(CEC) 1541 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U) 1542 #endif /* CEC */ 1543 #if defined(UCPD1) 1544 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U) 1545 #endif /* UCPD1 */ 1546 #if defined(UCPD2) 1547 #define __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U) 1548 #endif /* UCPD2 */ 1549 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) 1550 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) 1551 #if defined(DAC1) 1552 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U) 1553 #endif /* DAC1 */ 1554 #if defined(LPTIM2) 1555 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U) 1556 #endif /* LPTIM2 */ 1557 #if defined(LPTIM1) 1558 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U) 1559 #endif /* LPTIM1 */ 1560 #if defined(TIM2) 1561 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) 1562 #endif /* TIM2 */ 1563 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) 1564 #if defined(TIM4) 1565 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U) 1566 #endif /* TIM4 */ 1567 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U) 1568 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U) 1569 #if defined(CRS) 1570 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) 1571 #endif /* CRS */ 1572 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) 1573 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) 1574 #if defined(FDCAN1) || defined(FDCAN2) 1575 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U) 1576 #endif /* FDCAN1 || FDCAN2 */ 1577 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1578 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) 1579 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1580 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) 1581 #if defined(SPI3) 1582 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U) 1583 #endif /* SPI3 */ 1584 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) 1585 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) 1586 #define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) 1587 #if defined(USART5) 1588 #define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U) 1589 #endif /* USART5 */ 1590 #if defined(USART6) 1591 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U) 1592 #endif /* USART6 */ 1593 #if defined(LPUART1) 1594 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U) 1595 #endif /* LPUART1 */ 1596 #if defined(LPUART2) 1597 #define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U) 1598 #endif /* LPUART2 */ 1599 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) 1600 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) 1601 #if defined(I2C3) 1602 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U) 1603 #endif /* I2C3 */ 1604 #if defined(CEC) 1605 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U) 1606 #endif /* CEC */ 1607 #if defined(UCPD1) 1608 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U) 1609 #endif /* UCPD1 */ 1610 #if defined(UCPD2) 1611 #define __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U) 1612 #endif /* UCPD2 */ 1613 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) 1614 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) 1615 #if defined(DAC1) 1616 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U) 1617 #endif /* DAC1 */ 1618 #if defined(LPTIM2) 1619 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U) 1620 #endif /* LPTIM2 */ 1621 #if defined(LPTIM1) 1622 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U) 1623 #endif /* LPTIM1 */ 1624 1625 /** 1626 * @} 1627 */ 1628 1629 /** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status 1630 * @brief Check whether the APB2 peripheral clock is enabled or not. 1631 * @note After reset, the peripheral clock (used for registers read/write access) 1632 * is disabled and the application software has to enable this clock before 1633 * using it. 1634 * @{ 1635 */ 1636 1637 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) 1638 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) 1639 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) 1640 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) 1641 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) 1642 #if defined(TIM15) 1643 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) 1644 #endif /* TIM15 */ 1645 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) 1646 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) 1647 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) 1648 1649 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) 1650 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) 1651 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) 1652 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) 1653 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) 1654 #if defined(TIM15) 1655 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) 1656 #endif /* TIM15 */ 1657 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) 1658 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) 1659 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) 1660 1661 /** 1662 * @} 1663 */ 1664 1665 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 1666 * @brief Force or release AHB1 peripheral reset. 1667 * @{ 1668 */ 1669 #define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) 1670 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1671 #if defined(DMA2) 1672 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) 1673 #endif /* DMA2 */ 1674 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1675 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1676 #if defined(RNG) 1677 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) 1678 #endif /* RNG */ 1679 #if defined(AES) 1680 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) 1681 #endif /* AES */ 1682 1683 #define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) 1684 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 1685 #if defined(DMA2) 1686 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) 1687 #endif /* DMA2 */ 1688 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 1689 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 1690 #if defined(RNG) 1691 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) 1692 #endif /* RNG */ 1693 #if defined(AES) 1694 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) 1695 #endif /* AES */ 1696 /** 1697 * @} 1698 */ 1699 1700 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset 1701 * @brief Force or release IO Port reset. 1702 * @{ 1703 */ 1704 #define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) 1705 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1706 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1707 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1708 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1709 #if defined(GPIOE) 1710 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) 1711 #endif /* GPIOE */ 1712 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1713 1714 #define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) 1715 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 1716 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 1717 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 1718 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 1719 #if defined(GPIOE) 1720 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) 1721 #endif /* GPIOE */ 1722 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 1723 1724 /** 1725 * @} 1726 */ 1727 1728 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1729 * @brief Force or release APB1 peripheral reset. 1730 * @{ 1731 */ 1732 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) 1733 1734 #if defined(TIM2) 1735 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1736 #endif /* TIM2 */ 1737 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1738 #if defined(TIM4) 1739 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) 1740 #endif /* TIM4 */ 1741 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) 1742 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) 1743 #if defined(CRS) 1744 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1745 #endif /* CRS */ 1746 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1747 #if defined(SPI3) 1748 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) 1749 #endif /* SPI3 */ 1750 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1751 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) 1752 #define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) 1753 #if defined(USART5) 1754 #define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) 1755 #endif /* USART5 */ 1756 #if defined(USART6) 1757 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) 1758 #endif /* USART6 */ 1759 #if defined(LPUART1) 1760 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) 1761 #endif /* LPUART1 */ 1762 #if defined(LPUART2) 1763 #define __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) 1764 #endif /* LPUART2 */ 1765 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1766 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1767 #if defined(I2C3) 1768 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) 1769 #endif /* I2C3 */ 1770 #if defined(CEC) 1771 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) 1772 #endif /* CEC */ 1773 #if defined(UCPD1) 1774 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) 1775 #endif /* UCPD1 */ 1776 #if defined(UCPD2) 1777 #define __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) 1778 #endif /* UCPD2 */ 1779 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1780 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1781 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1782 #if defined(FDCAN1) || defined(FDCAN2) 1783 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) 1784 #endif /* FDCAN1 || FDCAN2 */ 1785 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 1786 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1787 #if defined(DAC1) 1788 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) 1789 #endif /* DAC1 */ 1790 #if defined(LPTIM2) 1791 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) 1792 #endif /* LPTIM2 */ 1793 #if defined(LPTIM1) 1794 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) 1795 #endif /* LPTIM1 */ 1796 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) 1797 #if defined(TIM2) 1798 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) 1799 #endif /* TIM2 */ 1800 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 1801 #if defined(TIM4) 1802 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) 1803 #endif /* TIM4 */ 1804 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) 1805 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) 1806 #if defined(CRS) 1807 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) 1808 #endif /* CRS */ 1809 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) 1810 #if defined(SPI3) 1811 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) 1812 #endif /* SPI3 */ 1813 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 1814 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) 1815 #define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) 1816 #if defined(USART5) 1817 #define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) 1818 #endif /* USART5 */ 1819 #if defined(USART6) 1820 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) 1821 #endif /* USART6 */ 1822 #if defined(LPUART1) 1823 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) 1824 #endif /* LPUART1 */ 1825 #if defined(LPUART2) 1826 #define __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) 1827 #endif /* LPUART2 */ 1828 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 1829 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) 1830 #if defined(I2C3) 1831 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) 1832 #endif /* I2C3 */ 1833 #if defined(CEC) 1834 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) 1835 #endif /* CEC */ 1836 #if defined(UCPD1) 1837 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) 1838 #endif /* UCPD1 */ 1839 #if defined(UCPD2) 1840 #define __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) 1841 #endif /* UCPD2 */ 1842 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 1843 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) 1844 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 1845 #if defined(FDCAN1) || defined(FDCAN2) 1846 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) 1847 #endif /* FDCAN1 || FDCAN2 */ 1848 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 1849 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 1850 #if defined(DAC1) 1851 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) 1852 #endif /* DAC1 */ 1853 #if defined(LPTIM2) 1854 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) 1855 #endif /* LPTIM2 */ 1856 #if defined(LPTIM1) 1857 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) 1858 #endif /* LPTIM1 */ 1859 /** 1860 * @} 1861 */ 1862 1863 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1864 * @brief Force or release APB2 peripheral reset. 1865 * @{ 1866 */ 1867 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) 1868 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1869 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1870 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1871 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1872 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 1873 #if defined(TIM15) 1874 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) 1875 #endif /* TIM15 */ 1876 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1877 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 1878 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1879 1880 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U) 1881 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1882 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1883 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1884 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1885 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 1886 #if defined(TIM15) 1887 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) 1888 #endif /* TIM15 */ 1889 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1890 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 1891 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1892 1893 /** 1894 * @} 1895 */ 1896 1897 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable 1898 * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. 1899 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1900 * power consumption. 1901 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1902 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1903 * @{ 1904 */ 1905 1906 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1907 #if defined(DMA2) 1908 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) 1909 #endif /* DMA2 */ 1910 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1911 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1912 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1913 #if defined(RNG) 1914 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) 1915 #endif /* RNG */ 1916 #if defined(AES) 1917 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) 1918 #endif /* AES */ 1919 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1920 #if defined(DMA2) 1921 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) 1922 #endif /* DMA2 */ 1923 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1924 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1925 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1926 #if defined(RNG) 1927 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) 1928 #endif /* RNG */ 1929 #if defined(AES) 1930 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) 1931 #endif /* AES */ 1932 1933 /** 1934 * @} 1935 */ 1936 1937 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable 1938 * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. 1939 * @note IOPORT clock gating in SLEEP mode can be used to further reduce 1940 * power consumption. 1941 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1942 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1943 * @{ 1944 */ 1945 1946 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1947 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1948 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1949 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1950 #if defined(GPIOE) 1951 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) 1952 #endif /* GPIOE */ 1953 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1954 1955 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1956 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1957 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1958 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1959 #if defined(GPIOE) 1960 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) 1961 #endif /* GPIOE */ 1962 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1963 /** 1964 * @} 1965 */ 1966 1967 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1968 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1969 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1970 * power consumption. 1971 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1972 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1973 * @{ 1974 */ 1975 #if defined(TIM2) 1976 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 1977 #endif /* TIM2 */ 1978 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1979 #if defined(TIM4) 1980 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) 1981 #endif /* TIM4 */ 1982 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) 1983 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) 1984 #if defined(CRS) 1985 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 1986 #endif /* CRS */ 1987 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1988 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1989 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 1990 #if defined(SPI3) 1991 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) 1992 #endif /* SPI3 */ 1993 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1994 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) 1995 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) 1996 #if defined(USART5) 1997 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) 1998 #endif /* USART5 */ 1999 #if defined(USART6) 2000 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) 2001 #endif /* USART6 */ 2002 #if defined(LPUART1) 2003 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) 2004 #endif /* LPUART1 */ 2005 #if defined(LPUART2) 2006 #define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) 2007 #endif /* LPUART2 */ 2008 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 2009 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 2010 #if defined(I2C3) 2011 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) 2012 #endif /* I2C3 */ 2013 #if defined(CEC) 2014 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) 2015 #endif /* CEC */ 2016 #if defined(UCPD1) 2017 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) 2018 #endif /* UCPD1 */ 2019 #if defined(UCPD2) 2020 #define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) 2021 #endif /* UCPD2 */ 2022 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 2023 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 2024 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 2025 #if defined(FDCAN1) || defined(FDCAN2) 2026 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) 2027 #endif /* FDCAN1 || FDCAN2 */ 2028 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 2029 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 2030 #if defined(DAC1) 2031 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) 2032 #endif /* DAC1 */ 2033 #if defined(LPTIM2) 2034 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) 2035 #endif /* LPTIM2 */ 2036 #if defined(LPTIM1) 2037 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) 2038 #endif /* LPTIM1 */ 2039 #if defined(TIM2) 2040 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) 2041 #endif /* TIM2 */ 2042 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 2043 #if defined(TIM4) 2044 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) 2045 #endif /* TIM4 */ 2046 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) 2047 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) 2048 #if defined(CRS) 2049 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) 2050 #endif /* CRS */ 2051 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 2052 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 2053 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) 2054 #if defined(SPI3) 2055 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) 2056 #endif /* TIM2 */ 2057 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 2058 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) 2059 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) 2060 #if defined(USART5) 2061 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) 2062 #endif /* USART5 */ 2063 #if defined(USART6) 2064 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) 2065 #endif /* USART6 */ 2066 #if defined(LPUART1) 2067 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) 2068 #endif /* LPUART1 */ 2069 #if defined(LPUART2) 2070 #define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) 2071 #endif /* LPUART2 */ 2072 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 2073 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) 2074 #if defined(I2C3) 2075 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) 2076 #endif /* I2C3 */ 2077 #if defined(CEC) 2078 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) 2079 #endif /* CEC */ 2080 #if defined(UCPD1) 2081 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) 2082 #endif /* UCPD1 */ 2083 #if defined(UCPD2) 2084 #define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) 2085 #endif /* UCPD2 */ 2086 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 2087 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) 2088 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 2089 #if defined(FDCAN1) || defined(FDCAN2) 2090 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) 2091 #endif /* FDCAN1) || FDCAN2 */ 2092 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 2093 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 2094 #if defined(DAC1) 2095 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) 2096 #endif /* DAC1 */ 2097 #if defined(LPTIM2) 2098 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) 2099 #endif /* LPTIM2 */ 2100 #if defined(LPTIM1) 2101 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) 2102 #endif /* LPTIM1 */ 2103 /** 2104 * @} 2105 */ 2106 2107 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2108 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2109 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2110 * power consumption. 2111 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2112 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2113 * @{ 2114 */ 2115 2116 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 2117 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 2118 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 2119 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 2120 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 2121 #if defined(TIM15) 2122 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) 2123 #endif /* TIM15 */ 2124 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 2125 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 2126 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 2127 2128 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 2129 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 2130 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 2131 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 2132 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 2133 #if defined(TIM15) 2134 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) 2135 #endif /* TIM15 */ 2136 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 2137 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 2138 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 2139 2140 /** 2141 * @} 2142 */ 2143 2144 /** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status 2145 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. 2146 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2147 * power consumption. 2148 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2149 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2150 * @{ 2151 */ 2152 2153 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) 2154 #if defined(DMA2) 2155 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET) 2156 #endif /* DMA2 */ 2157 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) 2158 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) 2159 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) 2160 #if defined(RNG) 2161 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET) 2162 #endif /* RNG */ 2163 #if defined(AES) 2164 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET) 2165 #endif /* AES */ 2166 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) 2167 #if defined(DMA2) 2168 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET) 2169 #endif /* DMA2 */ 2170 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) 2171 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) 2172 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) 2173 #if defined(RNG) 2174 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET) 2175 #endif /* RNG */ 2176 #if defined(AES) 2177 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET) 2178 #endif /* AES */ 2179 2180 /** 2181 * @} 2182 */ 2183 2184 /** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status 2185 * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. 2186 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2187 * power consumption. 2188 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2189 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2190 * @{ 2191 */ 2192 2193 2194 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) 2195 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) 2196 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) 2197 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) 2198 #if defined(GPIOE) 2199 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET) 2200 #endif /* GPIOE */ 2201 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) 2202 2203 2204 2205 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) 2206 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) 2207 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) 2208 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) 2209 #if defined(GPIOE) 2210 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET) 2211 #endif /* GPIOE */ 2212 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) 2213 2214 /** 2215 * @} 2216 */ 2217 2218 /** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2219 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2220 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2221 * power consumption. 2222 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2223 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2224 * @{ 2225 */ 2226 #if defined(TIM2) 2227 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET) 2228 #endif /* TIM2 */ 2229 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) 2230 #if defined(TIM4) 2231 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET) 2232 #endif /* TIM4 */ 2233 #if defined(TIM6) 2234 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET) 2235 #endif /* TIM6 */ 2236 #if defined(TIM7) 2237 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET) 2238 #endif /* TIM7 */ 2239 #if defined(CRS) 2240 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) 2241 #endif /* CRS */ 2242 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) 2243 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) 2244 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) 2245 #if defined(SPI3) 2246 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET) 2247 #endif /* SPI3 */ 2248 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) 2249 #if defined(USART3) 2250 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET) 2251 #endif /* USART3 */ 2252 #if defined(USART4) 2253 #define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET) 2254 #endif /* USART4 */ 2255 #if defined(USART5) 2256 #define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET) 2257 #endif /* USART5 */ 2258 #if defined(USART6) 2259 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET) 2260 #endif /* USART6 */ 2261 #if defined(LPUART1) 2262 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET) 2263 #endif /* LPUART1 */ 2264 #if defined(LPUART2) 2265 #define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET) 2266 #endif /* LPUART2 */ 2267 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) 2268 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) 2269 #if defined(I2C3) 2270 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET) 2271 #endif /* I2C3 */ 2272 #if defined(CEC) 2273 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET) 2274 #endif /* CEC */ 2275 #if defined(UCPD1) 2276 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET) 2277 #endif /* UCPD1 */ 2278 #if defined(UCPD2) 2279 #define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET) 2280 #endif /* UCPD2 */ 2281 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 2282 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) 2283 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 2284 #if defined(FDCAN1) || defined(FDCAN2) 2285 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET) 2286 #endif /* FDCAN1 || FDCAN2 */ 2287 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) 2288 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) 2289 #if defined(DAC1) 2290 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET) 2291 #endif /* DAC1 */ 2292 #if defined(LPTIM2) 2293 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET) 2294 #endif /* LPTIM2 */ 2295 #if defined(LPTIM1) 2296 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET) 2297 #endif /* LPTIM1 */ 2298 #if defined(TIM2) 2299 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET) 2300 #endif /* TIM2 */ 2301 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) 2302 #if defined(TIM4) 2303 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET) 2304 #endif /* TIM4 */ 2305 #if defined(TIM6) 2306 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET) 2307 #endif /* TIM6 */ 2308 #if defined(TIM7) 2309 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET) 2310 #endif /* TIM7 */ 2311 #if defined(CRS) 2312 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) 2313 #endif /* CRS */ 2314 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) 2315 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) 2316 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) 2317 #if defined(SPI3) 2318 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET) 2319 #endif /* SPI3 */ 2320 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) 2321 #if defined(USART3) 2322 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET) 2323 #endif /* USART3 */ 2324 #if defined(USART4) 2325 #define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET) 2326 #endif /* USART4 */ 2327 #if defined(USART5) 2328 #define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET) 2329 #endif /* USART5 */ 2330 #if defined(USART6) 2331 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET) 2332 #endif /* USART6 */ 2333 #if defined(LPUART1) 2334 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET) 2335 #endif /* LPUART1 */ 2336 #if defined(LPUART2) 2337 #define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET) 2338 #endif /* LPUART2 */ 2339 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) 2340 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) 2341 #if defined(I2C3) 2342 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET) 2343 #endif /* I2C3 */ 2344 #if defined(CEC) 2345 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET) 2346 #endif /* CEC */ 2347 #if defined(UCPD1) 2348 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET) 2349 #endif /* UCPD1 */ 2350 #if defined(UCPD2) 2351 #define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET) 2352 #endif /* UCPD2 */ 2353 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) 2354 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) 2355 #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ 2356 #if defined(FDCAN1) || defined(FDCAN2) 2357 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET) 2358 #endif /* FDCAN1 || FDCAN2 */ 2359 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) 2360 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) 2361 #if defined(DAC1) 2362 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET) 2363 #endif /* DAC1 */ 2364 #if defined(LPTIM2) 2365 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET) 2366 #endif /* LPTIM2 */ 2367 #if defined(LPTIM1) 2368 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET) 2369 #endif /* LPTIM1 */ 2370 2371 /** 2372 * @} 2373 */ 2374 2375 /** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2376 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2377 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2378 * power consumption. 2379 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2380 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2381 * @{ 2382 */ 2383 2384 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) 2385 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) 2386 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) 2387 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) 2388 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) 2389 #if defined(TIM15) 2390 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET) 2391 #endif /* TIM15 */ 2392 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) 2393 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) 2394 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) 2395 2396 2397 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) 2398 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) 2399 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) 2400 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) 2401 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) 2402 #if defined(TIM15) 2403 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET) 2404 #endif /* TIM15 */ 2405 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) 2406 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) 2407 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) 2408 2409 2410 /** 2411 * @} 2412 */ 2413 2414 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2415 * @{ 2416 */ 2417 2418 /** @brief Macros to force or release the Backup domain reset. 2419 * @note This function resets the RTC peripheral (including the backup registers) 2420 * and the RTC clock source selection in RCC_CSR register. 2421 * @note The BKPSRAM is not affected by this reset. 2422 * @retval None 2423 */ 2424 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2425 2426 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2427 2428 /** 2429 * @} 2430 */ 2431 2432 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2433 * @{ 2434 */ 2435 2436 /** @brief Macros to enable or disable the RTC clock. 2437 * @note As the RTC is in the Backup domain and write access is denied to 2438 * this domain after reset, you have to enable write access using 2439 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2440 * (to be done once after reset). 2441 * @note These macros must be used after the RTC clock source was selected. 2442 * @retval None 2443 */ 2444 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2445 2446 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2447 2448 /** 2449 * @} 2450 */ 2451 2452 /** @defgroup RCC_Clock_Configuration RCC Clock Configuration 2453 * @{ 2454 */ 2455 2456 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 2457 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2458 * It is used (enabled by hardware) as system clock source after startup 2459 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2460 * of the HSE used directly or indirectly as system clock (if the Clock 2461 * Security System CSS is enabled). 2462 * @note After enabling the HSI, the application software should wait on HSIRDY 2463 * flag to be set indicating that HSI clock is stable and can be used as 2464 * system clock source. 2465 * This parameter can be: ENABLE or DISABLE. 2466 * @retval None 2467 */ 2468 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 2469 2470 /** @brief Macros to disable the Internal High Speed oscillator (HSI). 2471 * @note HSI can not be stopped if it is used as system clock source. In this case, 2472 * you have to select another source of the system clock then stop the HSI. 2473 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2474 * clock cycles. 2475 * @retval None 2476 */ 2477 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 2478 2479 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2480 * @note The calibration is used to compensate for the variations in voltage 2481 * and temperature that influence the frequency of the internal HSI RC. 2482 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2483 * (default is RCC_HSICALIBRATION_DEFAULT). 2484 * This parameter must be a number between 0 and 127. 2485 * @retval None 2486 */ 2487 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2488 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 2489 2490 /** 2491 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2492 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2493 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2494 * speed because of the HSI startup time. 2495 * @note The enable of this function has not effect on the HSION bit. 2496 * This parameter can be: ENABLE or DISABLE. 2497 * @retval None 2498 */ 2499 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 2500 2501 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 2502 2503 /** @brief Macro to configure the HSISYS clock. 2504 * @param __HSIDIV__ specifies the HSI16 division factor. 2505 * This parameter can be one of the following values: 2506 * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 2507 * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 2508 * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 2509 * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 2510 * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 2511 * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 2512 * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 2513 * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 2514 */ 2515 #define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ 2516 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) 2517 2518 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2519 * @note After enabling the LSI, the application software should wait on 2520 * LSIRDY flag to be set indicating that LSI clock is stable and can 2521 * be used to clock the IWDG and/or the RTC. 2522 * @note LSI can not be disabled if the IWDG is running. 2523 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2524 * clock cycles. 2525 * @retval None 2526 */ 2527 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 2528 2529 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 2530 2531 /** 2532 * @brief Macro to configure the External High Speed oscillator (HSE). 2533 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2534 * supported by this macro. User should request a transition to HSE Off 2535 * first and then HSE On or HSE Bypass. 2536 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2537 * software should wait on HSERDY flag to be set indicating that HSE clock 2538 * is stable and can be used to clock the PLL and/or system clock. 2539 * @note HSE state can not be changed if it is used directly or through the 2540 * PLL as system clock. In this case, you have to select another source 2541 * of the system clock then change the HSE state (ex. disable it). 2542 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2543 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2544 * was previously enabled you have to enable it again after calling this 2545 * function. 2546 * @param __STATE__ specifies the new state of the HSE. 2547 * This parameter can be one of the following values: 2548 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2549 * 6 HSE oscillator clock cycles. 2550 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2551 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2552 * @retval None 2553 */ 2554 #define __HAL_RCC_HSE_CONFIG(__STATE__) do { \ 2555 if((__STATE__) == RCC_HSE_ON) \ 2556 { \ 2557 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2558 } \ 2559 else if((__STATE__) == RCC_HSE_BYPASS) \ 2560 { \ 2561 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2562 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2563 } \ 2564 else \ 2565 { \ 2566 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 2567 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2568 } \ 2569 } while(0U) 2570 2571 /** 2572 * @brief Macro to configure the External Low Speed oscillator (LSE). 2573 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2574 * supported by this macro. User should request a transition to LSE Off 2575 * first and then LSE On or LSE Bypass. 2576 * @note As the LSE is in the Backup domain and write access is denied to 2577 * this domain after reset, you have to enable write access using 2578 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2579 * (to be done once after reset). 2580 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2581 * software should wait on LSERDY flag to be set indicating that LSE clock 2582 * is stable and can be used to clock the RTC. 2583 * @param __STATE__ specifies the new state of the LSE. 2584 * This parameter can be one of the following values: 2585 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2586 * 6 LSE oscillator clock cycles. 2587 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2588 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2589 * @retval None 2590 */ 2591 #define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ 2592 if((__STATE__) == RCC_LSE_ON) \ 2593 { \ 2594 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2595 } \ 2596 else if((__STATE__) == RCC_LSE_BYPASS) \ 2597 { \ 2598 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2599 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2600 } \ 2601 else \ 2602 { \ 2603 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2604 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2605 } \ 2606 } while(0U) 2607 2608 #if defined(RCC_HSI48_SUPPORT) 2609 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2610 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2611 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2612 * flag to be set indicating that HSI48 clock is stable. 2613 * This parameter can be: ENABLE or DISABLE. 2614 * @retval None 2615 */ 2616 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 2617 2618 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 2619 2620 #endif /* RCC_HSI48_SUPPORT */ 2621 2622 /** 2623 * @} 2624 */ 2625 2626 /** @addtogroup RCC_RTC_Clock_Configuration 2627 * @{ 2628 */ 2629 2630 /** @brief Macros to configure the RTC clock (RTCCLK). 2631 * @note As the RTC clock configuration bits are in the Backup domain and write 2632 * access is denied to this domain after reset, you have to enable write 2633 * access using the Power Backup Access macro before to configure 2634 * the RTC clock source (to be done once after reset). 2635 * @note Once the RTC clock is configured it cannot be changed unless the 2636 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2637 * a Power On Reset (POR). 2638 * 2639 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2640 * This parameter can be one of the following values: 2641 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2642 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2643 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2644 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2645 * 2646 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2647 * work in STOP and STANDBY modes, and can be used as wakeup source. 2648 * However, when the HSE clock is used as RTC clock source, the RTC 2649 * cannot be used in STOP and STANDBY modes. 2650 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2651 * RTC clock source). 2652 * @retval None 2653 */ 2654 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 2655 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 2656 2657 2658 /** @brief Macro to get the RTC clock source. 2659 * @retval The returned value can be one of the following: 2660 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2661 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2662 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2663 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2664 */ 2665 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 2666 2667 /** @brief Macros to enable or disable the main PLL. 2668 * @note After enabling the main PLL, the application software should wait on 2669 * PLLRDY flag to be set indicating that PLL clock is stable and can 2670 * be used as system clock source. 2671 * @note The main PLL can not be disabled if it is used as system clock source 2672 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2673 * @retval None 2674 */ 2675 2676 /** 2677 * @} 2678 */ 2679 2680 /** @addtogroup RCC_Clock_Configuration 2681 * @{ 2682 */ 2683 2684 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 2685 2686 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 2687 2688 /** @brief Macro to configure the PLL clock source. 2689 * @note This function must be used only when the main PLL is disabled. 2690 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2691 * This parameter can be one of the following values: 2692 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2693 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2694 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2695 * @retval None 2696 * 2697 */ 2698 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 2699 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 2700 2701 /** @brief Macro to configure the PLL multiplication factor. 2702 * @note This function must be used only when the main PLL is disabled. 2703 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2704 * This parameter must be a value of RCC_PLLM_Clock_Divider. 2705 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2706 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 2707 * of 16 MHz to limit PLL jitter. 2708 * @retval None 2709 * 2710 */ 2711 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 2712 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 2713 2714 /** 2715 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 2716 * @note This function must be used only when the main PLL is disabled. 2717 * 2718 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2719 * This parameter can be one of the following values: 2720 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2721 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2722 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2723 * 2724 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 2725 * This parameter must be a value of RCC_PLLM_Clock_Divider. 2726 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2727 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 2728 * of 16 MHz to limit PLL jitter. 2729 * 2730 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 2731 * This parameter must be a number between 8 and 86. 2732 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2733 * output frequency is between 64 and 344 MHz. 2734 * 2735 * @param __PLLP__ specifies the division factor for ADC clock. 2736 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. 2737 * 2738 * @param __PLLQ__ specifies the division factor for RBG & HS Timers clocks.(1) 2739 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider 2740 * @note (1)__PLLQ__ parameter availability depends on devices 2741 * @note If the USB FS is used in your application, you have to set the 2742 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 2743 * the RNG needs a frequency lower than or equal to 48 MHz to work 2744 * correctly. 2745 * 2746 * @param __PLLR__ specifies the division factor for the main system clock. 2747 * This parameter must be a value of RCC_PLLR_Clock_Divider 2748 * @note You have to set the PLL parameters correctly to not exceed 64MHZ. 2749 * @retval None 2750 */ 2751 #if defined(RCC_PLLQ_SUPPORT) 2752 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 2753 MODIFY_REG(RCC->PLLCFGR, \ 2754 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 2755 RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ 2756 ((uint32_t) (__PLLSOURCE__) | \ 2757 (uint32_t) (__PLLM__) | \ 2758 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2759 (uint32_t) (__PLLP__) | \ 2760 (uint32_t) (__PLLQ__) | \ 2761 (uint32_t) (__PLLR__))) 2762 #else 2763 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \ 2764 MODIFY_REG(RCC->PLLCFGR, \ 2765 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 2766 RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \ 2767 ((uint32_t) (__PLLSOURCE__) | \ 2768 (uint32_t) (__PLLM__) | \ 2769 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2770 (uint32_t) (__PLLP__) | \ 2771 (uint32_t) (__PLLR__))) 2772 #endif /* RCC_PLLQ_SUPPORT */ 2773 /** @brief Macro to get the oscillator used as PLL clock source. 2774 * @retval The oscillator used as PLL clock source. The returned value can be one 2775 * of the following: 2776 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 2777 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 2778 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 2779 */ 2780 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 2781 2782 /** 2783 * @brief Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) 2784 * @note Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime 2785 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot 2786 * be stopped if used as System Clock. 2787 * @note (*) RCC_PLLQCLK availability depends on devices 2788 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2789 * This parameter can be one or a combination of the following values: 2790 * @arg @ref RCC_PLLPCLK This clock is used to generate the clock for the ADC. 2791 * @if defined(STM32G081xx) 2792 * @arg @ref RCC_PLLQCLK This Clock is used to generate the clock for the High Speed Timers, 2793 * and the random analog generator (<=48 MHz). 2794 * @endif 2795 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) 2796 * @retval None 2797 */ 2798 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2799 2800 /** 2801 * @brief Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) 2802 * @note Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime 2803 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot 2804 * be stopped if used as System Clock. 2805 * @note (*) RCC_PLLQCLK availability depends on devices 2806 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2807 * This parameter can be one or a combination of the following values: 2808 * @arg @ref RCC_PLLPCLK This clock may be used to generate the clock for the ADC, I2S1. 2809 * @if defined(STM32G081xx) 2810 * @arg @ref RCC_PLLQCLK This Clock may be used to generate the clock for the High Speed Timers, 2811 * and RNG (<=48 MHz). 2812 * @endif 2813 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) 2814 * @retval None 2815 */ 2816 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2817 2818 /** 2819 * @brief Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) 2820 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 2821 * This parameter can be one of the following values: 2822 * @arg RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1. 2823 * @if defined(STM32G081xx) 2824 * @arg RCC_PLLQCLK This Clock may be used to generate the clock for the HS Timers, 2825 * the RNG (<=48 MHz). 2826 * @endif 2827 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) 2828 * @retval SET / RESET 2829 * @note (*) RCC_PLLQCLK availability depends on devices 2830 */ 2831 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2832 2833 /** 2834 * @brief Macro to configure the system clock source. 2835 * @param __SYSCLKSOURCE__ specifies the system clock source. 2836 * This parameter can be one of the following values: 2837 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 2838 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 2839 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 2840 * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. 2841 * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. 2842 * @retval None 2843 */ 2844 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 2845 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 2846 2847 /** @brief Macro to get the clock source used as system clock. 2848 * @retval The clock source used as system clock. The returned value can be one 2849 * of the following: 2850 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 2851 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 2852 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 2853 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. 2854 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. 2855 */ 2856 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 2857 2858 /** 2859 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 2860 * @note As the LSE is in the Backup domain and write access is denied to 2861 * this domain after reset, you have to enable write access using 2862 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2863 * (to be done once after reset). 2864 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 2865 * This parameter can be one of the following values: 2866 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 2867 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 2868 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 2869 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 2870 * @retval None 2871 */ 2872 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 2873 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 2874 2875 /** @brief Macro to configure the Microcontroller output clock. 2876 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2877 * This parameter can be one of the following values: 2878 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 2879 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 2880 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 2881 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 2882 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 2883 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 2884 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 2885 * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source 2886 * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source 2887 * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source 2888 * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source 2889 @if STM32G0C1xx 2890 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 2891 @endif 2892 * @param __MCODIV__ specifies the MCO clock prescaler. 2893 * This parameter can be one of the following values: 2894 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 2895 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 2896 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 2897 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 2898 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 2899 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 2900 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 2901 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 2902 @if STM32G0C1xx 2903 * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256 2904 * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512 2905 * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024 2906 @endif 2907 */ 2908 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 2909 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 2910 2911 #if defined(RCC_MCO2_SUPPORT) 2912 /** @brief Macro to configure the Microcontroller output clock 2. 2913 * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. 2914 * This parameter can be one of the following values: 2915 * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled 2916 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source 2917 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source 2918 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee 2919 * @arg @ref RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source 2920 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source 2921 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source 2922 * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source 2923 * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source 2924 * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source 2925 * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source 2926 @if STM32G0C1xx 2927 * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48 2928 @endif 2929 * @param __MCODIV__ specifies the MCO clock prescaler. 2930 * This parameter can be one of the following values: 2931 * @arg @ref RCC_MCO2DIV_1 MCO2 clock source is divided by 1 2932 * @arg @ref RCC_MCO2DIV_2 MCO2 clock source is divided by 2 2933 * @arg @ref RCC_MCO2DIV_4 MCO2 clock source is divided by 4 2934 * @arg @ref RCC_MCO2DIV_8 MCO2 clock source is divided by 8 2935 * @arg @ref RCC_MCO2DIV_16 MCO2 clock source is divided by 16 2936 * @arg @ref RCC_MCO2DIV_32 MCO2 clock source is divided by 32 2937 * @arg @ref RCC_MCO2DIV_64 MCO2 clock source is divided by 64 2938 * @arg @ref RCC_MCO2DIV_128 MCO2 clock source is divided by 128 2939 * @arg @ref RCC_MCO2DIV_256 MCO2 clock source is divided by 256 2940 * @arg @ref RCC_MCO2DIV_512 MCO2 clock source is divided by 512 2941 * @arg @ref RCC_MCO2DIV_1024 MCO2 clock source is divided by 1024 2942 */ 2943 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 2944 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 2945 #endif /* RCC_MCO2_SUPPORT */ 2946 2947 /** 2948 * @} 2949 */ 2950 2951 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 2952 * @brief macros to manage the specified RCC Flags and interrupts. 2953 * @{ 2954 */ 2955 2956 /** @brief Enable RCC interrupt. 2957 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 2958 * This parameter can be any combination of the following values: 2959 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2960 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2961 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2962 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2963 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 2964 @if STM32G0C1xx 2965 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 2966 @endif 2967 * @retval None 2968 */ 2969 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 2970 2971 /** @brief Disable RCC interrupt. 2972 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 2973 * This parameter can be any combination of the following values: 2974 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2975 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2976 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2977 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2978 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 2979 @if STM32G0C1xx 2980 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 2981 @endif 2982 * @retval None 2983 */ 2984 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 2985 2986 /** @brief Clear RCC interrupt pending bits. 2987 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2988 * This parameter can be any combination of the following values: 2989 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 2990 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 2991 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 2992 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 2993 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 2994 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 2995 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 2996 @if STM32G0C1xx 2997 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 2998 @endif 2999 * @retval None 3000 */ 3001 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 3002 3003 /** @brief Check whether the RCC interrupt has occurred or not. 3004 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3005 * This parameter can be one of the following values: 3006 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3007 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3008 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3009 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3010 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3011 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3012 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 3013 @if STM32G0C1xx 3014 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3015 @endif 3016 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3017 */ 3018 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3019 3020 /** @brief Set RMVF bit to clear the reset flags. 3021 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, 3022 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3023 * @retval None 3024 */ 3025 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 3026 3027 /** @brief Check whether the selected RCC flag is set or not. 3028 * @param __FLAG__ specifies the flag to check. 3029 * This parameter can be one of the following values: 3030 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3031 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3032 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3033 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3034 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3035 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3036 @if STM32G0C1xx 3037 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3038 @endif 3039 * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset 3040 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3041 * @arg @ref RCC_FLAG_PINRST Pin reset 3042 * @arg @ref RCC_FLAG_SFTRST Software reset 3043 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3044 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3045 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3046 * @retval The new state of __FLAG__ (TRUE or FALSE). 3047 */ 3048 #if defined(RCC_HSI48_SUPPORT) 3049 #define __HAL_RCC_GET_FLAG(__FLAG__) \ 3050 (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3051 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3052 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3053 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3054 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) 3055 #else 3056 #define __HAL_RCC_GET_FLAG(__FLAG__) \ 3057 (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3058 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3059 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ 3060 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) 3061 #endif /* RCC_HSI48_SUPPORT */ 3062 3063 /** 3064 * @} 3065 */ 3066 3067 /** 3068 * @} 3069 */ 3070 3071 /* Include RCC HAL Extended module */ 3072 #include "stm32g0xx_hal_rcc_ex.h" 3073 3074 /* Exported functions --------------------------------------------------------*/ 3075 /** @addtogroup RCC_Exported_Functions 3076 * @{ 3077 */ 3078 3079 3080 /** @addtogroup RCC_Exported_Functions_Group1 3081 * @{ 3082 */ 3083 3084 /* Initialization and de-initialization functions ******************************/ 3085 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3086 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3087 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3088 3089 /** 3090 * @} 3091 */ 3092 3093 /** @addtogroup RCC_Exported_Functions_Group2 3094 * @{ 3095 */ 3096 3097 /* Peripheral Control functions ************************************************/ 3098 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3099 void HAL_RCC_EnableCSS(void); 3100 void HAL_RCC_EnableLSECSS(void); 3101 void HAL_RCC_DisableLSECSS(void); 3102 uint32_t HAL_RCC_GetSysClockFreq(void); 3103 uint32_t HAL_RCC_GetHCLKFreq(void); 3104 uint32_t HAL_RCC_GetPCLK1Freq(void); 3105 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3106 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3107 uint32_t HAL_RCC_GetResetSource(void); 3108 /* LSE & HSE CSS NMI IRQ handler */ 3109 void HAL_RCC_NMI_IRQHandler(void); 3110 /* User Callbacks in non blocking mode (IT mode) */ 3111 void HAL_RCC_CSSCallback(void); 3112 void HAL_RCC_LSECSSCallback(void); 3113 3114 /** 3115 * @} 3116 */ 3117 3118 /** 3119 * @} 3120 */ 3121 3122 /** 3123 * @} 3124 */ 3125 3126 /** 3127 * @} 3128 */ 3129 3130 #ifdef __cplusplus 3131 } 3132 #endif 3133 3134 #endif /* STM32G0xx_HAL_RCC_H */ 3135 3136
