1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2021 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### RCC specific features #####
25 ==============================================================================
26 [..]
27 After reset the device is running from Multiple Speed Internal oscillator
28 (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
29 and I-Cache are disabled, and all peripherals are off except internal
30 SRAM, Flash and JTAG.
31
32 (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
33 all peripherals mapped on these busses are running at MSI speed.
34 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
35 (+) All GPIOs are in analog mode, except the JTAG pins which
36 are assigned to be used for debug purpose.
37
38 [..]
39 Once the device started from reset, the user application has to:
40 (+) Configure the clock source to be used to drive the System clock
41 (if the application needs higher frequency/performance)
42 (+) Configure the System clock frequency and Flash settings
43 (+) Configure the AHB and APB busses prescalers
44 (+) Enable the clock for the peripheral(s) to be used
45 (+) Configure the clock source(s) for peripherals which clocks are not
46 derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG)
47
48 @endverbatim
49 ******************************************************************************
50 */
51
52 /* Includes ------------------------------------------------------------------*/
53 #include "stm32u5xx_hal.h"
54
55 /** @addtogroup STM32U5xx_HAL_Driver
56 * @{
57 */
58
59 /** @defgroup RCC RCC
60 * @brief RCC HAL module driver
61 * @{
62 */
63
64 #ifdef HAL_RCC_MODULE_ENABLED
65
66 /* Private typedef -----------------------------------------------------------*/
67 /* Private constants ---------------------------------------------------------*/
68 /** @defgroup RCC_Private_Constants RCC Private Constants
69 * @{
70 */
71 #define PLLDIVR_RESET_VALUE (0x01010280U)
72 #define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */
73 /**
74 * @}
75 */
76 /* Private macros ------------------------------------------------------------*/
77 /** @addtogroup RCC_Private_Macros
78 * @{
79 */
80 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
81 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
82
83 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
84 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL))
85
86 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
87 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \
88 ((__LSE__) == RCC_LSE_BYPASS))
89
90 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
91
92 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >>\
93 RCC_ICSCR3_HSITRIM_Pos))
94
95 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
96
97 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
98
99 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
100
101 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
102
103 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
104
105 #define IS_RCC_SHSI(__SHSI__) (((__SHSI__) == RCC_SHSI_OFF) || ((__SHSI__) == RCC_SHSI_ON))
106
107 #define IS_RCC_MSIK(__MSIK__) (((__MSIK__) == RCC_MSIK_OFF) || ((__MSIK__) == RCC_MSIK_ON))
108
109 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
110 ((PLL) == RCC_PLL_ON))
111
112 #define IS_RCC_PLLMBOOST_VALUE(VALUE) (((VALUE) == RCC_PLLMBOOST_DIV1) || \
113 ((VALUE) == RCC_PLLMBOOST_DIV2) || \
114 ((VALUE) == RCC_PLLMBOOST_DIV4) || \
115 ((VALUE) == RCC_PLLMBOOST_DIV6) || \
116 ((VALUE) == RCC_PLLMBOOST_DIV8) || \
117 ((VALUE) == RCC_PLLMBOOST_DIV10) || \
118 ((VALUE) == RCC_PLLMBOOST_DIV12) || \
119 ((VALUE) == RCC_PLLMBOOST_DIV14) || \
120 ((VALUE) == RCC_PLLMBOOST_DIV16))
121
122 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
123 ((VALUE) == RCC_PLL1_DIVQ) || \
124 ((VALUE) == RCC_PLL1_DIVR))
125
126 #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \
127 ((VALUE) == RCC_PLLVCIRANGE_1))
128
129 #define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U)
130
131 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU))
132
133 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
134 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
135 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
136 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
137
138 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
139 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
140 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
141 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
142 ((__HCLK__) == RCC_SYSCLK_DIV512))
143
144 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
145 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
146 ((__PCLK__) == RCC_HCLK_DIV16))
147
148 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
149
150 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
151 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
152 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
153 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
154 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
155 ((__SOURCE__) == RCC_MCO1SOURCE_PLL1CLK) || \
156 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
157 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
158 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)|| \
159 ((__SOURCE__) == RCC_MCO1SOURCE_MSIK))
160
161 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
162 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
163 ((__DIV__) == RCC_MCODIV_16))
164
165 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
166 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
167 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
168 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
169
170 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((0U < (ITEM)) && ((ITEM) <= 0x1FFFU))
171
172 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
173 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \
174 ((ATTRIBUTES) == RCC_SEC_NPRIV) || \
175 ((ATTRIBUTES) == RCC_NSEC_PRIV) || \
176 ((ATTRIBUTES) == RCC_NSEC_NPRIV))
177 #else
178 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV))
179 #endif /* __ARM_FEATURE_CMSE */
180 /**
181 * @}
182 */
183
184 /* Private define ------------------------------------------------------------*/
185 /** @defgroup RCC_Private_Constants RCC Private Constants
186 * @{
187 */
188 #define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when
189 LSI prediv is used) */
190 #define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
191 #define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
192 #define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
193 #define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
194 #define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */
195 #define EPOD_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
196 /**
197 * @}
198 */
199
200 /* Private macro -------------------------------------------------------------*/
201 /** @defgroup RCC_Private_Macros RCC Private Macros
202 * @{
203 */
204
205 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
206
207 #define MCO1_GPIO_PORT GPIOA
208
209 #define MCO1_PIN GPIO_PIN_8
210
211 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
212 (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
213 /**
214 * @}
215 */
216
217 /* Private variables ---------------------------------------------------------*/
218
219 /* Private function prototypes -----------------------------------------------*/
220 /** @defgroup RCC_Private_Functions RCC Private Functions
221 * @{
222 */
223 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
224 /**
225 * @}
226 */
227
228 /* Exported functions --------------------------------------------------------*/
229
230 /** @defgroup RCC_Exported_Functions RCC Exported Functions
231 * @{
232 */
233
234 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
235 * @brief Initialization and Configuration functions
236 *
237 @verbatim
238 ===============================================================================
239 ##### Initialization and de-initialization functions #####
240 ===============================================================================
241 [..]
242 This section provides functions allowing to configure the internal and external oscillators
243 (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
244 and APB2).
245
246 [..] Internal/external clock and PLL configuration
247 (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
248 the PLL as System clock source.
249
250 (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
251 It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz).
252 The number of flash wait states is automatically adjusted when MSI range is updated with
253 HAL_RCC_OscConfig() and the MSI is used as System clock source.
254
255 (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
256 clock source.
257
258 (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
259 through the PLL as System clock source. Can be used also optionally as RTC clock source.
260
261 (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
262
263 (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
264 (++) The first output is used to generate the high speed system clock (up to 80MHz).
265 (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz),
266 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
267 (++) The third output is used to generate an accurate clock to achieve
268 high-quality audio performance on SAI interface.
269
270 (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
271 (++) The first output is used to generate SAR ADC1 clock.
272 (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz),
273 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
274 (++) The Third output is used to generate an accurate clock to achieve
275 high-quality audio performance on SAI interface.
276
277 (+) PLL3 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
278 (++) The first output is used to generate SAR ADC4 clock.
279 (++) The second output is used to generate an accurate clock to achieve
280 high-quality audio performance on SAI interface.
281
282 (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
283 (HSE used directly or through PLL as System clock source), the System clock
284 is automatically switched to HSI and an interrupt is generated if enabled.
285 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
286 exception vector.
287
288 (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
289 main PLL clock (through a configurable prescaler) on PA8 pin.
290
291 [..] System, AHB and APB busses clocks configuration
292 (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
293 HSE and main PLL.
294 The AHB clock (HCLK) is derived from System clock through configurable
295 prescaler and used to clock the CPU, memory and peripherals mapped
296 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
297 from AHB clock through configurable prescalers and used to clock
298 the peripherals mapped on these busses. You can use
299 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
300
301 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
302
303 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLL2) or (PLL3) or
304 from an external clock mapped on the SAI_CKIN pin.
305 You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
306 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
307 divided by 2 to 31.
308 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
309 to configure this clock.
310 (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz
311 to work correctly, while the SDMMC1 and RNG peripherals require a frequency
312 equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2
313 through PLLQ divider. You have to enable the peripheral clock and use
314 HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
315 (+@) IWDG clock which is always the LSI clock.
316
317
318 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
319 The clock source frequency should be adapted depending on the device voltage range
320 as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
321
322 @endverbatim
323
324
325 Table 1. HCLK clock frequency for STM32U5xx devices
326 +-------------------------------------------------------+----------------------------------------+
327 | Latency | HCLK clock frequency (MHz) 0.9V-1.2V |
328 | |-------------------------------------|---------------------+------------------|
329 | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 |
330 | | 1.1 V - 1.2V | 1.0 V - 1.1V | 0.9 V - 1.0V | 0.9V |
331 |-----------------|------------------|------------------|---------------------|------------------|
332 |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5 | 0 < HCLK <= 8 |
333 |-----------------|------------------|------------------|---------------------|------------------|
334 |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25 | 8 < HCLK <= 16 |
335 |-----------------|------------------|------------------|---------------------|------------------|
336 |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5 | 16 < HCLK <= 24 |
337 |-----------------|------------------|------------------|---------------------|------------------|
338 |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100 | 37.5 < HCLK <= 50 | - |
339 |-----------------|------------------|------------------|---------------------|------------------|
340 |4WS(5 CPU cycles)|128 < HCLK <= 160 | - | - | - |
341 +-----------------+------------------+------------------+---------------------+------------------+
342 * @{
343 */
344
345 /**
346 * @brief Reset the RCC clock configuration to the default reset state.
347 * @note The default reset state of the clock configuration is given below:
348 * - MSI ON and used as system clock source
349 * - HSE, HSI, PLL, PLL2 and PLLISAI2 OFF
350 * - AHB, APB1 and APB2 prescaler set to 1
351 * - CSS, MCO1 OFF
352 * - All interrupts disabled
353 * - All interrupt and reset flags cleared
354 * @note This function doesn't modify the configuration of the
355 * - Peripheral clocks
356 * - LSI, LSE and RTC clocks
357 * @retval HAL status
358 */
359
HAL_RCC_DeInit(void)360 HAL_StatusTypeDef HAL_RCC_DeInit(void)
361 {
362 uint32_t tickstart;
363
364 /* Increasing the CPU frequency */
365 if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY())
366 {
367 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
368 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
369
370 /* Check that the new number of wait states is taken into account to access the Flash
371 memory by reading the FLASH_ACR register */
372 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
373 {
374 return HAL_ERROR;
375 }
376
377 }
378
379 tickstart = HAL_GetTick();
380
381 /* Set MSION bit */
382 SET_BIT(RCC->CR, RCC_CR_MSISON);
383
384 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
385 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
386 {
387 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
388 {
389 return HAL_TIMEOUT;
390 }
391 }
392
393 /* Set MSIRANGE default value */
394 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4);
395
396 /* Set MSITRIM default value */
397 WRITE_REG(RCC->ICSCR2, 0x00084210U);
398
399 /* Set MSIKRANGE default value */
400 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4);
401
402 /* Set MSIRGSEL default value */
403 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U);
404
405 tickstart = HAL_GetTick();
406
407 /* Reset CFGR register (MSI is selected as system clock source) */
408 CLEAR_REG(RCC->CFGR1);
409 CLEAR_REG(RCC->CFGR2);
410
411 /* Wait till clock switch is ready */
412 while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U)
413 {
414 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
415 {
416 return HAL_TIMEOUT;
417 }
418 }
419
420 /* Reset MSIKON, HSECSSON , HSEON, HSEBYP, HSION, HSIKERON, PLL1ON, PLL2ON, PLL3ON bits */
421 CLEAR_BIT(RCC->CR, RCC_CR_MSIKON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST | RCC_CR_MSIKERON | RCC_CR_CSSON | \
422 RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON | RCC_CR_HSI48ON | \
423 RCC_CR_HSEON | RCC_CR_SHSION);
424
425 /* Reset HSEBYP & HSEEXT bits */
426 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP | RCC_CR_HSEEXT);
427
428 tickstart = HAL_GetTick();
429
430 /* Clear PLL1ON bit */
431 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
432
433 /* Wait till PLL1 is disabled */
434 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
435 {
436 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
437 {
438 return HAL_TIMEOUT;
439 }
440 }
441
442 tickstart = HAL_GetTick();
443
444 /* Reset PLL2N bit */
445 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
446
447 /* Wait till PLL2 is disabled */
448 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
449 {
450 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
451 {
452 return HAL_TIMEOUT;
453 }
454 }
455
456 tickstart = HAL_GetTick();
457
458 /* Reset PLL3 bit */
459 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
460
461 /* Wait till PLL3 is disabled */
462 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
463 {
464 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
465 {
466 return HAL_TIMEOUT;
467 }
468 }
469
470 /* Reset PLL1CFGR register */
471 CLEAR_REG(RCC->PLL1CFGR);
472
473 /* Reset PLL1DIVR register */
474 WRITE_REG(RCC->PLL1DIVR, PLLDIVR_RESET_VALUE);
475
476 /* Reset PLL1FRACR register */
477 CLEAR_REG(RCC->PLL1FRACR);
478
479 /* Reset PLL2CFGR register */
480 CLEAR_REG(RCC->PLL2CFGR);
481
482 /* Reset PLL2DIVR register */
483 WRITE_REG(RCC->PLL2DIVR, PLLDIVR_RESET_VALUE);
484
485 /* Reset PLL2FRACR register */
486 CLEAR_REG(RCC->PLL2FRACR);
487
488 /* Reset PLL3CFGR register */
489 CLEAR_REG(RCC->PLL3CFGR);
490
491 /* Reset PLL3DIVR register */
492 WRITE_REG(RCC->PLL3DIVR, PLLDIVR_RESET_VALUE);
493
494 /* Reset PLL3FRACR register */
495 CLEAR_REG(RCC->PLL3FRACR);
496
497 /* Disable all interrupts */
498 CLEAR_REG(RCC->CIER);
499
500 /* Clear all interrupts flags */
501 WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
502
503 /* Reset all CSR flags */
504 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
505
506 /* Update the SystemCoreClock global variable */
507 SystemCoreClock = MSI_VALUE;
508
509 /* Decreasing the number of wait states because of lower CPU frequency */
510 if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY())
511 {
512 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
513 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
514
515 /* Check that the new number of wait states is taken into account to access the Flash
516 memory by reading the FLASH_ACR register */
517 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
518 {
519 return HAL_ERROR;
520 }
521 }
522
523 /* Adapt Systick interrupt period */
524 return (HAL_InitTick(TICK_INT_PRIORITY));
525
526 }
527
528 /**
529 * @brief Initialize the RCC Oscillators according to the specified parameters in the
530 * RCC_OscInitTypeDef.
531 * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
532 * contains the configuration information for the RCC Oscillators.
533 * @note The PLL is not disabled when used as system clock.
534 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
535 * supported by this function. User should request a transition to LSE Off
536 * first and then LSE On or LSE Bypass.
537 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
538 * supported by this function. User should request a transition to HSE Off
539 * first and then HSE On or HSE Bypass.
540 * @retval HAL status
541 */
HAL_RCC_OscConfig(const RCC_OscInitTypeDef * pRCC_OscInitStruct)542 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct)
543 {
544 uint32_t tickstart;
545 HAL_StatusTypeDef status;
546 uint32_t sysclk_source;
547 uint32_t pll_config;
548 FlagStatus pwrboosten = RESET;
549 uint32_t temp1_pllckcfg;
550 uint32_t temp2_pllckcfg;
551
552 /* Check Null pointer */
553 if (pRCC_OscInitStruct == NULL)
554 {
555 return HAL_ERROR;
556 }
557
558 /* Check the parameters */
559 assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType));
560
561 sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
562 pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
563
564 /*----------------------------- MSI Configuration --------------------------*/
565 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
566 {
567 /* Check the parameters */
568 assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState));
569 assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
570 assert_param(IS_RCC_MSI_CLOCK_RANGE(pRCC_OscInitStruct->MSIClockRange));
571
572 /*Check if MSI is used as system clock or as PLL source when PLL is selected as system clock*/
573
574 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
575 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
576 {
577 if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF)
578 {
579 return HAL_ERROR;
580 }
581
582 /* Otherwise, just the calibration and MSI range change are allowed */
583 else
584 {
585 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
586 must be correctly programmed according to the frequency of the CPU clock
587 (HCLK) and the supply voltage of the device */
588 if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
589 {
590 /* Decrease number of wait states update if necessary */
591 /* Only possible when MSI is the System clock source */
592 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
593 {
594 if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
595 {
596 return HAL_ERROR;
597 }
598 }
599
600 /* Selects the Multiple Speed oscillator (MSI) clock range */
601 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
602 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
603 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
604 (pRCC_OscInitStruct->MSIClockRange));
605 }
606 else
607 {
608 /* Else, keep current flash latency while decreasing applies */
609 /* Selects the Multiple Speed oscillator (MSI) clock range */
610 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
611 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
612 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
613 (pRCC_OscInitStruct->MSIClockRange));
614
615 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
616 {
617 if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
618 {
619 return HAL_ERROR;
620 }
621 }
622 }
623
624 /* Update the SystemCoreClock global variable */
625 (void) HAL_RCC_GetHCLKFreq();
626 /* Configure the source of time base considering new system clocks settings*/
627 status = HAL_InitTick(uwTickPrio);
628 if (status != HAL_OK)
629 {
630 return status;
631 }
632 }
633 }
634 else
635 {
636 /* Check the MSI State */
637 if (pRCC_OscInitStruct->MSIState != RCC_MSI_OFF)
638 {
639 /* Enable the Internal High Speed oscillator (MSI) */
640 __HAL_RCC_MSI_ENABLE();
641
642 tickstart = HAL_GetTick();
643
644 /* Wait till MSI is ready */
645 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
646 {
647 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
648 {
649 return HAL_TIMEOUT;
650 }
651 }
652 /* Selects the Multiple Speed oscillator (MSI) clock range */
653 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
654 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
655 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
656 (pRCC_OscInitStruct->MSIClockRange));
657
658 }
659 else
660 {
661 /* Disable the Internal High Speed oscillator (MSI) */
662 __HAL_RCC_MSI_DISABLE();
663
664 tickstart = HAL_GetTick();
665
666 /* Wait till MSI is ready */
667 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U)
668 {
669 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
670 {
671 return HAL_TIMEOUT;
672 }
673 }
674 }
675 }
676 }
677 /*------------------------------- HSE Configuration ------------------------*/
678 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
679 {
680 /* Check the parameters */
681 assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState));
682
683 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
684 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
685 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
686 {
687 if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF)
688 {
689 return HAL_ERROR;
690 }
691 }
692 else
693 {
694 /* Set the new HSE configuration ---------------------------------------*/
695 __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState);
696
697 /* Check the HSE State */
698 if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF)
699 {
700 tickstart = HAL_GetTick();
701
702 /* Wait till HSE is ready */
703 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
704 {
705 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
706 {
707 return HAL_TIMEOUT;
708 }
709 }
710 }
711 else
712 {
713 tickstart = HAL_GetTick();
714
715 /* Wait till HSE is disabled */
716 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
717 {
718 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
719 {
720 return HAL_TIMEOUT;
721 }
722 }
723 }
724 }
725 }
726 /*----------------------------- HSI Configuration --------------------------*/
727 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
728 {
729 /* Check the parameters */
730 assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState));
731 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue));
732
733 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
734 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
735 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
736 {
737 /* When HSI is used as system clock it will not be disabled */
738 if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF)
739 {
740 return HAL_ERROR;
741 }
742 /* Otherwise, just the calibration is allowed */
743 else
744 {
745 /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
746 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
747 }
748 }
749 else
750 {
751 /* Check the HSI State */
752 if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF)
753 {
754 /* Enable the Internal High Speed oscillator (HSI) */
755 __HAL_RCC_HSI_ENABLE();
756
757 tickstart = HAL_GetTick();
758
759 /* Wait till HSI is ready */
760 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
761 {
762 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
763 {
764 return HAL_TIMEOUT;
765 }
766 }
767
768 /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
769 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
770 }
771 else
772 {
773 /* Disable the Internal High Speed oscillator (HSI) */
774 __HAL_RCC_HSI_DISABLE();
775
776 tickstart = HAL_GetTick();
777
778 /* Wait till HSI is disabled */
779 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
780 {
781 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
782 {
783 return HAL_TIMEOUT;
784 }
785 }
786 }
787 }
788 }
789 /*------------------------------ LSI Configuration -------------------------*/
790 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
791 {
792 /* Check the parameters */
793 assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState));
794
795 FlagStatus pwrclkchanged = RESET;
796
797 /* Update LSI configuration in Backup Domain control register */
798 /* Requires to enable write access to Backup Domain of necessary */
799 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800 {
801 __HAL_RCC_PWR_CLK_ENABLE();
802 pwrclkchanged = SET;
803 }
804
805 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
806 {
807 /* Enable write access to Backup domain */
808 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
809
810 /* Wait for Backup domain Write protection disable */
811 tickstart = HAL_GetTick();
812
813 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
814 {
815 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
816 {
817 return HAL_TIMEOUT;
818 }
819 }
820 }
821 /* Check the LSI State */
822 if (pRCC_OscInitStruct->LSIState != RCC_LSI_OFF)
823 {
824 uint32_t bdcr_temp = RCC->BDCR;
825
826 /* Check LSI division factor */
827 assert_param(IS_RCC_LSIDIV(pRCC_OscInitStruct->LSIDiv));
828
829 if (pRCC_OscInitStruct->LSIDiv != (bdcr_temp & RCC_BDCR_LSIPREDIV))
830 {
831 if (((bdcr_temp & RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) && \
832 ((bdcr_temp & RCC_BDCR_LSION) != RCC_BDCR_LSION))
833 {
834 /* If LSIRDY is set while LSION is not enabled, LSIPREDIV can't be updated */
835 /* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC */
836 return HAL_ERROR;
837 }
838
839 /* Turn off LSI before changing RCC_BDCR_LSIPREDIV */
840 if ((bdcr_temp & RCC_BDCR_LSION) == RCC_BDCR_LSION)
841 {
842 __HAL_RCC_LSI_DISABLE();
843
844 tickstart = HAL_GetTick();
845
846 /* Wait till LSI is disabled */
847 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
848 {
849 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
850 {
851 return HAL_TIMEOUT;
852 }
853 }
854 }
855
856 /* Set LSI division factor */
857 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, pRCC_OscInitStruct->LSIDiv);
858 }
859
860 /* Enable the Internal Low Speed oscillator (LSI) */
861 __HAL_RCC_LSI_ENABLE();
862
863 tickstart = HAL_GetTick();
864
865 /* Wait till LSI is ready */
866 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U)
867 {
868 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
869 {
870 return HAL_TIMEOUT;
871 }
872 }
873 }
874 else
875 {
876 /* Disable the Internal Low Speed oscillator (LSI) */
877 __HAL_RCC_LSI_DISABLE();
878
879 tickstart = HAL_GetTick();
880
881 /* Wait till LSI is disabled */
882 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
883 {
884 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
885 {
886 return HAL_TIMEOUT;
887 }
888 }
889 }
890 /* Restore clock configuration if changed */
891 if (pwrclkchanged == SET)
892 {
893 __HAL_RCC_PWR_CLK_DISABLE();
894 }
895 }
896 /*------------------------------ LSE Configuration -------------------------*/
897 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
898 {
899 FlagStatus pwrclkchanged = RESET;
900
901 /* Check the parameters */
902 assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState));
903
904 /* Update LSE configuration in Backup Domain control register */
905 /* Requires to enable write access to Backup Domain of necessary */
906 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
907 {
908 __HAL_RCC_PWR_CLK_ENABLE();
909 pwrclkchanged = SET;
910 }
911
912 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
913 {
914 /* Enable write access to Backup domain */
915 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
916
917 /* Wait for Backup domain Write protection disable */
918 tickstart = HAL_GetTick();
919
920 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
921 {
922 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
923 {
924 return HAL_TIMEOUT;
925 }
926 }
927 }
928
929 /* Set the new LSE configuration -----------------------------------------*/
930 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)
931 {
932 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)
933 {
934 /* LSE oscillator bypass enable */
935 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
936 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
937 }
938 else
939 {
940 /* LSE oscillator enable */
941 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
942 }
943 }
944 else
945 {
946 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
947 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
948 }
949
950 /* Check the LSE State */
951 if (pRCC_OscInitStruct->LSEState != RCC_LSE_OFF)
952 {
953 tickstart = HAL_GetTick();
954
955 /* Wait till LSE is ready */
956 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
957 {
958 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
959 {
960 return HAL_TIMEOUT;
961 }
962 }
963
964 /* Enable LSESYS additionally if requested */
965 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U)
966 {
967 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
968
969 /* Wait till LSESYS is ready */
970 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
971 {
972 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
973 {
974 return HAL_TIMEOUT;
975 }
976 }
977 }
978 else
979 {
980 /* Make sure LSESYSEN/LSESYSRDY are reset */
981 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
982
983 /* Wait till LSESYSRDY is cleared */
984 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
985 {
986 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
987 {
988 return HAL_TIMEOUT;
989 }
990 }
991 }
992 }
993 else
994 {
995 tickstart = HAL_GetTick();
996
997 /* Wait till LSE is disabled */
998 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
999 {
1000 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1001 {
1002 return HAL_TIMEOUT;
1003 }
1004 }
1005
1006 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U)
1007 {
1008 /* Reset LSESYSEN once LSE is disabled */
1009 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1010
1011 /* Wait till LSESYSRDY is cleared */
1012 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
1013 {
1014 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1015 {
1016 return HAL_TIMEOUT;
1017 }
1018 }
1019 }
1020 }
1021
1022 /* Restore clock configuration if changed */
1023 if (pwrclkchanged == SET)
1024 {
1025 __HAL_RCC_PWR_CLK_DISABLE();
1026 }
1027 }
1028 /*------------------------------ HSI48 Configuration -----------------------*/
1029 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
1030 {
1031 /* Check the parameters */
1032 assert_param(IS_RCC_HSI48(pRCC_OscInitStruct->HSI48State));
1033
1034 /* Check the HSI48 State */
1035 if (pRCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
1036 {
1037 /* Enable the Internal High Speed oscillator (HSI48) */
1038 __HAL_RCC_HSI48_ENABLE();
1039
1040 tickstart = HAL_GetTick();
1041
1042 /* Wait till HSI48 is ready */
1043 while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
1044 {
1045 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
1046 {
1047 return HAL_TIMEOUT;
1048 }
1049 }
1050 }
1051 else
1052 {
1053 /* Disable the Internal High Speed oscillator (HSI48) */
1054 __HAL_RCC_HSI48_DISABLE();
1055
1056 tickstart = HAL_GetTick();
1057
1058 /* Wait till HSI48 is disabled */
1059 while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U)
1060 {
1061 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
1062 {
1063 return HAL_TIMEOUT;
1064 }
1065 }
1066 }
1067 }
1068
1069 /*------------------------------ SHSI Configuration -----------------------*/
1070 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_SHSI) == RCC_OSCILLATORTYPE_SHSI)
1071 {
1072 /* Check the parameters */
1073 assert_param(IS_RCC_SHSI(pRCC_OscInitStruct->SHSIState));
1074
1075 /* Check the SHSI State */
1076 if (pRCC_OscInitStruct->SHSIState != RCC_SHSI_OFF)
1077 {
1078 /* Enable the Secure Internal High Speed oscillator (SHSI) */
1079 __HAL_RCC_SHSI_ENABLE();
1080
1081 tickstart = HAL_GetTick();
1082
1083 /* Wait till SHSI is ready */
1084 while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == 0U)
1085 {
1086 if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
1087 {
1088 return HAL_TIMEOUT;
1089 }
1090 }
1091 }
1092 else
1093 {
1094 /* Disable the Secure Internal High Speed oscillator (SHSI) */
1095 __HAL_RCC_SHSI_DISABLE();
1096
1097 tickstart = HAL_GetTick();
1098
1099 /* Wait till SHSI is disabled */
1100 while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) != 0U)
1101 {
1102 if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
1103 {
1104 return HAL_TIMEOUT;
1105 }
1106 }
1107 }
1108 }
1109 /*------------------------------ MSIK Configuration -----------------------*/
1110 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSIK) == RCC_OSCILLATORTYPE_MSIK)
1111 {
1112 /* Check the parameters */
1113 assert_param(IS_RCC_MSIK(pRCC_OscInitStruct->MSIKState));
1114 assert_param(IS_RCC_MSIK_CLOCK_RANGE(pRCC_OscInitStruct->MSIKClockRange));
1115 assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
1116
1117 /* Check the MSIK State */
1118 if (pRCC_OscInitStruct->MSIKState != RCC_MSIK_OFF)
1119 {
1120
1121 /* Selects the Multiple Speed of kernel high speed oscillator (MSIK) clock range .*/
1122 __HAL_RCC_MSIK_RANGE_CONFIG(pRCC_OscInitStruct->MSIKClockRange);
1123 /* Adjusts the Multiple Speed of kernel high speed oscillator (MSIK) calibration value.*/
1124 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
1125 (pRCC_OscInitStruct->MSIClockRange));
1126
1127 /* Enable the Internal kernel High Speed oscillator (MSIK) */
1128 __HAL_RCC_MSIK_ENABLE();
1129
1130 tickstart = HAL_GetTick();
1131
1132 /* Wait till MSIK is ready */
1133 while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == 0U)
1134 {
1135 if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
1136 {
1137 return HAL_TIMEOUT;
1138 }
1139 }
1140 }
1141 else
1142 {
1143 /* Disable the Internal High Speed Kernel oscillator (MSIK) */
1144 __HAL_RCC_MSIK_DISABLE();
1145
1146 tickstart = HAL_GetTick();
1147
1148 /* Wait till MSIK is disabled */
1149 while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) != 0U)
1150 {
1151 if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
1152 {
1153 return HAL_TIMEOUT;
1154 }
1155 }
1156 }
1157 }
1158 /*-------------------------------- PLL Configuration -----------------------*/
1159 /* Check the parameters */
1160 assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL.PLLState));
1161
1162 if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
1163 {
1164 FlagStatus pwrclkchanged = RESET;
1165
1166 /* Check if the PLL is used as system clock or not */
1167 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1168 {
1169 if ((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
1170 {
1171 /* Check the parameters */
1172 assert_param(IS_RCC_PLLMBOOST_VALUE(pRCC_OscInitStruct->PLL.PLLMBOOST));
1173 assert_param(IS_RCC_PLLSOURCE(pRCC_OscInitStruct->PLL.PLLSource));
1174 assert_param(IS_RCC_PLLM_VALUE(pRCC_OscInitStruct->PLL.PLLM));
1175 assert_param(IS_RCC_PLLN_VALUE(pRCC_OscInitStruct->PLL.PLLN));
1176 assert_param(IS_RCC_PLLP_VALUE(pRCC_OscInitStruct->PLL.PLLP));
1177 assert_param(IS_RCC_PLLQ_VALUE(pRCC_OscInitStruct->PLL.PLLQ));
1178 assert_param(IS_RCC_PLLR_VALUE(pRCC_OscInitStruct->PLL.PLLR));
1179
1180 /* Disable the main PLL */
1181 __HAL_RCC_PLL_DISABLE();
1182
1183 tickstart = HAL_GetTick();
1184
1185 /* Wait till PLL is disabled */
1186 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
1187 {
1188 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1189 {
1190 return HAL_TIMEOUT;
1191 }
1192 }
1193
1194 /* Requires to enable write access to Backup Domain of necessary */
1195 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
1196 {
1197 __HAL_RCC_PWR_CLK_ENABLE();
1198 pwrclkchanged = SET;
1199 }
1200
1201 /*Disable EPOD to configure PLL1MBOOST*/
1202 if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN)
1203 {
1204 pwrboosten = SET;
1205 }
1206 CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1207
1208 /* Configure the main PLL clock source, multiplication and division factors */
1209 __HAL_RCC_PLL_CONFIG(pRCC_OscInitStruct->PLL.PLLSource,
1210 pRCC_OscInitStruct->PLL.PLLMBOOST,
1211 pRCC_OscInitStruct->PLL.PLLM,
1212 pRCC_OscInitStruct->PLL.PLLN,
1213 pRCC_OscInitStruct->PLL.PLLP,
1214 pRCC_OscInitStruct->PLL.PLLQ,
1215 pRCC_OscInitStruct->PLL.PLLR);
1216
1217 assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
1218
1219 /* Disable PLL1FRACN */
1220 __HAL_RCC_PLL_FRACN_DISABLE();
1221
1222 /* Configure PLL PLL1FRACN */
1223 __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
1224
1225 /* Enable PLL1FRACN */
1226 __HAL_RCC_PLL_FRACN_ENABLE();
1227
1228 assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE));
1229
1230 /* Select PLL1 input reference frequency range: VCI */
1231 __HAL_RCC_PLL_VCIRANGE(pRCC_OscInitStruct->PLL.PLLRGE);
1232
1233 if (pwrboosten == SET)
1234 {
1235 /* Enable the EPOD to reach max frequency */
1236 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1237 }
1238
1239 /* Restore clock configuration if changed */
1240 if (pwrclkchanged == SET)
1241 {
1242 __HAL_RCC_PWR_CLK_DISABLE();
1243 }
1244
1245 /* Enable PLL System Clock output */
1246 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
1247
1248 /* Enable the main PLL */
1249 __HAL_RCC_PLL_ENABLE();
1250
1251 tickstart = HAL_GetTick();
1252
1253 /* Wait till PLL is ready */
1254 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
1255 {
1256 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1257 {
1258 return HAL_TIMEOUT;
1259 }
1260 }
1261 }
1262 else
1263 {
1264 /* Disable the main PLL */
1265 __HAL_RCC_PLL_DISABLE();
1266
1267 tickstart = HAL_GetTick();
1268
1269 /* Wait till PLL is disabled */
1270 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
1271 {
1272 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1273 {
1274 return HAL_TIMEOUT;
1275 }
1276 }
1277
1278 /* Unselect main PLL clock source and disable main PLL outputs to save power */
1279 RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN);
1280
1281 }
1282 }
1283 else
1284 {
1285 /* Do not return HAL_ERROR if request repeats the current configuration */
1286 temp1_pllckcfg = RCC->PLL1CFGR;
1287 temp2_pllckcfg = RCC->PLL1DIVR;
1288 if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
1289 (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) ||
1290 ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \
1291 RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) ||
1292 (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) ||
1293 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) ||
1294 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \
1295 RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) ||
1296 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \
1297 RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) ||
1298 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \
1299 RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U)))
1300 {
1301 return HAL_ERROR;
1302 }
1303
1304 /* FRACN1 on-the-fly value update */
1305 if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \
1306 RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN))
1307 {
1308 assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
1309
1310 /* Disable PLL1FRACN. */
1311 __HAL_RCC_PLL_FRACN_DISABLE();
1312
1313 /* Get Start Tick*/
1314 tickstart = HAL_GetTick();
1315
1316 /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value
1317 will be taken into account. */
1318 while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE)
1319 {
1320 }
1321
1322 /* Configure PLL PLL1FRACN */
1323 __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
1324
1325 /* Enable PLL1FRACN to latch the new value. */
1326 __HAL_RCC_PLL_FRACN_ENABLE();
1327 }
1328 }
1329 }
1330 return HAL_OK;
1331 }
1332
1333 /**
1334 * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
1335 * parameters in the pRCC_ClkInitStruct.
1336 * @param pRCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
1337 * contains the configuration information for the RCC peripheral.
1338 * @param FLatency FLASH Latency
1339 * This parameter can be one of the following values:
1340 * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
1341 * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
1342 * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
1343 * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
1344 * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
1345 * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
1346 *
1347 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1348 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
1349 *
1350 * @note The MSI is used by default as system clock source after
1351 * startup from Reset, wake-up from STANDBY mode. After restart from Reset,
1352 * the MSI frequency is set to its default value 4 MHz.
1353 * @note The HSI can be selected as system clock source after wakeup
1354 * from STOP modes or in case of failure of the HSE used directly or indirectly
1355 * as system clock (if the Clock Security System CSS is enabled).
1356 * @note A switch from one clock source to another occurs only if the target
1357 * clock source is ready (clock stable after startup delay or PLL locked).
1358 * If a clock source which is not yet ready is selected, the switch will
1359 * occur when the clock source is ready.
1360 * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
1361 * currently used as system clock source.
1362 *
1363 * @note Depending on the device voltage range, the software has to set correctly
1364 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
1365 * (for more details refer to section above "Initialization/de-initialization functions")
1366 * @retval HAL status
1367 */
HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef * const pRCC_ClkInitStruct,uint32_t FLatency)1368 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency)
1369 {
1370 HAL_StatusTypeDef status;
1371 uint32_t tickstart;
1372
1373 /* Check Null pointer */
1374 if (pRCC_ClkInitStruct == NULL)
1375 {
1376 return HAL_ERROR;
1377 }
1378
1379 /* Check the parameters */
1380 assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType));
1381 assert_param(IS_FLASH_LATENCY(FLatency));
1382
1383 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
1384 must be correctly programmed according to the frequency of the CPU clock
1385 (HCLK) and the supply voltage of the device */
1386
1387 /* Increasing the number of wait states because of higher CPU frequency */
1388 if (FLatency > __HAL_FLASH_GET_LATENCY())
1389 {
1390 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1391 __HAL_FLASH_SET_LATENCY(FLatency);
1392
1393 /* Check that the new number of wait states is taken into account to access the Flash
1394 memory by reading the FLASH_ACR register */
1395 if (__HAL_FLASH_GET_LATENCY() != FLatency)
1396 {
1397 return HAL_ERROR;
1398 }
1399 }
1400
1401 /* Increasing the BUS frequency divider */
1402 /*-------------------------- PCLK3 Configuration ---------------------------*/
1403 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
1404 {
1405 if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3))
1406 {
1407 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
1408 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider);
1409 }
1410 }
1411 /*-------------------------- PCLK2 Configuration ---------------------------*/
1412 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1413 {
1414 if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4))
1415 {
1416 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
1417 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
1418 }
1419 }
1420
1421 /*-------------------------- PCLK1 Configuration ---------------------------*/
1422 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1423 {
1424 if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1))
1425 {
1426 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
1427 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
1428 }
1429 }
1430
1431 /*-------------------------- HCLK Configuration --------------------------*/
1432 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1433 {
1434 if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE))
1435 {
1436 assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
1437 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
1438 }
1439 }
1440
1441 /*------------------------- SYSCLK Configuration ---------------------------*/
1442 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
1443 {
1444 assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
1445 FlagStatus pwrclkchanged = RESET;
1446
1447 /* PLL is selected as System Clock Source */
1448 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1449 {
1450 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
1451 {
1452 __HAL_RCC_PWR_CLK_ENABLE();
1453 pwrclkchanged = SET;
1454 }
1455 tickstart = HAL_GetTick();
1456 /* Check if EPOD is enabled */
1457 if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U)
1458 {
1459 /* Wait till BOOST is ready */
1460 while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == 0U)
1461 {
1462 if ((HAL_GetTick() - tickstart) > EPOD_TIMEOUT_VALUE)
1463 {
1464 return HAL_TIMEOUT;
1465 }
1466 }
1467 }
1468
1469 /* Restore clock configuration if changed */
1470 if (pwrclkchanged == SET)
1471 {
1472 __HAL_RCC_PWR_CLK_DISABLE();
1473 }
1474
1475 /* Check the PLL ready flag */
1476 if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
1477 {
1478 return HAL_ERROR;
1479 }
1480 }
1481 else
1482 {
1483 /* HSE is selected as System Clock Source */
1484 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1485 {
1486 /* Check the HSE ready flag */
1487 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
1488 {
1489 return HAL_ERROR;
1490 }
1491 }
1492 /* MSI is selected as System Clock Source */
1493 else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
1494 {
1495 /* Check the MSI ready flag */
1496 if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
1497 {
1498 return HAL_ERROR;
1499 }
1500 }
1501 /* HSI is selected as System Clock Source */
1502 else
1503 {
1504 /* Check the HSI ready flag */
1505 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
1506 {
1507 return HAL_ERROR;
1508 }
1509 }
1510 }
1511
1512 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pRCC_ClkInitStruct->SYSCLKSource);
1513
1514 tickstart = HAL_GetTick();
1515
1516 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1517 {
1518 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1519 {
1520 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1521 {
1522 return HAL_TIMEOUT;
1523 }
1524 }
1525 }
1526 else
1527 {
1528 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1529 {
1530 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
1531 {
1532 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1533 {
1534 return HAL_TIMEOUT;
1535 }
1536 }
1537 }
1538 else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
1539 {
1540 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
1541 {
1542 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1543 {
1544 return HAL_TIMEOUT;
1545 }
1546 }
1547 }
1548 else
1549 {
1550 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
1551 {
1552 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1553 {
1554 return HAL_TIMEOUT;
1555 }
1556 }
1557 }
1558 }
1559 }
1560
1561 /* Decreasing the BUS frequency divider */
1562 /*-------------------------- HCLK Configuration --------------------------*/
1563 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1564 {
1565 if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE))
1566 {
1567 assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
1568 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
1569 }
1570 }
1571
1572 /* Decreasing the number of wait states because of lower CPU frequency */
1573 if (FLatency < __HAL_FLASH_GET_LATENCY())
1574 {
1575 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1576 __HAL_FLASH_SET_LATENCY(FLatency);
1577
1578 /* Check that the new number of wait states is taken into account to access the Flash
1579 memory by reading the FLASH_ACR register */
1580 if (__HAL_FLASH_GET_LATENCY() != FLatency)
1581 {
1582 return HAL_ERROR;
1583 }
1584 }
1585
1586 /*-------------------------- PCLK1 Configuration ---------------------------*/
1587 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1588 {
1589 if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1))
1590 {
1591 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
1592 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
1593 }
1594 }
1595
1596 /*-------------------------- PCLK2 Configuration ---------------------------*/
1597 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1598 {
1599 if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4))
1600 {
1601 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
1602 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
1603 }
1604 }
1605
1606 /*-------------------------- PCLK3 Configuration ---------------------------*/
1607 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
1608 {
1609 if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3))
1610 {
1611 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
1612 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider));
1613 }
1614 }
1615
1616 /* Update the SystemCoreClock global variable */
1617 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
1618
1619 /* Configure the source of time base considering new system clocks settings*/
1620 status = HAL_InitTick(uwTickPrio);
1621
1622 return status;
1623 }
1624
1625 /**
1626 * @}
1627 */
1628
1629 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1630 * @brief RCC clocks control functions
1631 *
1632 @verbatim
1633 ===============================================================================
1634 ##### Peripheral Control functions #####
1635 ===============================================================================
1636 [..]
1637 This subsection provides a set of functions allowing to:
1638
1639 (+) Output clock to MCO pin.
1640 (+) Retrieve current clock frequencies.
1641 (+) Enable the Clock Security System.
1642
1643 @endverbatim
1644 * @{
1645 */
1646
1647 /**
1648 * @brief Select the clock source to output on MCO pin(PA8).
1649 * @note PA8 should be configured in alternate function mode.
1650 * @param RCC_MCOx specifies the output direction for the clock source.
1651 * For STM32U5xx family this parameter can have only one value:
1652 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
1653 * @param RCC_MCOSource specifies the clock source to output.
1654 * This parameter can be one of the following values:
1655 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
1656 * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
1657 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
1658 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
1659 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
1660 * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source
1661 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
1662 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
1663 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
1664 * @param RCC_MCODiv specifies the MCO prescaler.
1665 * This parameter can be one of the following values:
1666 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
1667 * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
1668 * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
1669 * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
1670 * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
1671 * @retval None
1672 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)1673 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1674 {
1675 GPIO_InitTypeDef gpio_initstruct;
1676 /* Check the parameters */
1677 assert_param(IS_RCC_MCO(RCC_MCOx));
1678 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1679 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1680
1681 /* MCO Clock Enable */
1682 MCO1_CLK_ENABLE();
1683
1684 /* Configure the MCO1 pin in alternate function mode */
1685 gpio_initstruct.Pin = MCO1_PIN;
1686 gpio_initstruct.Mode = GPIO_MODE_AF_PP;
1687 gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
1688 gpio_initstruct.Pull = GPIO_NOPULL;
1689 gpio_initstruct.Alternate = GPIO_AF0_MCO;
1690 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio_initstruct);
1691
1692 /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
1693 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
1694 }
1695
1696 /**
1697 * @brief Return the SYSCLK frequency.
1698 * @note The system frequency computed by this function is not the real
1699 * frequency in the chip. It is calculated based on the predefined
1700 * constant and the selected clock source:
1701 * @note If SYSCLK source is MSI, function returns values based on MSI
1702 * Value as defined by the MSI range.
1703 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1704 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
1705 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
1706 * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
1707 * @note (*) HSI_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
1708 * 16 MHz) but the real value may vary depending on the variations
1709 * in voltage and temperature.
1710 * @note (**) HSE_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
1711 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
1712 * frequency of the crystal used. Otherwise, this function may
1713 * have wrong result.
1714 * @note The result of this function could be not correct when using fractional
1715 * value for HSE crystal.
1716 * @note This function can be used by the user application to compute the
1717 * baudrate for the communication peripherals or configure other parameters.
1718 * @note Each time SYSCLK changes, this function must be called to update the
1719 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1720 * @retval SYSCLK frequency
1721 */
HAL_RCC_GetSysClockFreq(void)1722 uint32_t HAL_RCC_GetSysClockFreq(void)
1723 {
1724 uint32_t msirange = 0U;
1725 uint32_t pllsource;
1726 uint32_t pllr;
1727 uint32_t pllm;
1728 uint32_t pllfracen;
1729 uint32_t sysclockfreq = 0U;
1730 uint32_t sysclk_source;
1731 uint32_t pll_oscsource;
1732 float_t fracn1;
1733 float_t pllvco;
1734
1735 sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
1736 pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
1737
1738 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
1739 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
1740 {
1741 /* MSI or PLL with MSI source used as system clock source */
1742
1743 /* Get SYSCLK source */
1744 if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
1745 {
1746 /* MSISRANGE from RCC_CSR applies */
1747 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
1748 }
1749 else
1750 {
1751 /* MSIRANGE from RCC_CR applies */
1752 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
1753 }
1754 /*MSI frequency range in HZ*/
1755 msirange = MSIRangeTable[msirange];
1756
1757 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
1758 {
1759 /* MSI used as system clock source */
1760 sysclockfreq = msirange;
1761 }
1762 }
1763 else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
1764 {
1765 /* HSI used as system clock source */
1766 sysclockfreq = HSI_VALUE;
1767 }
1768 else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
1769 {
1770 /* HSE used as system clock source */
1771 sysclockfreq = HSE_VALUE;
1772 }
1773 else
1774 {
1775 /* Nothing to do */
1776 }
1777
1778 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1779 {
1780 /* PLL used as system clock source
1781 PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1782 SYSCLK = PLL_VCO / PLLR
1783 */
1784 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1785 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
1786 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
1787 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1788 RCC_PLL1FRACR_PLL1FRACN_Pos));
1789
1790 switch (pllsource)
1791 {
1792 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1793 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1794 (fracn1 / (float_t)0x2000) + (float_t)1U);
1795 break;
1796
1797 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1798 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1799 (fracn1 / (float_t)0x2000) + (float_t)1U);
1800 break;
1801
1802 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1803 default:
1804 pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1805 (fracn1 / (float_t)0x2000) + (float_t)1U);
1806 break;
1807 }
1808
1809 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
1810 sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr);
1811 }
1812
1813 return sysclockfreq;
1814 }
1815
1816 /**
1817 * @brief Return the HCLK frequency.
1818 * @note Each time HCLK changes, this function must be called to update the
1819 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1820 *
1821 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
1822 * @retval HCLK frequency in Hz
1823 */
HAL_RCC_GetHCLKFreq(void)1824 uint32_t HAL_RCC_GetHCLKFreq(void)
1825 {
1826 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
1827 return SystemCoreClock;
1828 }
1829
1830 /**
1831 * @brief Return the PCLK1 frequency.
1832 * @note Each time PCLK1 changes, this function must be called to update the
1833 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1834 * @retval PCLK1 frequency in Hz
1835 */
HAL_RCC_GetPCLK1Freq(void)1836 uint32_t HAL_RCC_GetPCLK1Freq(void)
1837 {
1838 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1839 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]);
1840 }
1841
1842 /**
1843 * @brief Return the PCLK2 frequency.
1844 * @note Each time PCLK2 changes, this function must be called to update the
1845 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1846 * @retval PCLK2 frequency in Hz
1847 */
HAL_RCC_GetPCLK2Freq(void)1848 uint32_t HAL_RCC_GetPCLK2Freq(void)
1849 {
1850 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1851 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]);
1852 }
1853
1854 /**
1855 * @brief Return the PCLK3 frequency.
1856 * @note Each time PCLK3 changes, this function must be called to update the
1857 * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect.
1858 * @retval PCLK3 frequency in Hz
1859 */
HAL_RCC_GetPCLK3Freq(void)1860 uint32_t HAL_RCC_GetPCLK3Freq(void)
1861 {
1862 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1863 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE3) >> RCC_CFGR3_PPRE3_Pos]);
1864 }
1865 /**
1866 * @brief Get the pRCC_OscInitStruct according to the internal
1867 * RCC configuration registers.
1868 * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1869 * will be configured.
1870 * @retval None
1871 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * pRCC_OscInitStruct)1872 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
1873 {
1874 uint32_t regval;
1875 uint32_t reg1val;
1876 uint32_t reg2val;
1877
1878 /* Check the parameters */
1879 assert_param(pRCC_OscInitStruct != (void *)NULL);
1880
1881 /* Set all possible values for the Oscillator type parameter ---------------*/
1882 pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
1883 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
1884
1885 /* Get Control register */
1886 regval = RCC->CR;
1887
1888 /* Get the HSE configuration -----------------------------------------------*/
1889 pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT));
1890
1891 /* Get the MSI configuration -----------------------------------------------*/
1892 pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON;
1893
1894 reg1val = RCC->ICSCR1;
1895 reg2val = RCC->ICSCR2;
1896
1897 pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE));
1898 if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12)
1899 {
1900 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \
1901 RCC_ICSCR2_MSITRIM3_Pos);
1902 }
1903 else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8)
1904 {
1905 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \
1906 RCC_ICSCR2_MSITRIM2_Pos);
1907 }
1908 else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4)
1909 {
1910 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \
1911 RCC_ICSCR2_MSITRIM1_Pos);
1912 }
1913 else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/
1914 {
1915 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \
1916 RCC_ICSCR2_MSITRIM0_Pos);
1917 }
1918
1919
1920 /* Get the HSI configuration -----------------------------------------------*/
1921 pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION;
1922 pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
1923
1924 /* Get BDCR register */
1925 regval = RCC->BDCR;
1926
1927 /* Get the LSE configuration -----------------------------------------------*/
1928 pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN));
1929
1930 /* Get the LSI configuration -----------------------------------------------*/
1931 pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION;
1932
1933 /* Get Control register */
1934 regval = RCC->CR;
1935
1936 /* Get the HSI48 configuration ---------------------------------------------*/
1937 pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON;
1938
1939 /* Get the PLL configuration -----------------------------------------------*/
1940 if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON)
1941 {
1942 pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1943 }
1944 else
1945 {
1946 pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1947 }
1948
1949 reg1val = RCC->PLL1CFGR;
1950 reg2val = RCC->PLL1DIVR;
1951
1952 pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC);
1953 pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U);
1954 pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U);
1955 pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U);
1956 pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
1957 pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U);
1958 pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE));
1959 pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1960 RCC_PLL1FRACR_PLL1FRACN_Pos));
1961 pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \
1962 RCC_PLL1CFGR_PLL1MBOOST_Pos));
1963 }
1964
1965 /**
1966 * @brief Configure the pRCC_ClkInitStruct according to the internal
1967 * RCC configuration registers.
1968 * @param pRCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1969 * will be configured.
1970 * @param pFLatency Pointer on the Flash Latency.
1971 * @retval None
1972 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * pRCC_ClkInitStruct,uint32_t * pFLatency)1973 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency)
1974 {
1975 /* Check the parameters */
1976 assert_param(pRCC_ClkInitStruct != (void *)NULL);
1977 assert_param(pFLatency != (void *)NULL);
1978
1979 /* Set all possible values for the Clock type parameter --------------------*/
1980 pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
1981 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
1982
1983 /* Get the SYSCLK configuration --------------------------------------------*/
1984 pRCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW);
1985
1986 /* Get the HCLK configuration ----------------------------------------------*/
1987 pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE);
1988
1989 /* Get the APB1 configuration ----------------------------------------------*/
1990 pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1);
1991
1992 /* Get the APB2 configuration ----------------------------------------------*/
1993 pRCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4);
1994
1995 /* Get the APB3 configuration ----------------------------------------------*/
1996 pRCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CFGR3 & RCC_CFGR3_PPRE3);
1997
1998 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1999 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
2000 }
2001
2002 /**
2003 * @brief Get and clear reset flags
2004 * @note Once reset flags are retrieved, this API is clearing them in order
2005 * to isolate next reset reason.
2006 * @retval can be a combination of @ref RCC_Reset_Flag
2007 */
HAL_RCC_GetResetSource(void)2008 uint32_t HAL_RCC_GetResetSource(void)
2009 {
2010 uint32_t reset;
2011
2012 /* Get all reset flags */
2013 reset = RCC->CSR & RCC_RESET_FLAG_ALL;
2014
2015 /* Clear Reset flags */
2016 RCC->CSR |= RCC_CSR_RMVF;
2017
2018 return reset;
2019 }
2020
2021 /**
2022 * @brief Enable the Clock Security System.
2023 * @note If a failure is detected on the HSE oscillator clock, this oscillator
2024 * is automatically disabled and an interrupt is generated to inform the
2025 * software about the failure (Clock Security System Interrupt, CSSI),
2026 * allowing the MCU to perform rescue operations. The CSSI is linked to
2027 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
2028 * @note The Clock Security System can only be cleared by reset.
2029 * @retval None
2030 */
HAL_RCC_EnableCSS(void)2031 void HAL_RCC_EnableCSS(void)
2032 {
2033 SET_BIT(RCC->CR, RCC_CR_CSSON);
2034 }
2035
2036 /**
2037 * @brief Handle the RCC Clock Security System interrupt request.
2038 * @note This API should be called under the NMI_Handler().
2039 * @retval None
2040 */
HAL_RCC_NMI_IRQHandler(void)2041 void HAL_RCC_NMI_IRQHandler(void)
2042 {
2043 /* Check RCC CSSF interrupt flag */
2044 if (__HAL_RCC_GET_IT(RCC_IT_CSS))
2045 {
2046 /* RCC Clock Security System interrupt user callback */
2047 HAL_RCC_CSSCallback();
2048
2049 /* Clear RCC CSS pending bit */
2050 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
2051 }
2052 }
2053
2054 /**
2055 * @brief RCC Clock Security System interrupt callback.
2056 * @retval none
2057 */
HAL_RCC_CSSCallback(void)2058 __weak void HAL_RCC_CSSCallback(void)
2059 {
2060 /* NOTE : This function should not be modified, when the callback is needed,
2061 the HAL_RCC_CSSCallback should be implemented in the user file
2062 */
2063 }
2064
2065 /**
2066 * @}
2067 */
2068 /** @defgroup RCC_Exported_Functions_Group3 Attributes management functions
2069 * @brief Attributes management functions.
2070 *
2071 @verbatim
2072 ===============================================================================
2073 ##### RCC attributes functions #####
2074 ===============================================================================
2075 @endverbatim
2076 * @{
2077 */
2078 /**
2079 * @brief Configure the RCC item attribute(s).
2080 * @note Available attributes are to secure items and set RCC as privileged.
2081 * @param Item Item(s) to set attributes on.
2082 * This parameter can be a one or a combination of @ref RCC_items
2083 * @param Attributes specifies the RCC secure/privilege attributes.
2084 * This parameter can be a value of @ref RCC_attributes
2085 * @retval None
2086 */
HAL_RCC_ConfigAttributes(uint32_t Item,uint32_t Attributes)2087 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
2088 {
2089 /* Check the parameters */
2090 assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
2091 assert_param(IS_RCC_ATTRIBUTES(Attributes));
2092
2093 switch (Attributes)
2094 {
2095 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2096 /* Secure Privilege attribute */
2097 case RCC_SEC_PRIV:
2098 SET_BIT(RCC->SECCFGR, Item);
2099 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2100 break;
2101 /* Secure Non-Privilege attribute */
2102 case RCC_SEC_NPRIV:
2103 SET_BIT(RCC->SECCFGR, Item);
2104 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2105 break;
2106 /* Non-secure Privilege attribute */
2107 case RCC_NSEC_PRIV:
2108 CLEAR_BIT(RCC->SECCFGR, Item);
2109 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2110 break;
2111 /* Non-secure Non-Privilege attribute */
2112 case RCC_NSEC_NPRIV:
2113 CLEAR_BIT(RCC->SECCFGR, Item);
2114 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2115 break;
2116 #else
2117 /* Non-secure Privilege attribute */
2118 case RCC_NSEC_PRIV:
2119 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2120 break;
2121 /* Non-secure Non-Privilege attribute */
2122 case RCC_NSEC_NPRIV:
2123 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2124 break;
2125 #endif /* __ARM_FEATURE_CMSE */
2126 default:
2127 /* Nothing to do */
2128 break;
2129 }
2130 }
2131 /**
2132 * @}
2133 */
2134
2135 /**
2136 * @brief Get the attribute of a RCC item.
2137 * @note Secure and non-secure attributes are only available from secure state
2138 * when the system implements the security (TZEN=1)
2139 * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from.
2140 * This parameter can be a one value of @ref RCC_items except RCC_ALL.
2141 * @param pAttributes pointer to return the attributes.
2142 * @retval HAL Status.
2143 */
HAL_RCC_GetConfigAttributes(uint32_t Item,uint32_t * pAttributes)2144 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
2145 {
2146 uint32_t attributes;
2147
2148 /* Check null pointer */
2149 if (pAttributes == NULL)
2150 {
2151 return HAL_ERROR;
2152 }
2153
2154 /* Check the parameters */
2155 assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
2156
2157 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2158
2159 /* Check item security */
2160 if ((RCC->SECCFGR & Item) == Item)
2161 {
2162 /* Get Secure privileges attribute */
2163 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV;
2164 }
2165 else
2166 {
2167 /* Get Non-Secure privileges attribute */
2168 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
2169 }
2170 #else
2171 /* Get Non-Secure privileges attribute */
2172 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
2173 #endif /* __ARM_FEATURE_CMSE */
2174
2175 /* return value */
2176 *pAttributes = attributes;
2177
2178 return HAL_OK;
2179 }
2180 /**
2181 * @}
2182 */
2183
2184 /* Private function prototypes -----------------------------------------------*/
2185 /** @addtogroup RCC_Private_Functions
2186 * @{
2187 */
2188 /**
2189 * @brief Update number of Flash wait states in line with MSI range and current
2190 voltage range.
2191 * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_15
2192 * @retval HAL status
2193 */
RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)2194 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
2195 {
2196 uint32_t vos;
2197 uint32_t latency; /* default value 0WS */
2198
2199 if (__HAL_RCC_PWR_IS_CLK_ENABLED())
2200 {
2201 vos = HAL_PWREx_GetVoltageRange();
2202 }
2203 else
2204 {
2205 __HAL_RCC_PWR_CLK_ENABLE();
2206 vos = HAL_PWREx_GetVoltageRange();
2207 __HAL_RCC_PWR_CLK_DISABLE();
2208 }
2209
2210 if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
2211 {
2212
2213 if (msirange < RCC_MSIRANGE_1)
2214 {
2215 /* MSI = 48Mhz */
2216 latency = FLASH_LATENCY_1; /* 1WS */
2217 }
2218 else
2219 {
2220 /* MSI < 48Mhz */
2221 latency = FLASH_LATENCY_0; /* 0WS */
2222 }
2223 }
2224 else
2225 {
2226 if (msirange < RCC_MSIRANGE_1)
2227 {
2228 /* MSI = 48Mhz */
2229 if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
2230 {
2231 latency = FLASH_LATENCY_3; /* 3WS */
2232 }
2233 else
2234 {
2235 return HAL_ERROR;
2236 }
2237 }
2238 else
2239 {
2240 if (msirange > RCC_MSIRANGE_2)
2241 {
2242 if (vos == PWR_REGULATOR_VOLTAGE_SCALE4)
2243 {
2244 if (msirange > RCC_MSIRANGE_3)
2245 {
2246 latency = FLASH_LATENCY_0; /* 1WS */
2247 }
2248 else
2249 {
2250 latency = FLASH_LATENCY_1; /* 0WS */
2251 }
2252 }
2253 else
2254 {
2255 latency = FLASH_LATENCY_0; /* 0WS */
2256 }
2257 }
2258 else
2259 {
2260 if (msirange == RCC_MSIRANGE_1)
2261 {
2262 if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
2263 {
2264 latency = FLASH_LATENCY_1; /* 1WS */
2265 }
2266 else
2267 {
2268 latency = FLASH_LATENCY_2; /* 2WS */
2269 }
2270 }
2271 else
2272 {
2273 latency = FLASH_LATENCY_1; /* 1WS */
2274 }
2275 }
2276 }
2277 }
2278
2279 __HAL_FLASH_SET_LATENCY(latency);
2280
2281 /* Check that the new number of wait states is taken into account to access the Flash
2282 memory by reading the FLASH_ACR register */
2283 if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
2284 {
2285 return HAL_ERROR;
2286 }
2287
2288 return HAL_OK;
2289 }
2290
2291 /**
2292 * @}
2293 */
2294 #endif /* HAL_RCC_MODULE_ENABLED */
2295 /**
2296 * @}
2297 */
2298
2299 /**
2300 * @}
2301 */
2302
