1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32L0xx_HAL_RCC_H 20 #define __STM32L0xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l0xx_hal_def.h" 28 29 /** @addtogroup STM32L0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @addtogroup RCC_Private_Constants 38 * @{ 39 */ 40 41 /** @defgroup RCC_Timeout RCC Timeout 42 * @{ 43 */ 44 45 /* Disable Backup domain write protection state change timeout */ 46 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ 47 /* LSE state change timeout */ 48 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 49 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 50 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 51 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 52 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 53 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 54 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 55 #if defined(RCC_HSI48_SUPPORT) 56 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 57 #endif /* RCC_HSI48_SUPPORT */ 58 /** 59 * @} 60 */ 61 62 63 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 64 * @brief RCC registers bit address in the alias region 65 * @{ 66 */ 67 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 68 /* --- CR Register ---*/ 69 /* Alias word address of HSION bit */ 70 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) 71 /* --- CFGR Register ---*/ 72 /* Alias word address of I2SSRC bit */ 73 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 74 /* --- CSR Register ---*/ 75 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) 76 77 /* CR register byte 3 (Bits[23:16]) base address */ 78 #define RCC_CR_BYTE2_ADDRESS (0x40023802U) 79 80 /* CIER register byte 0 (Bits[0:8]) base address */ 81 #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U)) 82 /** 83 * @} 84 */ 85 86 87 /* Defines used for Flags */ 88 #define CR_REG_INDEX ((uint8_t)1) 89 #define CSR_REG_INDEX ((uint8_t)2) 90 #define CRRCR_REG_INDEX ((uint8_t)3) 91 92 #define RCC_FLAG_MASK ((uint8_t)0x1F) 93 94 /** 95 * @} 96 */ 97 98 /** @addtogroup RCC_Private_Macros 99 * @{ 100 */ 101 #if defined(RCC_HSI48_SUPPORT) 102 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 103 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 104 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 105 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 106 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 107 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 108 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) 109 110 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 111 #else 112 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 113 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 114 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 115 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 116 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 117 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) 118 #endif /* RCC_HSI48_SUPPORT */ 119 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 120 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 121 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 122 ((__HSE__) == RCC_HSE_BYPASS)) 123 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 124 ((__LSE__) == RCC_LSE_BYPASS)) 125 #if defined(RCC_CR_HSIOUTEN) 126 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ 127 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN) || \ 128 ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_ON)) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_DIV4))) 129 #else 130 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ 131 ((__HSI__) == RCC_HSI_DIV4)) 132 #endif /* RCC_CR_HSIOUTEN */ 133 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 134 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) 135 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 136 ((__RANGE__) == RCC_MSIRANGE_1) || \ 137 ((__RANGE__) == RCC_MSIRANGE_2) || \ 138 ((__RANGE__) == RCC_MSIRANGE_3) || \ 139 ((__RANGE__) == RCC_MSIRANGE_4) || \ 140 ((__RANGE__) == RCC_MSIRANGE_5) || \ 141 ((__RANGE__) == RCC_MSIRANGE_6)) 142 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 143 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 144 145 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 146 ((__PLL__) == RCC_PLL_ON)) 147 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ 148 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) 149 150 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ 151 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ 152 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ 153 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ 154 ((__MUL__) == RCC_PLL_MUL48)) 155 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 156 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 157 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 158 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 159 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 160 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 161 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 162 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 163 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ 164 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 165 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 166 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 167 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 168 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 169 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 170 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 171 ((__HCLK__) == RCC_SYSCLK_DIV512)) 172 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 173 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 174 ((__PCLK__) == RCC_HCLK_DIV16)) 175 #if defined(RCC_MCO3_SUPPORT) 176 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3)) 177 #else 178 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2)) 179 180 #endif /* RCC_MCO3_SUPPORT */ 181 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 182 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 183 ((__DIV__) == RCC_MCODIV_16)) 184 #if defined(RCC_CFGR_MCOSEL_HSI48) 185 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 186 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 187 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 188 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 189 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 190 #else 191 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 192 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 193 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 194 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 195 #endif /* RCC_CFGR_MCOSEL_HSI48 */ 196 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 197 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 198 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 199 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 200 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 201 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 202 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) 203 204 /** 205 * @} 206 */ 207 208 /* Exported types ------------------------------------------------------------*/ 209 210 /** @defgroup RCC_Exported_Types RCC Exported Types 211 * @{ 212 */ 213 214 /** 215 * @brief RCC PLL configuration structure definition 216 */ 217 typedef struct 218 { 219 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 220 This parameter can be a value of @ref RCC_PLL_Config */ 221 222 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 223 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 224 225 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 226 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ 227 228 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock 229 This parameter must be a value of @ref RCC_PLL_Division_Factor*/ 230 } RCC_PLLInitTypeDef; 231 232 /** 233 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 234 */ 235 typedef struct 236 { 237 uint32_t OscillatorType; /*!< The oscillators to be configured. 238 This parameter can be a value of @ref RCC_Oscillator_Type */ 239 240 uint32_t HSEState; /*!< The new state of the HSE. 241 This parameter can be a value of @ref RCC_HSE_Config */ 242 243 uint32_t LSEState; /*!< The new state of the LSE. 244 This parameter can be a value of @ref RCC_LSE_Config */ 245 246 uint32_t HSIState; /*!< The new state of the HSI. 247 This parameter can be a value of @ref RCC_HSI_Config */ 248 249 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 250 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 251 252 uint32_t LSIState; /*!< The new state of the LSI. 253 This parameter can be a value of @ref RCC_LSI_Config */ 254 255 #if defined(RCC_HSI48_SUPPORT) 256 uint32_t HSI48State; /*!< The new state of the HSI48. 257 This parameter can be a value of @ref RCC_HSI48_Config */ 258 259 #endif /* RCC_HSI48_SUPPORT */ 260 uint32_t MSIState; /*!< The new state of the MSI. 261 This parameter can be a value of @ref RCC_MSI_Config */ 262 263 uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). 264 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 265 266 uint32_t MSIClockRange; /*!< The MSI frequency range. 267 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 268 269 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 270 271 } RCC_OscInitTypeDef; 272 273 /** 274 * @brief RCC System, AHB and APB busses clock configuration structure definition 275 */ 276 typedef struct 277 { 278 uint32_t ClockType; /*!< The clock to be configured. 279 This parameter can be a value of @ref RCC_System_Clock_Type */ 280 281 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 282 This parameter can be a value of @ref RCC_System_Clock_Source */ 283 284 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 285 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 286 287 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 288 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 289 290 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 291 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 292 } RCC_ClkInitTypeDef; 293 294 /** 295 * @} 296 */ 297 298 /* Exported constants --------------------------------------------------------*/ 299 /** @defgroup RCC_Exported_Constants RCC Exported Constants 300 * @{ 301 */ 302 303 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 304 * @{ 305 */ 306 307 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 308 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 309 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCC_Oscillator_Type Oscillator Type 315 * @{ 316 */ 317 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) 318 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) 319 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) 320 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) 321 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) 322 #define RCC_OSCILLATORTYPE_MSI (0x00000010U) 323 #if defined(RCC_HSI48_SUPPORT) 324 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) 325 #endif /* RCC_HSI48_SUPPORT */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup RCC_HSE_Config HSE Config 331 * @{ 332 */ 333 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 334 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 335 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup RCC_LSE_Config LSE Config 341 * @{ 342 */ 343 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ 344 #define RCC_LSE_ON RCC_CSR_LSEON /*!< LSE clock activation */ 345 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) /*!< External clock source for LSE clock */ 346 347 /** 348 * @} 349 */ 350 351 /** @defgroup RCC_HSI_Config HSI Config 352 * @{ 353 */ 354 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 355 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 356 #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */ 357 #if defined(RCC_CR_HSIOUTEN) 358 #define RCC_HSI_OUTEN RCC_CR_HSIOUTEN /*!< HSI_OUTEN clock activation */ 359 /* This value is to be used in combination with RCC_HSI_ON/RCC_HSI_DIV4 */ 360 #endif /* RCC_CR_HSIOUTEN */ 361 362 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ 363 364 /** 365 * @} 366 */ 367 368 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 369 * @{ 370 */ 371 372 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ 373 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ 374 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ 375 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ 376 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ 377 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ 378 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ 379 380 /** 381 * @} 382 */ 383 384 /** @defgroup RCC_LSI_Config LSI Config 385 * @{ 386 */ 387 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 388 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 389 390 /** 391 * @} 392 */ 393 394 /** @defgroup RCC_MSI_Config MSI Config 395 * @{ 396 */ 397 #define RCC_MSI_OFF (0x00000000U) 398 #define RCC_MSI_ON (0x00000001U) 399 400 #define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */ 401 402 /** 403 * @} 404 */ 405 406 #if defined(RCC_HSI48_SUPPORT) 407 /** @defgroup RCC_HSI48_Config HSI48 Config 408 * @{ 409 */ 410 #define RCC_HSI48_OFF ((uint8_t)0x00) 411 #define RCC_HSI48_ON ((uint8_t)0x01) 412 413 /** 414 * @} 415 */ 416 #endif /* RCC_HSI48_SUPPORT */ 417 418 /** @defgroup RCC_PLL_Config PLL Config 419 * @{ 420 */ 421 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ 422 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ 423 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ 424 425 /** 426 * @} 427 */ 428 429 /** @defgroup RCC_System_Clock_Type System Clock Type 430 * @{ 431 */ 432 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 433 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 434 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 435 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ 436 437 /** 438 * @} 439 */ 440 441 /** @defgroup RCC_System_Clock_Source System Clock Source 442 * @{ 443 */ 444 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ 445 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 446 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 447 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 448 449 /** 450 * @} 451 */ 452 453 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 454 * @{ 455 */ 456 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 457 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 458 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 459 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 460 461 /** 462 * @} 463 */ 464 465 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 466 * @{ 467 */ 468 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 469 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 470 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 471 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 472 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 473 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 474 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 475 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 476 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 477 478 /** 479 * @} 480 */ 481 482 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 483 * @{ 484 */ 485 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 486 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 487 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 488 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 489 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 490 491 /** 492 * @} 493 */ 494 495 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 496 * @{ 497 */ 498 #define RCC_RTC_HSE_DIV_2 (0x00000000U) /*!< HSE is divided by 2 for RTC clock */ 499 #define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ 500 #define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ 501 #define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source 507 * @{ 508 */ 509 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ 510 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 511 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 512 #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ 513 #define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ 514 #define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ 515 #define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ 516 #define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup RCC_PLL_Division_Factor PLL Division Factor 522 * @{ 523 */ 524 525 #define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 526 #define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 527 #define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 528 529 /** 530 * @} 531 */ 532 533 /** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor 534 * @{ 535 */ 536 537 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 538 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 539 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 540 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 541 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 542 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 543 #define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 544 #define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 545 #define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 546 547 /** 548 * @} 549 */ 550 551 /** @defgroup RCC_MCO_Index MCO Index 552 * @{ 553 */ 554 #define RCC_MCO1 (0x00000000U) 555 #define RCC_MCO2 (0x00000001U) 556 #if defined(RCC_MCO3_SUPPORT) 557 #define RCC_MCO3 (0x00000002U) 558 #if defined(RCC_MCO3_AF0_SUPPORT) 559 #define MCO3_GPIO_AF GPIO_AF0_MCO 560 #else 561 #define MCO3_GPIO_AF GPIO_AF2_MCO 562 #endif /* RCC_MCO3_AF0_SUPPORT */ 563 #endif /* RCC_MCO3_SUPPORT */ 564 565 /** 566 * @} 567 */ 568 569 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 570 * @{ 571 */ 572 #define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 573 #define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 574 #define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 575 #define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 576 #define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 577 578 /** 579 * @} 580 */ 581 582 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 583 * @{ 584 */ 585 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK 586 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK 587 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI 588 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI 589 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE 590 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI 591 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE 592 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL 593 #if defined(RCC_CFGR_MCOSEL_HSI48) 594 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 595 #endif /* RCC_CFGR_MCOSEL_HSI48 */ 596 597 /** 598 * @} 599 */ 600 /** @defgroup RCC_Interrupt Interrupts 601 * @{ 602 */ 603 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 604 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 605 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 606 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 607 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 608 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 609 #define RCC_IT_LSECSS RCC_CIFR_CSSLSEF /*!< LSE Clock Security System Interrupt flag */ 610 #if defined(RCC_HSECSS_SUPPORT) 611 #define RCC_IT_CSS RCC_CIFR_CSSHSEF /*!< Clock Security System Interrupt flag */ 612 #endif /* RCC_HSECSS_SUPPORT */ 613 #if defined(RCC_HSI48_SUPPORT) 614 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 615 #endif /* RCC_HSI48_SUPPORT */ 616 /** 617 * @} 618 */ 619 620 /** @defgroup RCC_Flag Flags 621 * Elements values convention: XXXYYYYYb 622 * - YYYYY : Flag position in the register 623 * - XXX : Register index 624 * - 001: CR register 625 * - 010: CSR register 626 * - 011: CRRCR register (*) 627 * (*) Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx 628 * @{ 629 */ 630 /* Flags in the CR register */ 631 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ 632 #define RCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIDIVF_Pos)) /*!< HSI16 divider flag */ 633 #define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */ 634 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ 635 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ 636 /* Flags in the CSR register */ 637 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ 638 #define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ 639 #define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSECSSD_Pos)) /*!< CSS on LSE failure Detection */ 640 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_Pos)) /*!< Options bytes loading reset flag */ 641 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 642 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ 643 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 644 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 645 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 646 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 647 #if defined(RCC_CSR_FWRSTF) 648 #define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_FWRSTF_Pos)) /*!< RCC flag FW reset */ 649 #endif /* RCC_CSR_FWRSTF */ 650 /* Flags in the CRRCR register */ 651 #if defined(RCC_HSI48_SUPPORT) 652 #define RCC_FLAG_HSI48RDY ((uint8_t)((CRRCR_REG_INDEX << 5) | RCC_CRRCR_HSI48RDY_Pos)) /*!< HSI48 clock ready flag */ 653 #endif /* RCC_HSI48_SUPPORT */ 654 655 /** 656 * @} 657 */ 658 659 /** 660 * @} 661 */ 662 663 /* Exported macro ------------------------------------------------------------*/ 664 665 /** @defgroup RCC_Exported_Macros RCC Exported Macros 666 * @{ 667 */ 668 669 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 670 * @brief Enable or disable the AHB peripheral clock. 671 * @note After reset, the peripheral clock (used for registers read/write access) 672 * is disabled and the application software has to enable this clock before 673 * using it. 674 * @{ 675 */ 676 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 677 __IO uint32_t tmpreg; \ 678 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 679 /* Delay after an RCC peripheral clock enabling */ \ 680 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 681 UNUSED(tmpreg); \ 682 } while(0) 683 684 #define __HAL_RCC_MIF_CLK_ENABLE() do { \ 685 __IO uint32_t tmpreg; \ 686 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 687 /* Delay after an RCC peripheral clock enabling */ \ 688 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 689 UNUSED(tmpreg); \ 690 } while(0) 691 692 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 693 __IO uint32_t tmpreg; \ 694 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 695 /* Delay after an RCC peripheral clock enabling */ \ 696 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 697 UNUSED(tmpreg); \ 698 } while(0) 699 700 701 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 702 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) 703 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 704 705 /** 706 * @} 707 */ 708 709 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable 710 * @brief Enable or disable the IOPORT peripheral clock. 711 * @note After reset, the peripheral clock (used for registers read/write access) 712 * is disabled and the application software has to enable this clock before 713 * using it. 714 * @{ 715 */ 716 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 717 __IO uint32_t tmpreg; \ 718 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ 719 /* Delay after an RCC peripheral clock enabling */ \ 720 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ 721 UNUSED(tmpreg); \ 722 } while(0) 723 724 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 725 __IO uint32_t tmpreg; \ 726 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ 727 /* Delay after an RCC peripheral clock enabling */ \ 728 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ 729 UNUSED(tmpreg); \ 730 } while(0) 731 732 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 733 __IO uint32_t tmpreg; \ 734 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ 735 /* Delay after an RCC peripheral clock enabling */ \ 736 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ 737 UNUSED(tmpreg); \ 738 } while(0) 739 740 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 741 __IO uint32_t tmpreg; \ 742 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ 743 /* Delay after an RCC peripheral clock enabling */ \ 744 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ 745 UNUSED(tmpreg); \ 746 } while(0) 747 748 749 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 750 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 751 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 752 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) 753 754 /** 755 * @} 756 */ 757 758 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 759 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 760 * @note After reset, the peripheral clock (used for registers read/write access) 761 * is disabled and the application software has to enable this clock before 762 * using it. 763 * @{ 764 */ 765 #define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN)) 766 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN)) 767 768 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN)) 769 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN)) 770 /** 771 * @} 772 */ 773 774 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 775 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 776 * @note After reset, the peripheral clock (used for registers read/write access) 777 * is disabled and the application software has to enable this clock before 778 * using it. 779 * @{ 780 */ 781 #define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN)) 782 #define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN)) 783 784 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN)) 785 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN)) 786 /** 787 * @} 788 */ 789 790 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status 791 * @brief Check whether the AHB peripheral clock is enabled or not. 792 * @note After reset, the peripheral clock (used for registers read/write access) 793 * is disabled and the application software has to enable this clock before 794 * using it. 795 * @{ 796 */ 797 798 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U) 799 #define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != 0U) 800 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U) 801 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U) 802 #define __HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == 0U) 803 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U) 804 805 /** 806 * @} 807 */ 808 809 /** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status 810 * @brief Check whether the IOPORT peripheral clock is enabled or not. 811 * @note After reset, the peripheral clock (used for registers read/write access) 812 * is disabled and the application software has to enable this clock before 813 * using it. 814 * @{ 815 */ 816 817 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U) 818 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U) 819 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U) 820 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != 0U) 821 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U) 822 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U) 823 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U) 824 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == 0U) 825 826 /** 827 * @} 828 */ 829 830 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 831 * @brief Check whether the APB1 peripheral clock is enabled or not. 832 * @note After reset, the peripheral clock (used for registers read/write access) 833 * is disabled and the application software has to enable this clock before 834 * using it. 835 * @{ 836 */ 837 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U) 838 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U) 839 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U) 840 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U) 841 842 /** 843 * @} 844 */ 845 846 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 847 * @brief Check whether the APB2 peripheral clock is enabled or not. 848 * @note After reset, the peripheral clock (used for registers read/write access) 849 * is disabled and the application software has to enable this clock before 850 * using it. 851 * @{ 852 */ 853 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 854 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != 0U) 855 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 856 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == 0U) 857 858 /** 859 * @} 860 */ 861 862 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 863 * @brief Force or release AHB peripheral reset. 864 * @{ 865 */ 866 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 867 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) 868 #define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) 869 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) 870 871 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) 872 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) 873 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) 874 #define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) 875 /** 876 * @} 877 */ 878 879 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset 880 * @brief Force or release IOPORT peripheral reset. 881 * @{ 882 */ 883 #define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU) 884 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) 885 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) 886 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) 887 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST)) 888 889 #define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U) 890 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) 891 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) 892 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) 893 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST)) 894 895 /** 896 * @} 897 */ 898 899 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 900 * @brief Force or release APB1 peripheral reset. 901 * @{ 902 */ 903 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 904 #define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) 905 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) 906 907 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) 908 #define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) 909 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) 910 911 /** 912 * @} 913 */ 914 915 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 916 * @brief Force or release APB2 peripheral reset. 917 * @{ 918 */ 919 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 920 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) 921 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) 922 923 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) 924 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) 925 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) 926 /** 927 * @} 928 */ 929 930 931 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable 932 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. 933 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 934 * power consumption. 935 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 936 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 937 * @{ 938 */ 939 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN)) 940 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN)) 941 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN)) 942 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN)) 943 944 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN)) 945 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN)) 946 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN)) 947 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN)) 948 /** 949 * @} 950 */ 951 952 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable 953 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. 954 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 955 * power consumption. 956 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 957 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 958 * @{ 959 */ 960 961 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN)) 962 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN)) 963 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN)) 964 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN)) 965 966 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN)) 967 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN)) 968 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN)) 969 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN)) 970 /** 971 * @} 972 */ 973 974 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 975 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 976 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 977 * power consumption. 978 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 979 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 980 * @{ 981 */ 982 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN)) 983 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN)) 984 985 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN)) 986 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN)) 987 988 /** 989 * @} 990 */ 991 992 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 993 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 994 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 995 * power consumption. 996 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 997 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 998 * @{ 999 */ 1000 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN)) 1001 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN)) 1002 1003 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN)) 1004 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN)) 1005 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status 1011 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. 1012 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1013 * power consumption. 1014 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1015 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1016 * @{ 1017 */ 1018 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0U) 1019 #define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0U) 1020 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != 0U) 1021 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != 0U) 1022 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == 0U) 1023 #define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == 0U) 1024 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == 0U) 1025 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == 0U) 1026 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status 1032 * @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not. 1033 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1034 * power consumption. 1035 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1036 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1037 * @{ 1038 */ 1039 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != 0U) 1040 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != 0U) 1041 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != 0U) 1042 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != 0U) 1043 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == 0U) 1044 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == 0U) 1045 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == 0U) 1046 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == 0U) 1047 1048 /** 1049 * @} 1050 */ 1051 1052 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 1053 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1054 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1055 * power consumption. 1056 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1057 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1058 * @{ 1059 */ 1060 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != 0U) 1061 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != 0U) 1062 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == 0U) 1063 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == 0U) 1064 1065 /** 1066 * @} 1067 */ 1068 1069 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 1070 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1071 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1072 * power consumption. 1073 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1074 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1075 * @{ 1076 */ 1077 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 1078 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != 0U) 1079 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 1080 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == 0U) 1081 1082 /** 1083 * @} 1084 */ 1085 /** @defgroup RCC_HSI_Configuration HSI Configuration 1086 * @{ 1087 */ 1088 1089 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 1090 * @note After enabling the HSI, the application software should wait on 1091 * HSIRDY flag to be set indicating that HSI clock is stable and can 1092 * be used to clock the PLL and/or system clock. 1093 * @note HSI can not be stopped if it is used directly or through the PLL 1094 * as system clock. In this case, you have to select another source 1095 * of the system clock then stop the HSI. 1096 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1097 * @param __STATE__ specifies the new state of the HSI. 1098 * This parameter can be one of the following values: 1099 * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator 1100 * @arg @ref RCC_HSI_ON turn ON the HSI oscillator 1101 * @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 1102 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1103 * clock cycles. 1104 */ 1105 #define __HAL_RCC_HSI_CONFIG(__STATE__) \ 1106 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__)) 1107 1108 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 1109 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1110 * It is used (enabled by hardware) as system clock source after startup 1111 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1112 * of the HSE used directly or indirectly as system clock (if the Clock 1113 * Security System CSS is enabled). 1114 * @note HSI can not be stopped if it is used as system clock source. In this case, 1115 * you have to select another source of the system clock then stop the HSI. 1116 * @note After enabling the HSI, the application software should wait on HSIRDY 1117 * flag to be set indicating that HSI clock is stable and can be used as 1118 * system clock source. 1119 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1120 * clock cycles. 1121 */ 1122 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 1123 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 1124 1125 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1126 * @note The calibration is used to compensate for the variations in voltage 1127 * and temperature that influence the frequency of the internal HSI RC. 1128 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 1129 * (default is RCC_HSICALIBRATION_DEFAULT). 1130 * This parameter must be a number between 0 and 0x1F. 1131 */ 1132 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 1133 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos)) 1134 1135 /** 1136 * @} 1137 */ 1138 1139 /** @defgroup RCC_LSI_Configuration LSI Configuration 1140 * @{ 1141 */ 1142 1143 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 1144 * @note After enabling the LSI, the application software should wait on 1145 * LSIRDY flag to be set indicating that LSI clock is stable and can 1146 * be used to clock the IWDG and/or the RTC. 1147 */ 1148 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 1149 1150 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 1151 * @note LSI can not be disabled if the IWDG is running. 1152 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1153 * clock cycles. 1154 */ 1155 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 1156 1157 /** 1158 * @} 1159 */ 1160 1161 /** @defgroup RCC_HSE_Configuration HSE Configuration 1162 * @{ 1163 */ 1164 1165 /** 1166 * @brief Macro to configure the External High Speed oscillator (HSE). 1167 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1168 * supported by this macro. User should request a transition to HSE Off 1169 * first and then HSE On or HSE Bypass. 1170 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1171 * software should wait on HSERDY flag to be set indicating that HSE clock 1172 * is stable and can be used to clock the PLL and/or system clock. 1173 * @note HSE state can not be changed if it is used directly or through the 1174 * PLL as system clock. In this case, you have to select another source 1175 * of the system clock then change the HSE state (ex. disable it). 1176 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1177 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1178 * was previously enabled you have to enable it again after calling this 1179 * function. 1180 * @param __STATE__ specifies the new state of the HSE. 1181 * This parameter can be one of the following values: 1182 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 1183 * 6 HSE oscillator clock cycles. 1184 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 1185 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 1186 */ 1187 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1188 do{ \ 1189 __IO uint32_t tmpreg; \ 1190 if ((__STATE__) == RCC_HSE_ON) \ 1191 { \ 1192 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1193 } \ 1194 else if ((__STATE__) == RCC_HSE_BYPASS) \ 1195 { \ 1196 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1197 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1198 } \ 1199 else \ 1200 { \ 1201 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1202 /* Delay after an RCC peripheral clock */ \ 1203 tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ 1204 UNUSED(tmpreg); \ 1205 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1206 } \ 1207 }while(0) 1208 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup RCC_LSE_Configuration LSE Configuration 1214 * @{ 1215 */ 1216 1217 /** 1218 * @brief Macro to configure the External Low Speed oscillator (LSE). 1219 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1220 * @note As the LSE is in the Backup domain and write access is denied to 1221 * this domain after reset, you have to enable write access using 1222 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1223 * (to be done once after reset). 1224 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1225 * software should wait on LSERDY flag to be set indicating that LSE clock 1226 * is stable and can be used to clock the RTC. 1227 * @param __STATE__ specifies the new state of the LSE. 1228 * This parameter can be one of the following values: 1229 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 1230 * 6 LSE oscillator clock cycles. 1231 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 1232 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1233 */ 1234 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1235 do{ \ 1236 if ((__STATE__) == RCC_LSE_ON) \ 1237 { \ 1238 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1239 } \ 1240 else if ((__STATE__) == RCC_LSE_OFF) \ 1241 { \ 1242 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1243 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1244 } \ 1245 else if ((__STATE__) == RCC_LSE_BYPASS) \ 1246 { \ 1247 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1248 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1249 } \ 1250 else \ 1251 { \ 1252 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1253 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1254 } \ 1255 }while(0) 1256 1257 /** 1258 * @} 1259 */ 1260 1261 /** @defgroup RCC_MSI_Configuration MSI Configuration 1262 * @{ 1263 */ 1264 1265 /** @brief Macro to enable Internal Multi Speed oscillator (MSI). 1266 * @note After enabling the MSI, the application software should wait on MSIRDY 1267 * flag to be set indicating that MSI clock is stable and can be used as 1268 * system clock source. 1269 */ 1270 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 1271 1272 /** @brief Macro to disable the Internal Multi Speed oscillator (MSI). 1273 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 1274 * It is used (enabled by hardware) as system clock source after startup 1275 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1276 * of the HSE used directly or indirectly as system clock (if the Clock 1277 * Security System CSS is enabled). 1278 * @note MSI can not be stopped if it is used as system clock source. In this case, 1279 * you have to select another source of the system clock then stop the MSI. 1280 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 1281 * clock cycles. 1282 */ 1283 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 1284 1285 /** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. 1286 * @note The calibration is used to compensate for the variations in voltage 1287 * and temperature that influence the frequency of the internal MSI RC. 1288 * Refer to the Application Note AN3300 for more details on how to 1289 * calibrate the MSI. 1290 * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. 1291 * (default is RCC_MSICALIBRATION_DEFAULT). 1292 * This parameter must be a number between 0 and 0xFF. 1293 */ 1294 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ 1295 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos)) 1296 1297 /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. 1298 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is 1299 * around 2.097 MHz. The MSI clock does not change after wake-up from 1300 * STOP mode. 1301 * @note The MSI clock range can be modified on the fly. 1302 * @param _MSIRANGEVALUE_ specifies the MSI Clock range. 1303 * This parameter must be one of the following values: 1304 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1305 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1306 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1307 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1308 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1309 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1310 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1311 */ 1312 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ 1313 RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) 1314 1315 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 1316 * @retval MSI clock range. 1317 * This parameter must be one of the following values: 1318 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1319 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1320 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1321 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1322 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1323 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1324 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1325 */ 1326 #define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) 1327 1328 /** 1329 * @} 1330 */ 1331 1332 /** @defgroup RCC_PLL_Configuration PLL Configuration 1333 * @{ 1334 */ 1335 1336 /** @brief Macro to enable the main PLL. 1337 * @note After enabling the main PLL, the application software should wait on 1338 * PLLRDY flag to be set indicating that PLL clock is stable and can 1339 * be used as system clock source. 1340 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1341 */ 1342 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 1343 1344 /** @brief Macro to disable the main PLL. 1345 * @note The main PLL can not be disabled if it is used as system clock source 1346 */ 1347 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 1348 1349 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 1350 * @note This function must be used only when the main PLL is disabled. 1351 * 1352 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 1353 * This parameter can be one of the following values: 1354 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1355 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1356 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 1357 * This parameter can be one of the following values: 1358 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 1359 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 1360 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 1361 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 1362 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 1363 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 1364 * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 1365 * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 1366 * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 1367 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in Range 1, 1368 * 48 MHz when the product is in Range 2and 24 MHz when the product is in Range 3. 1369 * 1370 * @param __PLLDIV__ specifies the division factor for PLL VCO input clock 1371 * This parameter can be one of the following values: 1372 * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2 1373 * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3 1374 * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4 1375 * 1376 */ 1377 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ 1378 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) 1379 1380 /** @brief Get oscillator clock selected as PLL input clock 1381 * @retval The clock source used for PLL entry. The returned value can be one 1382 * of the following: 1383 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock 1384 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 1385 */ 1386 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 1387 1388 /** 1389 * @} 1390 */ 1391 1392 /** @defgroup RCC_Get_Clock_source Get Clock source 1393 * @{ 1394 */ 1395 1396 /** 1397 * @brief Macro to configure the system clock source. 1398 * @param __SYSCLKSOURCE__ specifies the system clock source. 1399 * This parameter can be one of the following values: 1400 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 1401 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1402 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1403 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 1404 */ 1405 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1406 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1407 1408 /** @brief Macro to get the clock source used as system clock. 1409 * @retval The clock source used as system clock. The returned value can be one 1410 * of the following: 1411 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock 1412 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 1413 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 1414 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 1415 */ 1416 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 1417 1418 /** 1419 * @} 1420 */ 1421 1422 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1423 * @{ 1424 */ 1425 1426 /** @brief Macro to configure the MCO clock. 1427 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1428 * This parameter can be one of the following values: 1429 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1430 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1431 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock 1432 * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock 1433 * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock 1434 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock 1435 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock 1436 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock 1437 @if STM32L052xx 1438 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1439 @elseif STM32L053xx 1440 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1441 @elseif STM32L062xx 1442 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1443 @elseif STM32L063xx 1444 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1445 @elseif STM32L072xx 1446 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1447 @elseif STM32L073xx 1448 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1449 @elseif STM32L082xx 1450 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1451 @elseif STM32L083xx 1452 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1453 @endif 1454 * @param __MCODIV__ specifies the MCO clock prescaler. 1455 * This parameter can be one of the following values: 1456 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1457 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1458 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1459 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1460 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1461 */ 1462 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1463 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1464 1465 /** 1466 * @} 1467 */ 1468 1469 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1470 * @{ 1471 */ 1472 1473 /** @brief Macro to configure the RTC clock (RTCCLK). 1474 * @note As the RTC clock configuration bits are in the Backup domain and write 1475 * access is denied to this domain after reset, you have to enable write 1476 * access using the Power Backup Access macro before to configure 1477 * the RTC clock source (to be done once after reset). 1478 * @note Once the RTC clock is configured it cannot be changed unless the 1479 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1480 * a Power On Reset (POR). 1481 * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). 1482 * 1483 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1484 * This parameter can be one of the following values: 1485 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1486 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1487 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1488 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock 1489 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock 1490 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock 1491 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock 1492 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1493 * work in STOP and STANDBY modes, and can be used as wakeup source. 1494 * However, when the HSE clock is used as RTC clock source, the RTC 1495 * cannot be used in STOP and STANDBY modes. 1496 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1497 * RTC clock source). 1498 */ 1499 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ 1500 if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ 1501 { \ 1502 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ 1503 } \ 1504 } while (0) 1505 1506 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ 1507 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ 1508 RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ 1509 } while (0) 1510 1511 /** @brief Macro to get the RTC clock source. 1512 * @retval The clock source can be one of the following values: 1513 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1514 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1515 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1516 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1517 */ 1518 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) 1519 1520 /** 1521 * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). 1522 * 1523 * @retval Returned value can be one of the following values: 1524 * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock 1525 * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock 1526 * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock 1527 * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock 1528 * 1529 */ 1530 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) 1531 1532 /** @brief Macro to enable the the RTC clock. 1533 * @note These macros must be used only after the RTC clock source was selected. 1534 */ 1535 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN) 1536 1537 /** @brief Macro to disable the the RTC clock. 1538 * @note These macros must be used only after the RTC clock source was selected. 1539 */ 1540 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN) 1541 1542 /** @brief Macro to force the Backup domain reset. 1543 * @note This function resets the RTC peripheral (including the backup registers) 1544 * and the RTC clock source selection in RCC_CSR register. 1545 * @note The BKPSRAM is not affected by this reset. 1546 */ 1547 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST) 1548 1549 /** @brief Macros to release the Backup domain reset. 1550 */ 1551 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST) 1552 1553 /** 1554 * @} 1555 */ 1556 1557 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1558 * @brief macros to manage the specified RCC Flags and interrupts. 1559 * @{ 1560 */ 1561 1562 /** @brief Enable RCC interrupt. 1563 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled 1564 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is 1565 * automatically generated. The NMI will be executed indefinitely, and 1566 * since NMI has higher priority than any other IRQ (and main program) 1567 * the application will be stacked in the NMI ISR unless the CSS interrupt 1568 * pending bit is cleared. 1569 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1570 * This parameter can be any combination of the following values: 1571 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1572 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1573 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1574 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1575 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1576 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1577 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1578 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1579 */ 1580 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 1581 1582 /** @brief Disable RCC interrupt. 1583 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled 1584 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is 1585 * automatically generated. The NMI will be executed indefinitely, and 1586 * since NMI has higher priority than any other IRQ (and main program) 1587 * the application will be stacked in the NMI ISR unless the CSS interrupt 1588 * pending bit is cleared. 1589 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1590 * This parameter can be any combination of the following values: 1591 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1592 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1593 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1594 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1595 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1596 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1597 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1598 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1599 */ 1600 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 1601 1602 /** @brief Clear the RCC's interrupt pending bits. 1603 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1604 * This parameter can be any combination of the following values: 1605 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1606 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1607 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1608 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1609 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1610 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1611 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1612 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1613 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1614 */ 1615 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 1616 1617 /** @brief Check the RCC's interrupt has occurred or not. 1618 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1619 * This parameter can be one of the following values: 1620 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1621 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1622 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1623 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1624 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 1625 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1626 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1627 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1628 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1629 */ 1630 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 1631 1632 1633 /** @brief Set RMVF bit to clear the reset flags. 1634 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1635 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1636 */ 1637 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1638 1639 /** @brief Check RCC flag is set or not. 1640 * @param __FLAG__ specifies the flag to check. 1641 * This parameter can be one of the following values: 1642 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 1643 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices) 1644 * @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag 1645 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 1646 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 1647 * @arg @ref RCC_FLAG_PLLRDY PLL clock ready 1648 * @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected 1649 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 1650 * @arg @ref RCC_FLAG_FWRST Firewall reset 1651 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 1652 * @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset 1653 * @arg @ref RCC_FLAG_PINRST Pin reset 1654 * @arg @ref RCC_FLAG_PORRST POR/PDR reset 1655 * @arg @ref RCC_FLAG_SFTRST Software reset 1656 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 1657 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 1658 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 1659 * @retval The new state of __FLAG__ (TRUE or FALSE). 1660 */ 1661 #if defined(RCC_HSI48_SUPPORT) 1662 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U ) 1663 #else 1664 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U ) 1665 #endif /* RCC_HSI48_SUPPORT */ 1666 1667 /** 1668 * @} 1669 */ 1670 1671 /** 1672 * @} 1673 */ 1674 1675 /* Include RCC HAL Extension module */ 1676 #include "stm32l0xx_hal_rcc_ex.h" 1677 1678 /* Exported functions --------------------------------------------------------*/ 1679 /** @addtogroup RCC_Exported_Functions 1680 * @{ 1681 */ 1682 1683 /** @addtogroup RCC_Exported_Functions_Group1 1684 * @{ 1685 */ 1686 1687 /* Initialization and de-initialization functions ******************************/ 1688 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1689 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1690 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1691 1692 /** 1693 * @} 1694 */ 1695 1696 /** @addtogroup RCC_Exported_Functions_Group2 1697 * @{ 1698 */ 1699 1700 /* Peripheral Control functions ************************************************/ 1701 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1702 #if defined(RCC_HSECSS_SUPPORT) 1703 void HAL_RCC_EnableCSS(void); 1704 /* CSS NMI IRQ handler */ 1705 void HAL_RCC_NMI_IRQHandler(void); 1706 /* User Callbacks in non blocking mode (IT mode) */ 1707 void HAL_RCC_CSSCallback(void); 1708 #endif /* RCC_HSECSS_SUPPORT */ 1709 uint32_t HAL_RCC_GetSysClockFreq(void); 1710 uint32_t HAL_RCC_GetHCLKFreq(void); 1711 uint32_t HAL_RCC_GetPCLK1Freq(void); 1712 uint32_t HAL_RCC_GetPCLK2Freq(void); 1713 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1714 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1715 1716 /** 1717 * @} 1718 */ 1719 1720 /** 1721 * @} 1722 */ 1723 1724 /** 1725 * @} 1726 */ 1727 1728 /** 1729 * @} 1730 */ 1731 1732 #ifdef __cplusplus 1733 } 1734 #endif 1735 1736 #endif /* __STM32L0xx_HAL_RCC_H */ 1737 1738 1739
