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Searched refs:Instance (Results 1 – 25 of 1549) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_dma.h138 …void *Instance; … member
690 …NDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->I…
698 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)-…
699 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
707 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)-…
708 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
719 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
720 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
401 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); in HAL_DSI_Init()
404 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); in HAL_DSI_Init()
405 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); in HAL_DSI_Init()
408 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
409 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
414 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
[all …]
Dstm32f4xx_hal_cryp.c322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR…
323 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_…
330 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_Init()
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_Init()
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_SetConfig()
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_SetConfig()
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); in HAL_CRYP_Encrypt()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
401 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); in HAL_DSI_Init()
404 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); in HAL_DSI_Init()
405 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); in HAL_DSI_Init()
408 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
409 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
414 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
[all …]
Dstm32h7xx_hal_adc.c423 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
486 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
489 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
496 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
499 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
514 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
529 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
545 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
547 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) in HAL_ADC_Init()
566 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); in HAL_ADC_Init()
[all …]
Dstm32h7xx_hal_adc_ex.c132 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_Start()
152 LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); in HAL_ADCEx_Calibration_Start()
155 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) in HAL_ADCEx_Calibration_Start()
203 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_GetValue()
207 return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); in HAL_ADCEx_Calibration_GetValue()
223 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_LinearCalibration_GetValue()
226 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
233 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
235 LL_ADC_REG_StopConversion(hadc->Instance); in HAL_ADCEx_LinearCalibration_GetValue()
240 …LinearCalib_Buffer[cnt - 1U] = LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW… in HAL_ADCEx_LinearCalibration_GetValue()
[all …]
Dstm32h7xx_hal_cryp.c320 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR…
321 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
324 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
458 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_Init()
571 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_SetConfig()
945 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); in HAL_CRYP_Encrypt()
948 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; in HAL_CRYP_Encrypt()
958 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); in HAL_CRYP_Encrypt()
959 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); in HAL_CRYP_Encrypt()
962 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); in HAL_CRYP_Encrypt()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
401 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); in HAL_DSI_Init()
404 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); in HAL_DSI_Init()
405 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); in HAL_DSI_Init()
408 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
409 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
414 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
[all …]
Dstm32f7xx_hal_cryp.c322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR…
323 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_…
330 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_Init()
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_Init()
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_SetConfig()
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_SetConfig()
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); in HAL_CRYP_Encrypt()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
401 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); in HAL_DSI_Init()
404 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); in HAL_DSI_Init()
405 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); in HAL_DSI_Init()
408 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
409 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
414 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
[all …]
Dstm32l4xx_hal_cryp_ex.c308 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_IT()
310 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_IT()
312 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_IT()
314 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_IT()
534 …MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataTy… in HAL_CRYPEx_AES_Auth()
539 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); in HAL_CRYPEx_AES_Auth()
557 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_Auth()
559 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_Auth()
561 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_Auth()
563 hcryp->Instance->DINR = *(uint32_t*)(inputaddr); in HAL_CRYPEx_AES_Auth()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dsi.c263 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
274 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
289 hdsi->Instance->DPCBCR &= ~DSI_DPCBCR; in DSI_ConfigBandControl()
290 hdsi->Instance->DPCBCR |= (hdsi->Init.PHYFrequencyRange << DSI_DPCBCR_Pos); in DSI_ConfigBandControl()
293 hdsi->Instance->DPCSRCR = DSI_DPHY_SLEW_HS_TX_SPEED; in DSI_ConfigBandControl()
296 hdsi->Instance->DPDL0BCR &= ~DSI_DPDL0BCR; in DSI_ConfigBandControl()
297 hdsi->Instance->DPDL0BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL0BCR_Pos); in DSI_ConfigBandControl()
300 hdsi->Instance->DPDL0SRCR = DSI_DPHY_SLEW_HS_TX_SPEED; in DSI_ConfigBandControl()
303 hdsi->Instance->DPDL1BCR &= ~DSI_DPDL1BCR; in DSI_ConfigBandControl()
304 hdsi->Instance->DPDL1BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL1BCR_Pos); in DSI_ConfigBandControl()
[all …]
Dstm32u5xx_hal_mdf.c312 assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); in HAL_MDF_Init()
317 if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL) in HAL_MDF_Init()
325 if (IS_ADF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
353 if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) || in HAL_MDF_Init()
354 ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance))) in HAL_MDF_Init()
358 mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; in HAL_MDF_Init()
368 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
391 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
415 if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) in HAL_MDF_Init()
425 hmdf->Instance->SITFCR = 0U; in HAL_MDF_Init()
[all …]
Dstm32u5xx_hal_adc.c423 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
429 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
456 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
486 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
518 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
521 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
528 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
531 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
546 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
561 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
[all …]
Dstm32u5xx_hal_pka.c375 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
402 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
414 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
443 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
450 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
453 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
920 PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); in HAL_PKA_ModExp_GetResult()
975 PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); in HAL_PKA_ECDSASign_GetResult()
976 PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); in HAL_PKA_ECDSASign_GetResult()
983 PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); in HAL_PKA_ECDSASign_GetResult()
[all …]
Dstm32u5xx_hal_adc_ex.c144 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_Start()
160 if (hadc->Instance == ADC4) in HAL_ADCEx_Calibration_Start()
170 backup_setting_pwrr = READ_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF); in HAL_ADCEx_Calibration_Start()
171 backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG); in HAL_ADCEx_Calibration_Start()
172 CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG); in HAL_ADCEx_Calibration_Start()
173 CLEAR_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF); in HAL_ADCEx_Calibration_Start()
176 LL_ADC_StartCalibration(hadc->Instance, LL_ADC_CALIB_OFFSET); in HAL_ADCEx_Calibration_Start()
179 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) in HAL_ADCEx_Calibration_Start()
194 SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); in HAL_ADCEx_Calibration_Start()
195 SET_BIT(hadc->Instance->PWRR, backup_setting_pwrr); in HAL_ADCEx_Calibration_Start()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_opamp_ex.c159 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
160 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
161 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
163 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
164 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
165 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
167 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
172 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
173 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
174 SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
Dstm32g4xx_hal_adc.c411 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
477 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
480 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
487 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
490 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
505 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
520 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
536 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
538 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) in HAL_ADC_Init()
557 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); in HAL_ADC_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_opamp_ex.c109 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
110 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
114 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
115 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
118 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); in HAL_OPAMPEx_SelfCalibrateAll()
119 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); in HAL_OPAMPEx_SelfCalibrateAll()
122 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON); in HAL_OPAMPEx_SelfCalibrateAll()
123 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON); in HAL_OPAMPEx_SelfCalibrateAll()
127 MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); in HAL_OPAMPEx_SelfCalibrateAll()
128 MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_pka.c375 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
402 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
414 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
443 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
450 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
453 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
920 PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); in HAL_PKA_ModExp_GetResult()
975 PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); in HAL_PKA_ECDSASign_GetResult()
976 PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); in HAL_PKA_ECDSASign_GetResult()
983 PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); in HAL_PKA_ECDSASign_GetResult()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_pka.c375 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
402 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
414 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
443 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
450 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
453 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
920 PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); in HAL_PKA_ModExp_GetResult()
975 PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); in HAL_PKA_ECDSASign_GetResult()
976 PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); in HAL_PKA_ECDSASign_GetResult()
983 PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); in HAL_PKA_ECDSASign_GetResult()
[all …]
Dstm32h5xx_hal_adc.c408 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
473 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
476 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
483 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
486 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
501 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
516 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
532 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
534 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) in HAL_ADC_Init()
553 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); in HAL_ADC_Init()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_adc.c409 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
472 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
475 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
482 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
485 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
500 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
515 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
531 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
533 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) in HAL_ADC_Init()
552 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); in HAL_ADC_Init()
[all …]
Dstm32mp1xx_hal_adc_ex.c130 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_Start()
150 LL_ADC_StartCalibration(hadc->Instance , CalibrationMode, SingleDiff ); in HAL_ADCEx_Calibration_Start()
153 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) in HAL_ADCEx_Calibration_Start()
198 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_GetValue()
202 return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); in HAL_ADCEx_Calibration_GetValue()
218 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_LinearCalibration_GetValue()
221 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
228 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
230 LL_ADC_REG_StopConversion(hadc->Instance); in HAL_ADCEx_LinearCalibration_GetValue()
235 …LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >>… in HAL_ADCEx_LinearCalibration_GetValue()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_dma.h115 …DMA_Channel_TypeDef *Instance; /*!< Register b… member
498 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
505 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
518 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
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