1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_DMA_H 21 #define STM32H7xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @brief DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Request; /*!< Specifies the request selected for the specified stream. 51 This parameter can be a value of @ref DMA_Request_selection */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Stream */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 77 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 78 This parameter can be a value of @ref DMA_FIFO_direct_mode 79 @note The Direct mode (FIFO mode disabled) cannot be used if the 80 memory-to-memory data transfer is configured on the selected stream */ 81 82 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 83 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 84 85 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 86 It specifies the amount of data to be transferred in a single non interruptible 87 transaction. 88 This parameter can be a value of @ref DMA_Memory_burst 89 @note The burst mode is possible only if the address Increment mode is enabled. */ 90 91 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 92 It specifies the amount of data to be transferred in a single non interruptible 93 transaction. 94 This parameter can be a value of @ref DMA_Peripheral_burst 95 @note The burst mode is possible only if the address Increment mode is enabled. */ 96 }DMA_InitTypeDef; 97 98 /** 99 * @brief HAL DMA State structures definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 104 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 105 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 106 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 107 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 108 }HAL_DMA_StateTypeDef; 109 110 /** 111 * @brief HAL DMA Transfer complete level structure definition 112 */ 113 typedef enum 114 { 115 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 116 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 117 }HAL_DMA_LevelCompleteTypeDef; 118 119 /** 120 * @brief HAL DMA Callbacks IDs structure definition 121 */ 122 typedef enum 123 { 124 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 125 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 126 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 127 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 128 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 129 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 130 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 131 }HAL_DMA_CallbackIDTypeDef; 132 133 /** 134 * @brief DMA handle Structure definition 135 */ 136 typedef struct __DMA_HandleTypeDef 137 { 138 void *Instance; /*!< Register base address */ 139 140 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 141 142 HAL_LockTypeDef Lock; /*!< DMA locking object */ 143 144 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 145 146 void *Parent; /*!< Parent object state */ 147 148 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 149 150 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 151 152 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 153 154 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 155 156 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 157 158 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 159 160 __IO uint32_t ErrorCode; /*!< DMA Error code */ 161 162 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 163 164 uint32_t StreamIndex; /*!< DMA Stream Index */ 165 166 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ 167 168 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 169 170 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 171 172 173 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 174 175 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ 176 177 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 178 179 }DMA_HandleTypeDef; 180 181 /** 182 * @} 183 */ 184 185 186 /* Exported constants --------------------------------------------------------*/ 187 188 /** @defgroup DMA_Exported_Constants DMA Exported Constants 189 * @brief DMA Exported constants 190 * @{ 191 */ 192 193 /** @defgroup DMA_Error_Code DMA Error Code 194 * @brief DMA Error Code 195 * @{ 196 */ 197 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 198 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 199 #define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ 200 #define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ 201 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 202 #define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ 203 #define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ 204 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 205 #define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ 206 #define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ 207 #define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ 208 209 /** 210 * @} 211 */ 212 213 /** @defgroup DMA_Request_selection DMA Request selection 214 * @brief DMA Request selection 215 * @{ 216 */ 217 /* DMAMUX1 requests */ 218 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 219 220 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 221 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 222 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 223 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 224 #define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ 225 #define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ 226 #define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ 227 #define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ 228 229 #define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ 230 #define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ 231 232 #define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ 233 #define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ 234 #define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ 235 #define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ 236 #define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ 237 #define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ 238 #define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ 239 240 #define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ 241 #define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ 242 #define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ 243 #define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ 244 #define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ 245 246 #define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ 247 #define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ 248 #define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ 249 #define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ 250 #define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ 251 #define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ 252 253 #define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ 254 #define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ 255 #define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ 256 #define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ 257 258 #define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ 259 #define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ 260 #define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ 261 #define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ 262 263 #define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ 264 #define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ 265 #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ 266 #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ 267 268 #define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ 269 #define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ 270 #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ 271 #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ 272 #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ 273 #define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ 274 275 #define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ 276 #define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ 277 #define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ 278 #define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ 279 #define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ 280 #define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ 281 #define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ 282 283 #define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ 284 #define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ 285 #define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ 286 #define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ 287 #define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ 288 #define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ 289 290 #define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ 291 #define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ 292 293 #define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ 294 #define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ 295 #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ 296 #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ 297 298 #define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ 299 #define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ 300 301 #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ 302 #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ 303 304 #define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ 305 #define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ 306 307 #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ 308 #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ 309 310 #if defined (PSSI) 311 #define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ 312 #define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */ 313 #else 314 #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ 315 #endif /* PSSI */ 316 317 #define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ 318 #define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ 319 320 #define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ 321 322 #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ 323 #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ 324 #define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ 325 #define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ 326 327 #define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ 328 #define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ 329 #define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ 330 #define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ 331 332 #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ 333 #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ 334 335 #if defined(SAI2) 336 #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ 337 #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ 338 #endif /* SAI2 */ 339 340 #define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ 341 #define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ 342 343 #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ 344 #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ 345 346 #if defined(HRTIM1) 347 #define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ 348 #define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ 349 #define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ 350 #define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ 351 #define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ 352 #define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/ 353 #endif /* HRTIM1 */ 354 355 #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ 356 #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ 357 #define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ 358 #define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ 359 360 #define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ 361 #define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ 362 #define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ 363 #define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ 364 365 #define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ 366 #define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ 367 368 #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ 369 #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ 370 371 #if defined(SAI3) 372 #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ 373 #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ 374 #endif /* SAI3 */ 375 376 #if defined(ADC3) 377 #define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ 378 #endif /* ADC3 */ 379 380 #if defined(UART9) 381 #define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */ 382 #define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */ 383 #endif /* UART9 */ 384 385 #if defined(USART10) 386 #define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */ 387 #define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */ 388 #endif /* USART10 */ 389 390 #if defined(FMAC) 391 #define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ 392 #define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ 393 #endif /* FMAC */ 394 395 #if defined(CORDIC) 396 #define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ 397 #define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ 398 #endif /* CORDIC */ 399 400 #if defined(I2C5) 401 #define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ 402 #define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ 403 #endif /* I2C5 */ 404 405 #if defined(TIM23) 406 #define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ 407 #define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ 408 #define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ 409 #define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ 410 #define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ 411 #define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ 412 #endif /* TIM23 */ 413 414 #if defined(TIM24) 415 #define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ 416 #define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ 417 #define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ 418 #define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ 419 #define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ 420 #define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ 421 #endif /* TIM24 */ 422 423 /* DMAMUX2 requests */ 424 #define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 425 #define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ 426 #define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ 427 #define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ 428 #define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ 429 #define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ 430 #define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ 431 #define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ 432 #define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ 433 #define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ 434 #define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ 435 #define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ 436 #define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ 437 #define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ 438 #define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ 439 #if defined(SAI4) 440 #define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ 441 #define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ 442 #endif /* SAI4 */ 443 #if defined(ADC3) 444 #define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ 445 #endif /* ADC3 */ 446 #if defined(DAC2) 447 #define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ 448 #endif /* DAC2 */ 449 #if defined(DFSDM2_Channel0) 450 #define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */ 451 #endif /* DFSDM1_Channel0 */ 452 453 /** 454 * @} 455 */ 456 457 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 458 * @brief DMA data transfer direction 459 * @{ 460 */ 461 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 462 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 463 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 469 * @brief DMA peripheral incremented mode 470 * @{ 471 */ 472 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 473 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 479 * @brief DMA memory incremented mode 480 * @{ 481 */ 482 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 483 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 489 * @brief DMA peripheral data size 490 * @{ 491 */ 492 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ 493 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 494 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup DMA_Memory_data_size DMA Memory data size 500 * @brief DMA memory data size 501 * @{ 502 */ 503 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ 504 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 505 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 506 /** 507 * @} 508 */ 509 510 /** @defgroup DMA_mode DMA mode 511 * @brief DMA mode 512 * @{ 513 */ 514 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 515 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 516 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 517 #define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */ 518 #define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */ 519 /** 520 * @} 521 */ 522 523 /** @defgroup DMA_Priority_level DMA Priority level 524 * @brief DMA priority levels 525 * @{ 526 */ 527 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 528 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 529 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 530 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 536 * @brief DMA FIFO direct mode 537 * @{ 538 */ 539 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ 540 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 546 * @brief DMA FIFO level 547 * @{ 548 */ 549 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ 550 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 551 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 552 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup DMA_Memory_burst DMA Memory burst 558 * @brief DMA memory burst 559 * @{ 560 */ 561 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) 562 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 563 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 564 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 565 /** 566 * @} 567 */ 568 569 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 570 * @brief DMA peripheral burst 571 * @{ 572 */ 573 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) 574 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 575 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 576 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 577 /** 578 * @} 579 */ 580 581 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 582 * @brief DMA interrupts definition 583 * @{ 584 */ 585 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 586 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 587 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 588 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 589 #define DMA_IT_FE ((uint32_t)0x00000080U) 590 /** 591 * @} 592 */ 593 594 /** @defgroup DMA_flag_definitions DMA flag definitions 595 * @brief DMA flag definitions 596 * @{ 597 */ 598 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) 599 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) 600 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) 601 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) 602 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) 603 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) 604 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) 605 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) 606 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) 607 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) 608 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) 609 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) 610 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) 611 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) 612 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) 613 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) 614 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) 615 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) 616 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) 617 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) 618 /** 619 * @} 620 */ 621 622 /** @defgroup BDMA_flag_definitions BDMA flag definitions 623 * @brief BDMA flag definitions 624 * @{ 625 */ 626 #define BDMA_FLAG_GL0 ((uint32_t)0x00000001) 627 #define BDMA_FLAG_TC0 ((uint32_t)0x00000002) 628 #define BDMA_FLAG_HT0 ((uint32_t)0x00000004) 629 #define BDMA_FLAG_TE0 ((uint32_t)0x00000008) 630 #define BDMA_FLAG_GL1 ((uint32_t)0x00000010) 631 #define BDMA_FLAG_TC1 ((uint32_t)0x00000020) 632 #define BDMA_FLAG_HT1 ((uint32_t)0x00000040) 633 #define BDMA_FLAG_TE1 ((uint32_t)0x00000080) 634 #define BDMA_FLAG_GL2 ((uint32_t)0x00000100) 635 #define BDMA_FLAG_TC2 ((uint32_t)0x00000200) 636 #define BDMA_FLAG_HT2 ((uint32_t)0x00000400) 637 #define BDMA_FLAG_TE2 ((uint32_t)0x00000800) 638 #define BDMA_FLAG_GL3 ((uint32_t)0x00001000) 639 #define BDMA_FLAG_TC3 ((uint32_t)0x00002000) 640 #define BDMA_FLAG_HT3 ((uint32_t)0x00004000) 641 #define BDMA_FLAG_TE3 ((uint32_t)0x00008000) 642 #define BDMA_FLAG_GL4 ((uint32_t)0x00010000) 643 #define BDMA_FLAG_TC4 ((uint32_t)0x00020000) 644 #define BDMA_FLAG_HT4 ((uint32_t)0x00040000) 645 #define BDMA_FLAG_TE4 ((uint32_t)0x00080000) 646 #define BDMA_FLAG_GL5 ((uint32_t)0x00100000) 647 #define BDMA_FLAG_TC5 ((uint32_t)0x00200000) 648 #define BDMA_FLAG_HT5 ((uint32_t)0x00400000) 649 #define BDMA_FLAG_TE5 ((uint32_t)0x00800000) 650 #define BDMA_FLAG_GL6 ((uint32_t)0x01000000) 651 #define BDMA_FLAG_TC6 ((uint32_t)0x02000000) 652 #define BDMA_FLAG_HT6 ((uint32_t)0x04000000) 653 #define BDMA_FLAG_TE6 ((uint32_t)0x08000000) 654 #define BDMA_FLAG_GL7 ((uint32_t)0x10000000) 655 #define BDMA_FLAG_TC7 ((uint32_t)0x20000000) 656 #define BDMA_FLAG_HT7 ((uint32_t)0x40000000) 657 #define BDMA_FLAG_TE7 ((uint32_t)0x80000000) 658 659 /** 660 * @} 661 */ 662 663 /** 664 * @} 665 */ 666 667 /* Exported macro ------------------------------------------------------------*/ 668 /** @defgroup DMA_Exported_Macros DMA Exported Macros 669 * @{ 670 */ 671 672 /** @brief Reset DMA handle state 673 * @param __HANDLE__: specifies the DMA handle. 674 * @retval None 675 */ 676 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 677 678 /** 679 * @brief Return the current DMA Stream FIFO filled level. 680 * @param __HANDLE__: DMA handle 681 * @retval The FIFO filling state. 682 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 683 * and not empty. 684 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 685 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 686 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 687 * - DMA_FIFOStatus_Empty: when FIFO is empty 688 * - DMA_FIFOStatus_Full: when FIFO is full 689 */ 690 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) 691 692 /** 693 * @brief Enable the specified DMA Stream. 694 * @param __HANDLE__: DMA handle 695 * @retval None 696 */ 697 #define __HAL_DMA_ENABLE(__HANDLE__) \ 698 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \ 699 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) 700 701 /** 702 * @brief Disable the specified DMA Stream. 703 * @param __HANDLE__: DMA handle 704 * @retval None 705 */ 706 #define __HAL_DMA_DISABLE(__HANDLE__) \ 707 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \ 708 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) 709 710 /* Interrupt & Flag management */ 711 712 /** 713 * @brief Return the current DMA Stream transfer complete flag. 714 * @param __HANDLE__: DMA handle 715 * @retval The specified transfer complete flag index. 716 */ 717 #if defined(BDMA1) 718 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 719 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 720 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 723 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 724 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 725 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 726 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 727 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 728 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 729 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 730 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 731 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ 732 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ 733 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ 734 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ 735 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\ 736 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\ 737 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\ 738 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\ 739 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\ 740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\ 741 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\ 742 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\ 743 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\ 744 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\ 745 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\ 746 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\ 747 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\ 748 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\ 749 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\ 750 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\ 751 (uint32_t)0x00000000) 752 #else 753 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 754 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 755 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 756 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 761 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 762 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 763 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 764 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 765 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 766 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ 767 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ 768 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ 769 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ 770 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\ 771 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\ 772 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\ 773 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\ 774 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\ 775 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\ 776 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ 777 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ 778 (uint32_t)0x00000000) 779 #endif /* BDMA1 */ 780 781 /** 782 * @brief Return the current DMA Stream half transfer complete flag. 783 * @param __HANDLE__: DMA handle 784 * @retval The specified half transfer complete flag index. 785 */ 786 #if defined(BDMA1) 787 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 788 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 789 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 790 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 791 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 792 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 793 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 794 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 795 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 796 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 797 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 798 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 799 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 800 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ 801 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ 802 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ 803 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ 804 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\ 805 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\ 806 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\ 807 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\ 808 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\ 809 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\ 810 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\ 811 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\ 812 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\ 813 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\ 814 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\ 815 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\ 816 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\ 817 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\ 818 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\ 819 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\ 820 (uint32_t)0x00000000) 821 #else 822 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 823 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 824 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 825 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 826 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 827 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 828 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 829 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 830 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 831 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 832 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 833 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 834 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 835 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ 836 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ 837 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ 838 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ 839 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\ 840 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\ 841 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\ 842 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\ 843 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\ 844 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\ 845 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ 846 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ 847 (uint32_t)0x00000000) 848 #endif /* BDMA1 */ 849 850 /** 851 * @brief Return the current DMA Stream transfer error flag. 852 * @param __HANDLE__: DMA handle 853 * @retval The specified transfer error flag index. 854 */ 855 #if defined(BDMA1) 856 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 857 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 858 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 859 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 860 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 861 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 862 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 863 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 864 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 865 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 866 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 867 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 868 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 869 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ 870 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ 871 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ 872 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ 873 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\ 874 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\ 875 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\ 876 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\ 877 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\ 878 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\ 879 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\ 880 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\ 881 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\ 882 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\ 883 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\ 884 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\ 885 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\ 886 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\ 887 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\ 888 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\ 889 (uint32_t)0x00000000) 890 #else 891 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 892 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 893 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 894 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 895 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 896 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 897 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 898 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 899 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 900 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 901 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 902 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 903 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 904 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ 905 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ 906 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ 907 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ 908 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\ 909 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\ 910 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\ 911 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\ 912 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\ 913 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\ 914 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ 915 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ 916 (uint32_t)0x00000000) 917 #endif /* BDMA1 */ 918 919 /** 920 * @brief Return the current DMA Stream FIFO error flag. 921 * @param __HANDLE__: DMA handle 922 * @retval The specified FIFO error flag index. 923 */ 924 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 925 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 926 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 927 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 928 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 929 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 930 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 931 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 932 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 933 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 934 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 935 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 936 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 937 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ 938 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ 939 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ 940 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ 941 (uint32_t)0x00000000) 942 943 /** 944 * @brief Return the current DMA Stream direct mode error flag. 945 * @param __HANDLE__: DMA handle 946 * @retval The specified direct mode error flag index. 947 */ 948 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 949 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 950 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 951 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 952 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 953 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 954 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 955 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 956 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 957 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 958 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 959 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 960 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 961 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ 962 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ 963 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ 964 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ 965 (uint32_t)0x00000000) 966 967 /** 968 * @brief Returns the current BDMA Channel Global interrupt flag. 969 * @param __HANDLE__: DMA handle 970 * @retval The specified transfer error flag index. 971 */ 972 #if defined(BDMA1) 973 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 974 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\ 975 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\ 976 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\ 977 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\ 978 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\ 979 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\ 980 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\ 981 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\ 982 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\ 983 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\ 984 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\ 985 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\ 986 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\ 987 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\ 988 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\ 989 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\ 990 (uint32_t)0x00000000) 991 #else 992 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 993 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ 994 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ 995 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\ 996 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\ 997 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\ 998 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\ 999 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ 1000 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ 1001 (uint32_t)0x00000000) 1002 #endif /* BDMA1 */ 1003 1004 /** 1005 * @brief Get the DMA Stream pending flags. 1006 * @param __HANDLE__: DMA handle 1007 * @param __FLAG__: Get the specified flag. 1008 * This parameter can be any combination of the following values: 1009 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 1010 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 1011 * @arg DMA_FLAG_TEIFx: Transfer error flag. 1012 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 1013 * @arg DMA_FLAG_FEIFx: FIFO error flag. 1014 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 1015 * @retval The state of FLAG (SET or RESET). 1016 */ 1017 #if defined(BDMA1) 1018 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 1019 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\ 1020 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\ 1021 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\ 1022 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\ 1023 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 1024 #else 1025 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 1026 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ 1027 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 1028 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 1029 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 1030 #endif /* BDMA1 */ 1031 1032 /** 1033 * @brief Clear the DMA Stream pending flags. 1034 * @param __HANDLE__: DMA handle 1035 * @param __FLAG__: specifies the flag to clear. 1036 * This parameter can be any combination of the following values: 1037 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 1038 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 1039 * @arg DMA_FLAG_TEIFx: Transfer error flag. 1040 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 1041 * @arg DMA_FLAG_FEIFx: FIFO error flag. 1042 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 1043 * @retval None 1044 */ 1045 #if defined(BDMA1) 1046 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1047 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\ 1048 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\ 1049 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 1050 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 1051 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 1052 #else 1053 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1054 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ 1055 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 1056 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 1057 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 1058 #endif /* BDMA1 */ 1059 1060 #define DMA_TO_BDMA_IT(__DMA_IT__) \ 1061 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ 1062 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\ 1063 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ 1064 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\ 1065 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\ 1066 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\ 1067 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\ 1068 (uint32_t)0x00000000) 1069 1070 1071 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1072 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) 1073 1074 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 1075 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) 1076 1077 /** 1078 * @brief Enable the specified DMA Stream interrupts. 1079 * @param __HANDLE__: DMA handle 1080 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 1081 * This parameter can be one of the following values: 1082 * @arg DMA_IT_TC: Transfer complete interrupt mask. 1083 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 1084 * @arg DMA_IT_TE: Transfer error interrupt mask. 1085 * @arg DMA_IT_FE: FIFO error interrupt mask. 1086 * @arg DMA_IT_DME: Direct mode error interrupt. 1087 * @retval None 1088 */ 1089 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ 1090 (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ 1091 (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) 1092 1093 1094 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) 1095 1096 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 1097 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) 1098 1099 /** 1100 * @brief Disable the specified DMA Stream interrupts. 1101 * @param __HANDLE__: DMA handle 1102 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 1103 * This parameter can be one of the following values: 1104 * @arg DMA_IT_TC: Transfer complete interrupt mask. 1105 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 1106 * @arg DMA_IT_TE: Transfer error interrupt mask. 1107 * @arg DMA_IT_FE: FIFO error interrupt mask. 1108 * @arg DMA_IT_DME: Direct mode error interrupt. 1109 * @retval None 1110 */ 1111 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ 1112 (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ 1113 (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) 1114 1115 1116 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) 1117 1118 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 1119 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ 1120 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) 1121 1122 /** 1123 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 1124 * @param __HANDLE__: DMA handle 1125 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 1126 * This parameter can be one of the following values: 1127 * @arg DMA_IT_TC: Transfer complete interrupt mask. 1128 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 1129 * @arg DMA_IT_TE: Transfer error interrupt mask. 1130 * @arg DMA_IT_FE: FIFO error interrupt mask. 1131 * @arg DMA_IT_DME: Direct mode error interrupt. 1132 * @retval The state of DMA_IT. 1133 */ 1134 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 1135 (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ 1136 (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) 1137 1138 /** 1139 * @brief Writes the number of data units to be transferred on the DMA Stream. 1140 * @param __HANDLE__: DMA handle 1141 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) 1142 * Number of data items depends only on the Peripheral data format. 1143 * 1144 * @note If Peripheral data format is Bytes: number of data units is equal 1145 * to total number of bytes to be transferred. 1146 * 1147 * @note If Peripheral data format is Half-Word: number of data units is 1148 * equal to total number of bytes to be transferred / 2. 1149 * 1150 * @note If Peripheral data format is Word: number of data units is equal 1151 * to total number of bytes to be transferred / 4. 1152 * 1153 * @retval The number of remaining data units in the current DMAy Streamx transfer. 1154 */ 1155 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 1156 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\ 1157 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) 1158 1159 /** 1160 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 1161 * @param __HANDLE__: DMA handle 1162 * 1163 * @retval The number of remaining data units in the current DMA Stream transfer. 1164 */ 1165 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ 1166 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\ 1167 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) 1168 1169 /** 1170 * @} 1171 */ 1172 1173 /* Include DMA HAL Extension module */ 1174 #include "stm32h7xx_hal_dma_ex.h" 1175 1176 /* Exported functions --------------------------------------------------------*/ 1177 1178 /** @defgroup DMA_Exported_Functions DMA Exported Functions 1179 * @brief DMA Exported functions 1180 * @{ 1181 */ 1182 1183 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 1184 * @brief Initialization and de-initialization functions 1185 * @{ 1186 */ 1187 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 1188 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 1194 * @brief I/O operation functions 1195 * @{ 1196 */ 1197 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 1198 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 1199 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 1200 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 1201 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 1202 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 1203 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 1204 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 1205 1206 /** 1207 * @} 1208 */ 1209 1210 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 1211 * @brief Peripheral State functions 1212 * @{ 1213 */ 1214 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 1215 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 1216 /** 1217 * @} 1218 */ 1219 /** 1220 * @} 1221 */ 1222 /* Private Constants -------------------------------------------------------------*/ 1223 /** @defgroup DMA_Private_Constants DMA Private Constants 1224 * @brief DMA private defines and constants 1225 * @{ 1226 */ 1227 /** 1228 * @} 1229 */ 1230 1231 /* Private types -------------------------------------------------------------*/ 1232 /** @defgroup DMA_Private_Types DMA Private Types 1233 * @{ 1234 */ 1235 /** 1236 * @} 1237 */ 1238 1239 /* Private macros ------------------------------------------------------------*/ 1240 /** @defgroup DMA_Private_Macros DMA Private Macros 1241 * @brief DMA private macros 1242 * @{ 1243 */ 1244 1245 #if defined(TIM24) 1246 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG)) 1247 #elif defined(ADC3) 1248 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) 1249 #else 1250 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) 1251 #endif /* TIM24 */ 1252 1253 #if defined(ADC3) 1254 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) 1255 #else 1256 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) 1257 #endif /* ADC3 */ 1258 1259 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 1260 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 1261 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 1262 1263 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 1264 1265 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 1266 ((STATE) == DMA_PINC_DISABLE)) 1267 1268 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 1269 ((STATE) == DMA_MINC_DISABLE)) 1270 1271 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 1272 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 1273 ((SIZE) == DMA_PDATAALIGN_WORD)) 1274 1275 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 1276 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 1277 ((SIZE) == DMA_MDATAALIGN_WORD )) 1278 1279 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 1280 ((MODE) == DMA_CIRCULAR) || \ 1281 ((MODE) == DMA_PFCTRL) || \ 1282 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ 1283 ((MODE) == DMA_DOUBLE_BUFFER_M1)) 1284 1285 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 1286 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 1287 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 1288 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 1289 1290 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 1291 ((STATE) == DMA_FIFOMODE_ENABLE)) 1292 1293 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 1294 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 1295 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 1296 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 1297 1298 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 1299 ((BURST) == DMA_MBURST_INC4) || \ 1300 ((BURST) == DMA_MBURST_INC8) || \ 1301 ((BURST) == DMA_MBURST_INC16)) 1302 1303 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 1304 ((BURST) == DMA_PBURST_INC4) || \ 1305 ((BURST) == DMA_PBURST_INC8) || \ 1306 ((BURST) == DMA_PBURST_INC16)) 1307 /** 1308 * @} 1309 */ 1310 1311 /* Private functions ---------------------------------------------------------*/ 1312 /** @defgroup DMA_Private_Functions DMA Private Functions 1313 * @brief DMA private functions 1314 * @{ 1315 */ 1316 /** 1317 * @} 1318 */ 1319 1320 /** 1321 * @} 1322 */ 1323 1324 /** 1325 * @} 1326 */ 1327 1328 #ifdef __cplusplus 1329 } 1330 #endif 1331 1332 #endif /* STM32H7xx_HAL_DMA_H */ 1333 1334
